drivers/i2c/xilinx_iic/xiic_i.h

   1 /* $Id: xiic_i.h,v 1.1.1.1 2005/04/11 02:50:21 jack Exp $ */
   2 /******************************************************************************
   3 *
   4 *     Author: Xilinx, Inc.
   5 *
   6 *
   7 *     This program is free software; you can redistribute it and/or modify it
   8 *     under the terms of the GNU General Public License as published by the
   9 *     Free Software Foundation; either version 2 of the License, or (at your
  10 *     option) any later version.
  11 *
  12 *
  13 *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
  14 *     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
  15 *     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
  16 *     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
  17 *     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR
  18 *     OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
  19 *     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
  20 *     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
  21 *     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
  22 *     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
  23 *     FITNESS FOR A PARTICULAR PURPOSE.
  24 *
  25 *
  26 *     Xilinx products are not intended for use in life support appliances,
  27 *     devices, or systems. Use in such applications is expressly prohibited.
  28 *
  29 *
  30 *     (c) Copyright 2002 Xilinx Inc.
  31 *     All rights reserved.
  32 *
  33 *
  34 *     You should have received a copy of the GNU General Public License along
  35 *     with this program; if not, write to the Free Software Foundation, Inc.,
  36 *     675 Mass Ave, Cambridge, MA 02139, USA.
  37 *
  38 ******************************************************************************/
  39 /*****************************************************************************/
  40 /**
  41 *
  42 * @file xiic_i.h
  43 *
  44 * This header file contains internal identifiers, which are those shared
  45 * between XIic components.  The identifiers in this file are not intended for
  46 * use external to the driver.
  47 *
  48 * <pre>
  49 * MODIFICATION HISTORY:
  50 *
  51 * Ver   Who  Date     Changes
  52 * ----- ---- -------- -----------------------------------------------
  53 * 1.01a rfp  10/19/01 release
  54 * </pre>
  55 *
  56 ******************************************************************************/
  57
  58 #ifndef XIIC_I_H                /* prevent circular inclusions */
  59 #define XIIC_I_H                /* by using protection macros */
  60
  61 /***************************** Include Files *********************************/
  62
  63 #include "xbasic_types.h"
  64 #include "xstatus.h"
  65
  66 /************************** Constant Definitions *****************************/
  67
  68 /**************************** Type Definitions *******************************/
  69
  70 /***************** Macros (Inline Functions) Definitions *********************/
  71
  72 /******************************************************************************
  73 *
  74 * This macro sends the first byte of the address for a 10 bit address during
  75 * both read and write operations. It takes care of the details to format the
  76 * address correctly.
  77 *
  78 * address = 1111_0xxD   xx = address MSBits
  79 *                        D = Tx direction = 0 = write
  80 *
  81 * @param    SlaveAddress contains the address of the slave to send to.
  82 *
  83 * @param    Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
  84 *
  85 * @return
  86 *
  87 * None.
  88 *
  89 * @note
  90 *
  91 * Signature: void XIic_mSend10BitAddrByte1(u16 SlaveAddress, u8 Operation);
  92 *
  93 ******************************************************************************/
  94 #define XIic_mSend10BitAddrByte1(SlaveAddress, Operation)                  \
  95 {                                                                            \
  96     u8 LocalAddr = (u8)((SlaveAddress) >> 7);                        \
  97     LocalAddr = (LocalAddr & 0xF6) | 0xF0 | (Operation);                     \
  98     XIo_Out8(InstancePtr->BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr);  \
  99 }
 100
 101 /******************************************************************************
 102 *
 103 * This macro sends the second byte of the address for a 10 bit address during
 104 * both read and write operations. It takes care of the details to format the
 105 * address correctly.
 106 *
 107 * @param    SlaveAddress contains the address of the slave to send to.
 108 *
 109 * @return
 110 *
 111 * None.
 112 *
 113 * @note
 114 *
 115 * Signature: void XIic_mSend10BitAddrByte2(u16 SlaveAddress,
 116 *                                            u8 Operation);
 117 *
 118 ******************************************************************************/
 119 #define XIic_mSend10BitAddrByte2(SlaveAddress)                        \
 120     XIo_Out8(InstancePtr->BaseAddress + XIIC_DTR_REG_OFFSET,         \
 121              (u8)(SlaveAddress));
 122
 123 /******************************************************************************
 124 *
 125 * This macro sends the address for a 7 bit address during both read and write
 126 * operations. It takes care of the details to format the address correctly.
 127 *
 128 * @param    SlaveAddress contains the address of the slave to send to.
 129 *
 130 * @param    Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
 131 *
 132 * @return
 133 *
 134 * None.
 135 *
 136 * @note
 137 *
 138 * Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation);
 139 *
 140 ******************************************************************************/
 141 #define XIic_mSend7BitAddr(SlaveAddress, Operation)                          \
 142 {                                                                            \
 143     u8 LocalAddr = (u8)(SlaveAddress << 1);                          \
 144     LocalAddr = (LocalAddr & 0xFE) | (Operation);                            \
 145     XIo_Out8(InstancePtr->BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr);  \
 146 }
 147
 148 /******************************************************************************
 149 *
 150 * This macro disables the specified interrupts in the IPIF interrupt enable
 151 * register.  It is non-destructive in that the register is read and only the
 152 * interrupts specified is changed.
 153 *
 154 * @param    BaseAddress contains the IPIF registers base address.
 155 *
 156 * @param    InterruptMask contains the interrupts to be disabled
 157 *
 158 * @return
 159 *
 160 * None.
 161 *
 162 * @note
 163 *
 164 * Signature: void XIic_mDisableIntr(u32 BaseAddress,
 165 *                                        u32 InterruptMask);
 166 *
 167 ******************************************************************************/
 168 #define XIic_mDisableIntr(BaseAddress, InterruptMask)           \
 169     XIIF_V123B_WRITE_IIER((BaseAddress),                        \
 170         XIIF_V123B_READ_IIER(BaseAddress) & ~(InterruptMask))
 171
 172 /******************************************************************************
 173 *
 174 * This macro enables the specified interrupts in the IPIF interrupt enable
 175 * register.  It is non-destructive in that the register is read and only the
 176 * interrupts specified is changed.
 177 *
 178 * @param    BaseAddress contains the IPIF registers base address.
 179 *
 180 * @param    InterruptMask contains the interrupts to be disabled
 181 *
 182 * @return
 183 *
 184 * None.
 185 *
 186 * @note
 187 *
 188 * Signature: void XIic_mEnableIntr(u32 BaseAddress,
 189 *                                  u32 InterruptMask);
 190 *
 191 ******************************************************************************/
 192 #define XIic_mEnableIntr(BaseAddress, InterruptMask)           \
 193     XIIF_V123B_WRITE_IIER((BaseAddress),                       \
 194         XIIF_V123B_READ_IIER(BaseAddress) | (InterruptMask))
 195
 196 /******************************************************************************
 197 *
 198 * This macro clears the specified interrupt in the IPIF interrupt status
 199 * register.  It is non-destructive in that the register is read and only the
 200 * interrupt specified is cleared.  Clearing an interrupt acknowledges it.
 201 *
 202 * @param    BaseAddress contains the IPIF registers base address.
 203 *
 204 * @param    InterruptMask contains the interrupts to be disabled
 205 *
 206 * @return
 207 *
 208 * None.
 209 *
 210 * @note
 211 *
 212 * Signature: void XIic_mClearIntr(u32 BaseAddress,
 213 *                                 u32 InterruptMask);
 214 *
 215 ******************************************************************************/
 216 #define XIic_mClearIntr(BaseAddress, InterruptMask)                 \
 217     XIIF_V123B_WRITE_IISR((BaseAddress),                            \
 218         XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask))
 219
 220 /******************************************************************************
 221 *
 222 * This macro clears and enables the specified interrupt in the IPIF interrupt
 223 * status and enable registers.  It is non-destructive in that the registers are
 224 * read and only the interrupt specified is modified.
 225 * Clearing an interrupt acknowledges it.
 226 *
 227 * @param    BaseAddress contains the IPIF registers base address.
 228 *
 229 * @param    InterruptMask contains the interrupts to be cleared and enabled
 230 *
 231 * @return
 232 *
 233 * None.
 234 *
 235 * @note
 236 *
 237 * Signature: void XIic_mClearEnableIntr(u32 BaseAddress,
 238 *                                             u32 InterruptMask);
 239 *
 240 ******************************************************************************/
 241 #define XIic_mClearEnableIntr(BaseAddress, InterruptMask)          \
 242 {                                                                       \
 243     XIIF_V123B_WRITE_IISR(BaseAddress,                              \
 244         (XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask)));     \
 245                                                                         \
 246     XIIF_V123B_WRITE_IIER(BaseAddress,                              \
 247         (XIIF_V123B_READ_IIER(BaseAddress) | (InterruptMask)));     \
 248 }
 249
 250 /******************************************************************************
 251 *
 252 * This macro flushes the receive FIFO such that all bytes contained within it
 253 * are discarded.
 254 *
 255 * @param    InstancePtr is a pointer to the IIC instance containing the FIFO
 256 *           to be flushed.
 257 *
 258 * @return
 259 *
 260 * None.
 261 *
 262 * @note
 263 *
 264 * Signature: void XIic_mFlushRxFifo(XIic *InstancePtr);
 265 *
 266 ******************************************************************************/
 267 #define XIic_mFlushRxFifo(InstancePtr)                                     \
 268 {                                                                           \
 269     int LoopCnt;                                                            \
 270     u8 Temp;                                                            \
 271     u8 BytesToRead = XIo_In8(InstancePtr->BaseAddress +              \
 272                                  XIIC_RFO_REG_OFFSET) + 1;                  \
 273     for(LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++)                      \
 274     {                                                                       \
 275         Temp = XIo_In8(InstancePtr->BaseAddress + XIIC_DRR_REG_OFFSET);  \
 276     }                                                                       \
 277 }
 278
 279 /******************************************************************************
 280 *
 281 * This macro flushes the transmit FIFO such that all bytes contained within it
 282 * are discarded.
 283 *
 284 * @param    InstancePtr is a pointer to the IIC instance containing the FIFO
 285 *           to be flushed.
 286 *
 287 * @return
 288 *
 289 * None.
 290 *
 291 * @note
 292 *
 293 * Signature: void XIic_mFlushTxFifo(XIic *InstancePtr);
 294 *
 295 ******************************************************************************/
 296 #define XIic_mFlushTxFifo(InstancePtr);                                    \
 297 {                                                                           \
 298     u8 CntlReg = XIo_In8(InstancePtr->BaseAddress +                  \
 299                              XIIC_CR_REG_OFFSET);                           \
 300     XIo_Out8(InstancePtr->BaseAddress + XIIC_CR_REG_OFFSET,              \
 301              CntlReg | XIIC_CR_TX_FIFO_RESET_MASK);                         \
 302     XIo_Out8(InstancePtr->BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);    \
 303 }
 304
 305 /******************************************************************************
 306 *
 307 * This macro reads the next available received byte from the receive FIFO
 308 * and updates all the data structures to reflect it.
 309 *
 310 * @param    InstancePtr is a pointer to the IIC instance to be operated on.
 311 *
 312 * @return
 313 *
 314 * None.
 315 *
 316 * @note
 317 *
 318 * Signature: void XIic_mReadRecvByte(XIic *InstancePtr);
 319 *
 320 ******************************************************************************/
 321 #define XIic_mReadRecvByte(InstancePtr)                                    \
 322 {                                                                           \
 323     *InstancePtr->RecvBufferPtr++ =                                         \
 324         XIo_In8(InstancePtr->BaseAddress + XIIC_DRR_REG_OFFSET);         \
 325     InstancePtr->RecvByteCount--;                                           \
 326     InstancePtr->Stats.RecvBytes++;                                         \
 327 }
 328
 329 /******************************************************************************
 330 *
 331 * This macro writes the next byte to be sent to the transmit FIFO
 332 * and updates all the data structures to reflect it.
 333 *
 334 * @param    InstancePtr is a pointer to the IIC instance to be operated on.
 335 *
 336 * @return
 337 *
 338 * None.
 339 *
 340 * @note
 341 *
 342 * Signature: void XIic_mWriteSendByte(XIic *InstancePtr);
 343 *
 344 ******************************************************************************/
 345 #define XIic_mWriteSendByte(InstancePtr)                                   \
 346 {                                                                           \
 347     XIo_Out8(InstancePtr->BaseAddress + XIIC_DTR_REG_OFFSET,             \
 348         *InstancePtr->SendBufferPtr++);                                     \
 349     InstancePtr->SendByteCount--;                                           \
 350     InstancePtr->Stats.SendBytes++;                                         \
 351 }
 352
 353 /******************************************************************************
 354 *
 355 * This macro sets up the control register for a master receive operation.
 356 * A write is necessary if a 10 bit operation is being performed.
 357 *
 358 * @param    InstancePtr is a pointer to the IIC instance to be operated on.
 359 *
 360 * @param    ControlRegister contains the contents of the IIC device control
 361 *           register
 362 *
 363 * @param    ByteCount contains the number of bytes to be received for the
 364 *           master receive operation
 365 *
 366 * @return
 367 *
 368 * None.
 369 *
 370 * @note
 371 *
 372 * Signature: void XIic_mSetControlRegister(XIic *InstancePtr,
 373 *                                           u8 ControlRegister,
 374 *                                           int ByteCount);
 375 *
 376 ******************************************************************************/
 377 #define XIic_mSetControlRegister(InstancePtr, ControlRegister, ByteCount)  \
 378 {                                                                           \
 379     (ControlRegister) &= ~(XIIC_CR_NO_ACK_MASK | XIIC_CR_DIR_IS_TX_MASK);   \
 380     if (InstancePtr->Options & XII_SEND_10_BIT_OPTION)                      \
 381     {                                                                       \
 382         (ControlRegister) |= XIIC_CR_DIR_IS_TX_MASK;                        \
 383     }                                                                       \
 384     else                                                                    \
 385     {                                                                       \
 386         if ((ByteCount) == 1)                                               \
 387         {                                                                   \
 388             (ControlRegister) |= XIIC_CR_NO_ACK_MASK;                       \
 389         }                                                                   \
 390     }                                                                       \
 391 }
 392
 393 /******************************************************************************
 394 *
 395 * This macro enters a critical region by disabling the global interrupt bit
 396 * in the IPIF.
 397 *
 398 * @param    BaseAddress contains the IPIF registers base address.
 399 *
 400 * @return
 401 *
 402 * None.
 403 *
 404 * @note
 405 *
 406 * Signature: void XIic_mEnterCriticalRegion(u32 BaseAddress)
 407 *
 408 ******************************************************************************/
 409 #define XIic_mEnterCriticalRegion(BaseAddress)  \
 410     XIIF_V123B_GINTR_DISABLE(BaseAddress)
 411
 412 /******************************************************************************
 413 *
 414 * This macro exits a critical region by enabling the global interrupt bit
 415 * in the IPIF.
 416 *
 417 * @param    BaseAddress contains the IPIF registers base address.
 418 *
 419 * @return
 420 *
 421 * None.
 422 *
 423 * @note
 424 *
 425 * Signature: void XIic_mExitCriticalRegion(u32 BaseAddress)
 426 *
 427 ******************************************************************************/
 428 #define XIic_mExitCriticalRegion(BaseAddress)  \
 429     XIIF_V123B_GINTR_ENABLE(BaseAddress)
 430
 431 /******************************************************************************
 432 *
 433 * This macro clears the statistics of an instance such that it can be common
 434 * such that some parts of the driver may be optional.
 435 *
 436 * @param    InstancePtr is a pointer to the IIC instance to be operated on.
 437 *
 438 * @return
 439 *
 440 * None.
 441 *
 442 * @note
 443 *
 444 * Signature: void XIIC_CLEAR_STATS(XIic *InstancePtr)
 445 *
 446 ******************************************************************************/
 447 #define XIIC_CLEAR_STATS(InstancePtr)                                   \
 448 {                                                                       \
 449     u8 NumBytes;                                                    \
 450     u8 *DestPtr;                                                    \
 451                                                                         \
 452     DestPtr = (u8 *)&InstancePtr->Stats;                            \
 453     for (NumBytes = 0; NumBytes < sizeof(XIicStats); NumBytes++)        \
 454     {                                                                   \
 455         *DestPtr++ = 0;                                                 \
 456     }                                                                   \
 457 }
 458
 459 /************************** Function Prototypes ******************************/
 460
 461 extern XIic_Config XIic_ConfigTable[];
 462
 463 /* The following variables are shared across files of the driver and
 464  * are function pointers that are necessary to break dependencies allowing
 465  * optional parts of the driver to be used without condition compilation
 466  */
 467 extern void (*XIic_AddrAsSlaveFuncPtr) (XIic * InstancePtr);
 468 extern void (*XIic_NotAddrAsSlaveFuncPtr) (XIic * InstancePtr);
 469 extern void (*XIic_RecvSlaveFuncPtr) (XIic * InstancePtr);
 470 extern void (*XIic_SendSlaveFuncPtr) (XIic * InstancePtr);
 471 extern void (*XIic_RecvMasterFuncPtr) (XIic * InstancePtr);
 472 extern void (*XIic_SendMasterFuncPtr) (XIic * InstancePtr);
 473 extern void (*XIic_ArbLostFuncPtr) (XIic * InstancePtr);
 474 extern void (*XIic_BusNotBusyFuncPtr) (XIic * InstancePtr);
 475
 476 void XIic_TransmitFifoFill(XIic * InstancePtr, int Role);
 477
 478 #endif                          /* end of protection macro */