2 * dv1394-private.h - DV input/output over IEEE 1394 on OHCI chips
3 * Copyright (C)2001 Daniel Maas <dmaas@dcine.com>
4 * receive, proc_fs by Dan Dennedy <dan@dennedy.org>
7 * video1394.h - driver for OHCI 1394 boards
8 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
9 * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software Foundation,
23 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #ifndef _DV_1394_PRIVATE_H
27 #define _DV_1394_PRIVATE_H
31 #include <linux/pci.h>
32 #include <asm/scatterlist.h>
34 /* data structures private to the dv1394 driver */
35 /* none of this is exposed to user-space */
39 the 8-byte CIP (Common Isochronous Packet) header that precedes
40 each packet of DV data.
42 See the IEC 61883 standard.
45 struct CIP_header { unsigned char b[8]; };
47 static inline void fill_cip_header(struct CIP_header *cip,
48 unsigned char source_node_id,
49 unsigned long counter,
50 enum pal_or_ntsc format,
51 unsigned long timestamp)
53 cip->b[0] = source_node_id;
54 cip->b[1] = 0x78; /* packet size in quadlets (480/4) - even for empty packets! */
58 cip->b[4] = 0x80; /* const */
69 cip->b[6] = timestamp >> 8;
70 cip->b[7] = timestamp & 0xFF;
76 DMA commands used to program the OHCI's DMA engine
78 See the Texas Instruments OHCI 1394 chipset documentation.
81 struct output_more_immediate { u32 q[8]; };
82 struct output_more { u32 q[4]; };
83 struct output_last { u32 q[4]; };
84 struct input_more { u32 q[4]; };
85 struct input_last { u32 q[4]; };
89 static inline void fill_output_more_immediate(struct output_more_immediate *omi,
91 unsigned char channel,
92 unsigned char sync_tag,
93 unsigned int payload_size)
95 omi->q[0] = cpu_to_le32(0x02000000 | 8); /* OUTPUT_MORE_IMMEDIATE; 8 is the size of the IT header */
100 /* IT packet header */
101 omi->q[4] = cpu_to_le32( (0x0 << 16) /* DMA_SPEED_100 */
104 | (TCODE_ISO_DATA << 4)
107 /* reserved field; mimic behavior of my Sony DSR-40 */
108 omi->q[5] = cpu_to_le32((payload_size << 16) | (0x7F << 8) | 0xA0);
114 static inline void fill_output_more(struct output_more *om,
115 unsigned int data_size,
116 unsigned long data_phys_addr)
118 om->q[0] = cpu_to_le32(data_size);
119 om->q[1] = cpu_to_le32(data_phys_addr);
124 static inline void fill_output_last(struct output_last *ol,
127 unsigned int data_size,
128 unsigned long data_phys_addr)
131 temp |= 1 << 28; /* OUTPUT_LAST */
133 if(want_timestamp) /* controller will update timestamp at DMA time */
139 temp |= 3 << 18; /* must take branch */
142 ol->q[0] = cpu_to_le32(temp);
143 ol->q[1] = cpu_to_le32(data_phys_addr);
150 static inline void fill_input_more(struct input_more *im,
152 unsigned int data_size,
153 unsigned long data_phys_addr)
155 u32 temp = 2 << 28; /* INPUT_MORE */
156 temp |= 8 << 24; /* s = 1, update xferStatus and resCount */
158 temp |= 0 << 20; /* interrupts, i=0 in packet-per-buffer mode */
159 temp |= 0x0 << 16; /* disable branch to address for packet-per-buffer mode */
160 /* disable wait on sync field, not used in DV :-( */
163 im->q[0] = cpu_to_le32(temp);
164 im->q[1] = cpu_to_le32(data_phys_addr);
165 im->q[2] = 0; /* branchAddress and Z not use in packet-per-buffer mode */
166 im->q[3] = 0; /* xferStatus & resCount, resCount must be initialize to data_size */
169 static inline void fill_input_last(struct input_last *il,
170 unsigned int data_size,
171 unsigned long data_phys_addr)
173 u32 temp = 3 << 28; /* INPUT_LAST */
174 temp |= 8 << 24; /* s = 1, update xferStatus and resCount */
175 temp |= 3 << 20; /* enable interrupts */
176 temp |= 0xC << 16; /* enable branch to address */
177 /* disable wait on sync field, not used in DV :-( */
180 il->q[0] = cpu_to_le32(temp);
181 il->q[1] = cpu_to_le32(data_phys_addr);
182 il->q[2] = cpu_to_le32(1); /* branchAddress (filled in later) and Z = 1 descriptor in next block */
183 il->q[3] = cpu_to_le32(data_size); /* xferStatus & resCount, resCount must be initialize to data_size */
189 A "DMA descriptor block" consists of several contiguous DMA commands.
190 struct DMA_descriptor_block encapsulates all of the commands necessary
191 to send one packet of DV data.
193 There are three different types of these blocks:
195 1) command to send an empty packet (CIP header only, no DV data):
197 OUTPUT_MORE-Immediate <-- contains the iso header in-line
198 OUTPUT_LAST <-- points to the CIP header
200 2) command to send a full packet when the DV data payload does NOT
201 cross a page boundary:
203 OUTPUT_MORE-Immediate <-- contains the iso header in-line
204 OUTPUT_MORE <-- points to the CIP header
205 OUTPUT_LAST <-- points to entire DV data payload
207 3) command to send a full packet when the DV payload DOES cross
210 OUTPUT_MORE-Immediate <-- contains the iso header in-line
211 OUTPUT_MORE <-- points to the CIP header
212 OUTPUT_MORE <-- points to first part of DV data payload
213 OUTPUT_LAST <-- points to second part of DV data payload
215 This struct describes all three block types using unions.
217 !!! It is vital that an even number of these descriptor blocks fit on one
218 page of memory, since a block cannot cross a page boundary !!!
222 struct DMA_descriptor_block {
226 /* iso header, common to all output block types */
227 struct output_more_immediate omi;
232 struct output_last ol; /* CIP header */
237 struct output_more om; /* CIP header */
240 /* payload does not cross page boundary */
242 struct output_last ol; /* data payload */
245 /* payload crosses page boundary */
247 struct output_more om; /* data payload */
248 struct output_last ol; /* data payload */
257 struct input_last il;
262 /* ensure that PAGE_SIZE % sizeof(struct DMA_descriptor_block) == 0
263 by padding out to 128 bytes */
268 /* struct frame contains all data associated with one frame in the
269 ringbuffer these are allocated when the DMA context is initialized
270 do_dv1394_init(). They are re-used after the card finishes
271 transmitting the frame. */
273 struct video_card; /* forward declaration */
277 /* points to the struct video_card that owns this frame */
278 struct video_card *video;
280 /* index of this frame in video_card->frames[] */
281 unsigned int frame_num;
283 /* FRAME_CLEAR - DMA program not set up, waiting for data
284 FRAME_READY - DMA program written, ready to transmit
286 Changes to these should be locked against the interrupt
293 /* whether this frame has been DMA'ed already; used only from
294 the IRQ handler to determine whether the frame can be reset */
298 /* kernel virtual pointer to the start of this frame's data in
299 the user ringbuffer. Use only for CPU access; to get the DMA
300 bus address you must go through the video->user_dma mapping */
303 /* Max # of packets per frame */
304 /* 320 is enough for NTSC, need to check what PAL is */
305 #define MAX_PACKETS 500
308 /* a PAGE_SIZE memory pool for allocating CIP headers
309 !header_pool must be aligned to PAGE_SIZE! */
310 struct CIP_header *header_pool;
311 dma_addr_t header_pool_dma;
314 /* a physically contiguous memory pool for allocating DMA
315 descriptor blocks; usually around 64KB in size
316 !descriptor_pool must be aligned to PAGE_SIZE! */
317 struct DMA_descriptor_block *descriptor_pool;
318 dma_addr_t descriptor_pool_dma;
319 unsigned long descriptor_pool_size;
322 /* # of packets allocated for this frame */
323 unsigned int n_packets;
326 /* below are several pointers (kernel virtual addresses, not
327 DMA bus addresses) to parts of the DMA program. These are
328 set each time the DMA program is written in
329 frame_prepare(). They are used later on, e.g. from the
330 interrupt handler, to check the status of the frame */
332 /* points to status/timestamp field of first DMA packet */
333 /* (we'll check it later to monitor timestamp accuracy) */
334 u32 *frame_begin_timestamp;
336 /* the timestamp we assigned to the first packet in the frame */
337 u32 assigned_timestamp;
339 /* pointer to the first packet's CIP header (where the timestamp goes) */
340 struct CIP_header *cip_syt1;
342 /* pointer to the second packet's CIP header
343 (only set if the first packet was empty) */
344 struct CIP_header *cip_syt2;
346 /* in order to figure out what caused an interrupt,
347 store pointers to the status fields of the two packets
348 that can cause interrupts. We'll check these from the
351 u32 *mid_frame_timestamp;
352 u32 *frame_end_timestamp;
354 /* branch address field of final packet. This is effectively
355 the "tail" in the chain of DMA descriptor blocks.
356 We will fill it with the address of the first DMA descriptor
357 block in the subsequent frame, once it is ready.
359 u32 *frame_end_branch;
361 /* the number of descriptors in the first descriptor block
362 of the frame. Needed to start DMA */
363 int first_n_descriptors;
374 unsigned char data[480];
375 unsigned char padding[16]; /* force struct size =512 for page alignment */
379 /* allocate/free a frame */
380 static struct frame* frame_new(unsigned int frame_num, struct video_card *video);
381 static void frame_delete(struct frame *f);
383 /* reset f so that it can be used again */
384 static void frame_reset(struct frame *f);
387 /* structure for bookkeeping of a large non-physically-contiguous DMA buffer */
390 unsigned int n_pages;
391 unsigned int n_dma_pages;
392 struct scatterlist *sglist;
395 /* return the DMA bus address of the byte with the given offset
396 relative to the beginning of the dma_region */
398 static inline dma_addr_t dma_offset_to_bus(struct dma_region *dma, unsigned long offset)
401 struct scatterlist *sg;
403 for(i = 0, sg = &dma->sglist[0]; i < dma->n_dma_pages; i++, sg++) {
404 if(offset < sg_dma_len(sg)) {
405 return sg_dma_address(sg) + offset;
407 offset -= sg_dma_len(sg);
410 printk(KERN_ERR "dv1394: dma_offset_to_bus failed for offset %lu!\n", offset);
415 /* struct video_card contains all data associated with one instance
425 /* ohci card to which this instance corresponds */
426 struct ti_ohci *ohci;
428 /* OHCI card id; the link between the VFS inode and a specific video_card
429 (essentially the device minor number) */
432 /* entry in dv1394_cards */
433 struct list_head list;
435 /* handle to /dev/ieee1394/dv/N, NULL if devfs not in use */
436 devfs_handle_t devfs_handle;
438 /* OHCI card IT DMA context number, -1 if not in use */
440 struct ohci1394_iso_tasklet it_tasklet;
442 /* register offsets for current IT DMA context, 0 if not in use */
443 u32 ohci_IsoXmitContextControlSet;
444 u32 ohci_IsoXmitContextControlClear;
445 u32 ohci_IsoXmitCommandPtr;
447 /* OHCI card IR DMA context number, -1 if not in use */
448 struct ohci1394_iso_tasklet ir_tasklet;
451 /* register offsets for current IR DMA context, 0 if not in use */
452 u32 ohci_IsoRcvContextControlSet;
453 u32 ohci_IsoRcvContextControlClear;
454 u32 ohci_IsoRcvCommandPtr;
455 u32 ohci_IsoRcvContextMatch;
458 /* CONCURRENCY CONTROL */
460 /* there are THREE levels of locking associated with video_card. */
463 1) the 'open' flag - this prevents more than one process from
464 opening the device. (the driver currently assumes only one opener).
465 This is a regular int, but use test_and_set_bit() (on bit zero)
471 2) the spinlock - this provides mutual exclusion between the interrupt
472 handler and process-context operations. Generally you must take the
473 spinlock under the following conditions:
474 1) DMA (and hence the interrupt handler) may be running
476 2) you need to operate on the video_card, especially active_frame
478 It is OK to play with video_card without taking the spinlock if
479 you are certain that DMA is not running. Even if DMA is running,
480 it is OK to *read* active_frame with the lock, then drop it
481 immediately. This is safe because the interrupt handler will never
482 advance active_frame onto a frame that is not READY (and the spinlock
483 must be held while marking a frame READY).
485 spinlock is also used to protect ohci_it_ctx and ohci_ir_ctx,
486 which can be accessed from both process and interrupt context
491 3) the sleeping semaphore 'sem' - this is used from process context only,
492 to serialize various operations on the video_card. Even though only one
493 open() is allowed, we still need to prevent multiple threads of execution
494 from entering calls like read, write, ioctl, etc.
496 I honestly can't think of a good reason to use dv1394 from several threads
497 at once, but we need to serialize anyway to prevent oopses =).
499 NOTE: if you need both spinlock and sem, take sem first to avoid deadlock!
501 struct semaphore sem;
503 /* people waiting for buffer space, please form a line here... */
504 wait_queue_head_t waitq;
506 /* support asynchronous I/O signals (SIGIO) */
507 struct fasync_struct *fasync;
509 /* the large, non-contiguous (rvmalloc()) ringbuffer for DV
510 data, exposed to user-space via mmap() */
511 unsigned char *user_buf;
512 unsigned long user_buf_size;
513 struct dma_region user_dma;
515 /* next byte in the ringbuffer that a write() call will fill */
518 struct frame *frames[DV1394_MAX_FRAMES];
520 /* n_frames also serves as an indicator that this struct video_card is
521 intialized and ready to run DMA buffers */
525 /* this is the frame that is currently "owned" by the OHCI DMA controller
526 (set to -1 iff DMA is not running)
528 ! must lock against the interrupt handler when accessing it !
532 Only the interrupt handler may change active_frame if DMA
533 is running; if not, process may change it
535 If the next frame is READY, the interrupt handler will advance
536 active_frame when the current frame is finished.
538 If the next frame is CLEAR, the interrupt handler will re-transmit
539 the current frame, and the dropped_frames counter will be incremented.
541 The interrupt handler will NEVER advance active_frame to a
542 frame that is not READY.
548 /* the same locking rules apply to these three fields also: */
550 /* altered ONLY from process context. Must check first_clear_frame->state;
551 if it's READY, that means the ringbuffer is full with READY frames;
552 if it's CLEAR, that means one or more ringbuffer frames are CLEAR */
553 unsigned int first_clear_frame;
555 /* altered both by process and interrupt */
556 unsigned int n_clear_frames;
558 /* only altered by the interrupt */
559 unsigned int dropped_frames;
563 /* the CIP accumulator and continuity counter are properties
564 of the DMA stream as a whole (not a single frame), so they
565 are stored here in the video_card */
567 unsigned long cip_accum;
568 unsigned long cip_n, cip_d;
569 unsigned int syt_offset;
570 unsigned int continuity_counter;
572 enum pal_or_ntsc pal_or_ntsc;
574 /* redundant, but simplifies the code somewhat */
575 unsigned int frame_size; /* in bytes */
577 /* the isochronous channel to use, -1 if video card is inactive */
581 /* physically contiguous packet ringbuffer for receive */
582 #define MAX_PACKET_BUFFER 30
583 struct packet *packet_buffer;
584 dma_addr_t packet_buffer_dma;
585 unsigned long packet_buffer_size;
587 unsigned int current_packet;
588 int first_frame; /* received first start frame marker? */
593 if the video_card is not initialized, then the ONLY fields that are valid are:
599 static inline int video_card_initialized(struct video_card *v)
601 return v->n_frames > 0;
604 static int do_dv1394_init(struct video_card *video, struct dv1394_init *init);
605 static int do_dv1394_init_default(struct video_card *video);
606 static int do_dv1394_shutdown(struct video_card *video, int free_user_buf);
609 /* NTSC empty packet rate accurate to within 0.01%,
610 calibrated against a Sony DSR-40 DVCAM deck */
612 #define CIP_N_NTSC 68000000
613 #define CIP_D_NTSC 1068000000
618 #endif /* _DV_1394_PRIVATE_H */