1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000-2002 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
11 Please refer to Documentation/DocBook/tulip.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
17 #define DRV_NAME "tulip"
18 #define DRV_VERSION "0.9.15-pre12"
19 #define DRV_RELDATE "Aug 9, 2002"
21 #include <linux/config.h>
22 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/crc32.h>
31 #include <asm/unaligned.h>
32 #include <asm/uaccess.h>
38 static char version[] __devinitdata =
39 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
42 /* A few user-configurable values. */
44 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
45 static unsigned int max_interrupt_work = 25;
48 /* Used to pass the full-duplex flag, etc. */
49 static int full_duplex[MAX_UNITS];
50 static int options[MAX_UNITS];
51 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
53 /* The possible media types that can be set in options[] are: */
54 const char * const medianame[32] = {
55 "10baseT", "10base2", "AUI", "100baseTx",
56 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
57 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
58 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
59 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
60 "","","","", "","","","", "","","","Transceiver reset",
63 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
64 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
65 || defined(__sparc_) || defined(__ia64__) \
66 || defined(__sh__) || defined(__mips__)
67 static int rx_copybreak = 1518;
69 static int rx_copybreak = 100;
73 Set the bus performance register.
74 Typical: Set 16 longword cache alignment, no burst limit.
75 Cache alignment bits 15:14 Burst length 13:8
76 0000 No alignment 0x00000000 unlimited 0800 8 longwords
77 4000 8 longwords 0100 1 longword 1000 16 longwords
78 8000 16 longwords 0200 2 longwords 2000 32 longwords
79 C000 32 longwords 0400 4 longwords
80 Warning: many older 486 systems are broken and require setting 0x00A04800
81 8 longword cache alignment, 8 longword burst.
82 ToDo: Non-Intel setting could be better.
85 #if defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
86 static int csr0 = 0x01A00000 | 0xE000;
87 #elif defined(__i386__) || defined(__powerpc__)
88 static int csr0 = 0x01A00000 | 0x8000;
89 #elif defined(__sparc__) || defined(__hppa__)
90 /* The UltraSparc PCI controllers will disconnect at every 64-byte
91 * crossing anyways so it makes no sense to tell Tulip to burst
94 static int csr0 = 0x01A00000 | 0x9000;
95 #elif defined(__arm__) || defined(__sh__)
96 static int csr0 = 0x01A00000 | 0x4800;
97 #elif defined(__mips__)
98 static int csr0 = 0x00200000 | 0x4000;
100 #warning Processor architecture undefined!
101 static int csr0 = 0x00A00000 | 0x4800;
104 /* Operational parameters that usually are not changed. */
105 /* Time in jiffies before concluding the transmitter is hung. */
106 #define TX_TIMEOUT (4*HZ)
109 MODULE_AUTHOR("The Linux Kernel Team");
110 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
111 MODULE_LICENSE("GPL");
112 MODULE_PARM(tulip_debug, "i");
113 MODULE_PARM(max_interrupt_work, "i");
114 MODULE_PARM(rx_copybreak, "i");
115 MODULE_PARM(csr0, "i");
116 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
117 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
119 #define PFX DRV_NAME ": "
122 int tulip_debug = TULIP_DEBUG;
130 * This table use during operation for capabilities and media timer.
132 * It is indexed via the values in 'enum chips'
135 struct tulip_chip_table tulip_tbl[] = {
137 { "Digital DC21040 Tulip", 128, 0x0001ebef, 0, tulip_timer },
140 { "Digital DC21041 Tulip", 128, 0x0001ebef,
141 HAS_MEDIA_TABLE | HAS_NWAY, tulip_timer },
144 { "Digital DS21140 Tulip", 128, 0x0001ebef,
145 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer },
147 /* DC21142, DC21143 */
148 { "Digital DS21143 Tulip", 128, 0x0801fbff,
149 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
150 | HAS_INTR_MITIGATION | HAS_PCI_MWI, t21142_timer },
153 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
154 HAS_MII | HAS_PNICNWAY, pnic_timer },
157 { "Macronix 98713 PMAC", 128, 0x0001ebef,
158 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
161 { "Macronix 98715 PMAC", 256, 0x0001ebef,
162 HAS_MEDIA_TABLE, mxic_timer },
165 { "Macronix 98725 PMAC", 256, 0x0001ebef,
166 HAS_MEDIA_TABLE, mxic_timer },
169 { "ASIX AX88140", 128, 0x0001fbff,
170 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
171 | IS_ASIX, tulip_timer },
174 { "Lite-On PNIC-II", 256, 0x0801fbff,
175 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer },
178 { "ADMtek Comet", 256, 0x0001abef,
179 MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer },
182 { "Compex 9881 PMAC", 128, 0x0001ebef,
183 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
186 { "Intel DS21145 Tulip", 128, 0x0801fbff,
187 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
188 | HAS_NWAY | HAS_PCI_MWI, t21142_timer },
191 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
192 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
196 { "Conexant LANfinity", 256, 0x0001ebef,
197 HAS_MII, tulip_timer },
201 static struct pci_device_id tulip_pci_tbl[] __devinitdata = {
202 { 0x1011, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21040 },
203 { 0x1011, 0x0014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21041 },
204 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
205 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
206 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
207 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
208 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
209 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
210 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
211 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
212 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
213 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
214 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
215 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
216 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
217 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
218 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
219 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
220 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
221 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
223 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
224 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
225 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
226 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
228 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
233 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
234 { } /* terminate list */
236 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
239 /* A full-duplex map for media types. */
240 const char tulip_media_cap[32] =
241 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
242 u8 t21040_csr13[] = {2,0x0C,8,4, 4,0,0,0, 0,0,0,0, 4,0,0,0};
244 /* 21041 transceiver register settings: 10-T, 10-2, AUI, 10-T, 10T-FD*/
245 u16 t21041_csr13[] = {
246 csr13_mask_10bt, /* 10-T */
247 csr13_mask_auibnc, /* 10-2 */
248 csr13_mask_auibnc, /* AUI */
249 csr13_mask_10bt, /* 10-T */
250 csr13_mask_10bt, /* 10T-FD */
252 u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, };
253 u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
256 static void tulip_tx_timeout(struct net_device *dev);
257 static void tulip_init_ring(struct net_device *dev);
258 static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
259 static int tulip_open(struct net_device *dev);
260 static int tulip_close(struct net_device *dev);
261 static void tulip_up(struct net_device *dev);
262 static void tulip_down(struct net_device *dev);
263 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
264 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
265 static void set_rx_mode(struct net_device *dev);
269 static void tulip_set_power_state (struct tulip_private *tp,
270 int sleep, int snooze)
272 if (tp->flags & HAS_ACPI) {
274 pci_read_config_dword (tp->pdev, CFDD, &tmp);
275 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
277 newtmp |= CFDD_Sleep;
279 newtmp |= CFDD_Snooze;
281 pci_write_config_dword (tp->pdev, CFDD, newtmp);
287 static void tulip_up(struct net_device *dev)
289 struct tulip_private *tp = (struct tulip_private *)dev->priv;
290 long ioaddr = dev->base_addr;
291 int next_tick = 3*HZ;
293 unsigned long value32;
295 /* Wake the chip from sleep/snooze mode. */
296 tulip_set_power_state (tp, 0, 0);
298 /* On some chip revs we must set the MII/SYM port before the reset!? */
299 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
300 outl(0x00040000, ioaddr + CSR6);
302 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
303 outl(0x00000001, ioaddr + CSR0);
307 Wait the specified 50 PCI cycles after a reset by initializing
308 Tx and Rx queues and the address filter list. */
309 outl(tp->csr0, ioaddr + CSR0);
313 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
315 outl(tp->rx_ring_dma, ioaddr + CSR3);
316 outl(tp->tx_ring_dma, ioaddr + CSR4);
317 tp->cur_rx = tp->cur_tx = 0;
318 tp->dirty_rx = tp->dirty_tx = 0;
322 value32 = inl(ioaddr+0x88); //CSR18
323 value32 &= 0xff1fffff;
324 value32 |= 0x00400000; //set Receive FIFO 2K , Drain Receive threshold 32bit
325 outl(value32, ioaddr + 0x88);
328 // for (i=0;i<0x20;i++)
330 // printk("PHY %d = %04x\n",i,tulip_mdio_read(dev,1,i));
333 if (tp->flags & MC_HASH_ONLY) {
334 u32 addr_low = cpu_to_le32(get_unaligned((u32 *)dev->dev_addr));
336 u32 addr_high = (get_unaligned((u16 *)(dev->dev_addr+4)));
339 sp = (char *)&addr_high;
343 // printk("addr_low = %08lx\n",addr_low);
344 // printk("addr_high = %08lx\n",addr_high);
345 // printk(" %02x %02x %02x %02x\n",sp[0],sp[1],sp[2],sp[3]);
347 if (tp->chip_id == AX88140) {
348 outl(0, ioaddr + CSR13);
349 outl(addr_low, ioaddr + CSR14);
350 outl(1, ioaddr + CSR13);
351 outl(addr_high, ioaddr + CSR14);
352 } else if (tp->flags & COMET_MAC_ADDR) {
353 outl(addr_low, ioaddr + 0xA4);
354 outl(addr_high, ioaddr + 0xA8);
355 outl(0, ioaddr + 0xAC);
356 outl(0, ioaddr + 0xB0);
359 /* This is set_rx_mode(), but without starting the transmitter. */
360 u16 *eaddrs = (u16 *)dev->dev_addr;
361 u16 *setup_frm = &tp->setup_frame[15*6];
364 /* 21140 bug: you must add the broadcast address. */
365 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
366 /* Fill the final entry of the table with our physical address. */
367 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
368 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
369 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
371 mapping = pci_map_single(tp->pdev, tp->setup_frame,
372 sizeof(tp->setup_frame),
374 tp->tx_buffers[tp->cur_tx].skb = NULL;
375 tp->tx_buffers[tp->cur_tx].mapping = mapping;
377 /* Put the setup frame on the Tx list. */
378 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
379 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
380 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
385 tp->saved_if_port = dev->if_port;
386 if (dev->if_port == 0)
387 dev->if_port = tp->default_port;
389 /* Allow selecting a default media. */
391 if (tp->mtable == NULL)
394 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
395 (dev->if_port == 12 ? 0 : dev->if_port);
396 for (i = 0; i < tp->mtable->leafcount; i++)
397 if (tp->mtable->mleaf[i].media == looking_for) {
398 printk(KERN_INFO "%s: Using user-specified media %s.\n",
399 dev->name, medianame[dev->if_port]);
403 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
404 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
405 for (i = 0; i < tp->mtable->leafcount; i++)
406 if (tp->mtable->mleaf[i].media == looking_for) {
407 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
408 dev->name, medianame[looking_for]);
412 /* Start sensing first non-full-duplex media. */
413 for (i = tp->mtable->leafcount - 1;
414 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
423 if (tp->chip_id == DC21143 &&
424 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
425 /* We must reset the media CSRs when we force-select MII mode. */
426 outl(0x0000, ioaddr + CSR13);
427 outl(0x0000, ioaddr + CSR14);
428 outl(0x0008, ioaddr + CSR15);
430 tulip_select_media(dev, 1);
431 } else if (tp->chip_id == DC21041) {
433 tp->nway = tp->mediasense = 1;
434 tp->nwayset = tp->lpar = 0;
435 outl(0x00000000, ioaddr + CSR13);
436 outl(0xFFFFFFFF, ioaddr + CSR14);
437 outl(0x00000008, ioaddr + CSR15); /* Listen on AUI also. */
438 tp->csr6 = 0x80020000;
439 if (tp->sym_advertise & 0x0040)
440 tp->csr6 |= FullDuplex;
441 outl(tp->csr6, ioaddr + CSR6);
442 outl(0x0000EF01, ioaddr + CSR13);
444 } else if (tp->chip_id == DC21142) {
446 tulip_select_media(dev, 1);
448 printk(KERN_INFO "%s: Using MII transceiver %d, status "
450 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
451 outl(csr6_mask_defstate, ioaddr + CSR6);
452 tp->csr6 = csr6_mask_hdcap;
454 outl(0x0000, ioaddr + CSR13);
455 outl(0x0000, ioaddr + CSR14);
457 t21142_start_nway(dev);
458 } else if (tp->chip_id == PNIC2) {
459 /* for initial startup advertise 10/100 Full and Half */
460 tp->sym_advertise = 0x01E0;
461 /* enable autonegotiate end interrupt */
462 outl(inl(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
463 outl(inl(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
464 pnic2_start_nway(dev);
465 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
468 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
469 outl(0x0001, ioaddr + CSR15);
470 } else if (inl(ioaddr + CSR5) & TPLnkPass)
473 /* Start with 10mbps to do autonegotiation. */
474 outl(0x32, ioaddr + CSR12);
475 tp->csr6 = 0x00420000;
476 outl(0x0001B078, ioaddr + 0xB8);
477 outl(0x0201B078, ioaddr + 0xB8);
480 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
481 && ! tp->medialock) {
483 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
484 outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80);
485 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
486 /* Provided by BOLO, Macronix - 12/10/1998. */
488 tp->csr6 = 0x01a80200;
489 outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80);
490 outl(0x11000 | inw(ioaddr + 0xa0), ioaddr + 0xa0);
491 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
492 /* Enable automatic Tx underrun recovery. */
493 outl(inl(ioaddr + 0x88) | 1, ioaddr + 0x88);
494 dev->if_port = tp->mii_cnt ? 11 : 0;
495 //LIC01252005 tp->csr6 = 0x00040000;
496 tp->csr6 = 0x00040080; //LIC01252005
497 } else if (tp->chip_id == AX88140) {
498 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
500 tulip_select_media(dev, 1);
502 /* Start the chip's Tx to process setup frame. */
506 outl(tp->csr6 | TxOn, ioaddr + CSR6);
508 /* Enable interrupts by setting the interrupt mask. */
509 outl(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
510 outl(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
511 tulip_start_rxtx(tp);
512 outl(0, ioaddr + CSR2); /* Rx poll demand */
514 if (tulip_debug > 2) {
515 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
516 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5),
520 /* Set the timer to switch to check for link beat and perhaps switch
521 to an alternate media type. */
522 tp->timer.expires = RUN_AT(next_tick);
523 add_timer(&tp->timer);
526 #ifdef CONFIG_NET_HW_FLOWCONTROL
527 /* Enable receiver */
528 void tulip_xon(struct net_device *dev)
530 struct tulip_private *tp = (struct tulip_private *)dev->priv;
532 clear_bit(tp->fc_bit, &netdev_fc_xoff);
533 if (netif_running(dev)){
535 tulip_refill_rx(dev);
536 outl(tulip_tbl[tp->chip_id].valid_intrs, dev->base_addr+CSR7);
542 tulip_open(struct net_device *dev)
544 #ifdef CONFIG_NET_HW_FLOWCONTROL
545 struct tulip_private *tp = (struct tulip_private *)dev->priv;
550 if ((retval = request_irq(dev->irq, &tulip_interrupt, SA_SHIRQ, dev->name, dev))) {
555 tulip_init_ring (dev);
559 #ifdef CONFIG_NET_HW_FLOWCONTROL
560 tp->fc_bit = netdev_register_fc(dev, tulip_xon);
563 netif_start_queue (dev);
569 static void tulip_tx_timeout(struct net_device *dev)
571 struct tulip_private *tp = (struct tulip_private *)dev->priv;
572 long ioaddr = dev->base_addr;
575 printk("tulip_tx_timeout\n");
576 spin_lock_irqsave (&tp->lock, flags);
578 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
579 /* Do nothing -- the media monitor should handle this. */
581 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
583 // } else if (tp->chip_id == DC21040) {
584 // if ( !tp->medialock && inl(ioaddr + CSR12) & 0x0002) {
585 // dev->if_port = (dev->if_port == 2 ? 0 : 2);
586 // printk(KERN_INFO "%s: 21040 transmit timed out, switching to "
588 // dev->name, medianame[dev->if_port]);
589 // tulip_select_media(dev, 0);
592 // } else if (tp->chip_id == DC21041) {
593 // int csr12 = inl(ioaddr + CSR12);
595 // printk(KERN_WARNING "%s: 21041 transmit timed out, status %8.8x, "
596 // "CSR12 %8.8x, CSR13 %8.8x, CSR14 %8.8x, resetting...\n",
597 // dev->name, inl(ioaddr + CSR5), csr12,
598 // inl(ioaddr + CSR13), inl(ioaddr + CSR14));
599 // tp->mediasense = 1;
600 // if ( ! tp->medialock) {
601 // if (dev->if_port == 1 || dev->if_port == 2)
602 // if (csr12 & 0x0004) {
603 // dev->if_port = 2 - dev->if_port;
608 // tulip_select_media(dev, 0);
610 // } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
611 // || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
612 // || tp->chip_id == DM910X) {
613 // printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
614 // "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
615 // dev->name, inl(ioaddr + CSR5), inl(ioaddr + CSR12),
616 // inl(ioaddr + CSR13), inl(ioaddr + CSR14), inl(ioaddr + CSR15));
617 // if ( ! tp->medialock && tp->mtable) {
620 // while (tp->cur_index >= 0
621 // && (tulip_media_cap[tp->mtable->mleaf[tp->cur_index].media]
623 // if (--tp->cur_index < 0) {
624 // /* We start again, but should instead look for default. */
625 // tp->cur_index = tp->mtable->leafcount - 1;
627 // tulip_select_media(dev, 0);
628 // printk(KERN_WARNING "%s: transmit timed out, switching to %s "
629 // "media.\n", dev->name, medianame[dev->if_port]);
631 // } else if (tp->chip_id == PNIC2) {
632 // printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
633 // "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
634 // dev->name, (int)inl(ioaddr + CSR5), (int)inl(ioaddr + CSR6),
635 // (int)inl(ioaddr + CSR7), (int)inl(ioaddr + CSR12));
637 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
638 "%8.8x, resetting...\n",
639 dev->name, inl(ioaddr + CSR5), inl(ioaddr + CSR12));
643 //#if defined(way_too_many_messages)
644 // if (tulip_debug > 3) {
646 // for (i = 0; i < RX_RING_SIZE; i++) {
647 // u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
649 // printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
650 // "%2.2x %2.2x %2.2x.\n",
651 // i, (unsigned int)tp->rx_ring[i].status,
652 // (unsigned int)tp->rx_ring[i].length,
653 // (unsigned int)tp->rx_ring[i].buffer1,
654 // (unsigned int)tp->rx_ring[i].buffer2,
655 // buf[0], buf[1], buf[2]);
656 // for (j = 0; buf[j] != 0xee && j < 1600; j++)
657 // if (j < 100) printk(" %2.2x", buf[j]);
658 // printk(" j=%d.\n", j);
660 // printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
661 // for (i = 0; i < RX_RING_SIZE; i++)
662 // printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
663 // printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
664 // for (i = 0; i < TX_RING_SIZE; i++)
665 // printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
670 /* Stop and restart the chip's Tx processes . */
671 #ifdef CONFIG_NET_HW_FLOWCONTROL
672 if (tp->fc_bit && test_bit(tp->fc_bit,&netdev_fc_xoff))
673 printk("BUG tx_timeout restarting rx when fc on\n");
675 tulip_restart_rxtx(tp);
676 /* Trigger an immediate transmit demand. */
677 outl(0, ioaddr + CSR1);
679 tp->stats.tx_errors++;
682 spin_unlock_irqrestore (&tp->lock, flags);
683 dev->trans_start = jiffies;
684 netif_wake_queue (dev);
688 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
689 static void tulip_init_ring(struct net_device *dev)
691 struct tulip_private *tp = (struct tulip_private *)dev->priv;
698 for (i = 0; i < RX_RING_SIZE; i++) {
699 tp->rx_ring[i].status = 0x00000000;
700 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
701 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
702 tp->rx_buffers[i].skb = NULL;
703 tp->rx_buffers[i].mapping = 0;
705 /* Mark the last entry as wrapping the ring. */
706 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
707 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
709 for (i = 0; i < RX_RING_SIZE; i++) {
712 /* Note the receive buffer must be longword aligned.
713 dev_alloc_skb() provides 16 byte alignment. But do *not*
714 use skb_reserve() to align the IP header! */
715 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
716 tp->rx_buffers[i].skb = skb;
719 mapping = pci_map_single(tp->pdev, skb->tail,
720 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
721 tp->rx_buffers[i].mapping = mapping;
722 skb->dev = dev; /* Mark as being used by this device. */
723 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
724 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
726 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
728 /* The Tx buffer descriptor is filled in as needed, but we
729 do need to clear the ownership bit. */
730 for (i = 0; i < TX_RING_SIZE; i++) {
731 tp->tx_buffers[i].skb = NULL;
732 tp->tx_buffers[i].mapping = 0;
733 tp->tx_ring[i].status = 0x00000000;
734 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
736 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
740 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
742 struct tulip_private *tp = (struct tulip_private *)dev->priv;
746 unsigned long eflags;
748 spin_lock_irqsave(&tp->lock, eflags);
750 /* Calculate the next Tx descriptor entry. */
751 entry = tp->cur_tx % TX_RING_SIZE;
753 tp->tx_buffers[entry].skb = skb;
754 mapping = pci_map_single(tp->pdev, skb->data,
755 skb->len, PCI_DMA_TODEVICE);
756 tp->tx_buffers[entry].mapping = mapping;
757 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
759 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
760 flag = 0x60000000; /* No interrupt */
761 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
762 flag = 0xe0000000; /* Tx-done intr. */
763 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
764 flag = 0x60000000; /* No Tx-done intr. */
765 } else { /* Leave room for set_rx_mode() to fill entries. */
766 flag = 0xe0000000; /* Tx-done intr. */
767 netif_stop_queue(dev);
769 if (entry == TX_RING_SIZE-1)
770 flag = 0xe0000000 | DESC_RING_WRAP;
772 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
773 /* if we were using Transmit Automatic Polling, we would need a
775 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
780 /* Trigger an immediate transmit demand. */
781 outl(0, dev->base_addr + CSR1);
783 spin_unlock_irqrestore(&tp->lock, eflags);
785 dev->trans_start = jiffies;
790 static void tulip_clean_tx_ring(struct tulip_private *tp)
792 unsigned int dirty_tx;
794 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
796 int entry = dirty_tx % TX_RING_SIZE;
797 int status = le32_to_cpu(tp->tx_ring[entry].status);
800 tp->stats.tx_errors++; /* It wasn't Txed */
801 tp->tx_ring[entry].status = 0;
804 /* Check for Tx filter setup frames. */
805 if (tp->tx_buffers[entry].skb == NULL) {
806 /* test because dummy frames not mapped */
807 if (tp->tx_buffers[entry].mapping)
808 pci_unmap_single(tp->pdev,
809 tp->tx_buffers[entry].mapping,
810 sizeof(tp->setup_frame),
815 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
816 tp->tx_buffers[entry].skb->len,
819 /* Free the original skb. */
820 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
821 tp->tx_buffers[entry].skb = NULL;
822 tp->tx_buffers[entry].mapping = 0;
826 static void tulip_down (struct net_device *dev)
828 long ioaddr = dev->base_addr;
829 struct tulip_private *tp = (struct tulip_private *) dev->priv;
832 del_timer_sync (&tp->timer);
834 spin_lock_irqsave (&tp->lock, flags);
836 /* Disable interrupts by clearing the interrupt mask. */
837 outl (0x00000000, ioaddr + CSR7);
839 /* Stop the Tx and Rx processes. */
842 /* prepare receive buffers */
843 tulip_refill_rx(dev);
845 /* release any unconsumed transmit buffers */
846 tulip_clean_tx_ring(tp);
848 /* 21040 -- Leave the card in 10baseT state. */
849 // if (tp->chip_id == DC21040)
850 // outl (0x00000004, ioaddr + CSR13);
852 if (inl (ioaddr + CSR6) != 0xffffffff)
853 tp->stats.rx_missed_errors += inl (ioaddr + CSR8) & 0xffff;
855 spin_unlock_irqrestore (&tp->lock, flags);
857 init_timer(&tp->timer);
858 tp->timer.data = (unsigned long)dev;
859 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
861 dev->if_port = tp->saved_if_port;
863 /* Leave the driver in snooze, not sleep, mode. */
864 tulip_set_power_state (tp, 0, 1);
868 static int tulip_close (struct net_device *dev)
870 long ioaddr = dev->base_addr;
871 struct tulip_private *tp = (struct tulip_private *) dev->priv;
874 netif_stop_queue (dev);
876 #ifdef CONFIG_NET_HW_FLOWCONTROL
878 int bit = tp->fc_bit;
880 netdev_unregister_fc(bit);
886 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
887 dev->name, inl (ioaddr + CSR5));
889 free_irq (dev->irq, dev);
891 /* Free all the skbuffs in the Rx queue. */
892 for (i = 0; i < RX_RING_SIZE; i++) {
893 struct sk_buff *skb = tp->rx_buffers[i].skb;
894 dma_addr_t mapping = tp->rx_buffers[i].mapping;
896 tp->rx_buffers[i].skb = NULL;
897 tp->rx_buffers[i].mapping = 0;
899 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
900 tp->rx_ring[i].length = 0;
901 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
903 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
908 for (i = 0; i < TX_RING_SIZE; i++) {
909 struct sk_buff *skb = tp->tx_buffers[i].skb;
912 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
913 skb->len, PCI_DMA_TODEVICE);
916 tp->tx_buffers[i].skb = NULL;
917 tp->tx_buffers[i].mapping = 0;
925 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
927 struct tulip_private *tp = (struct tulip_private *)dev->priv;
928 long ioaddr = dev->base_addr;
930 if (netif_running(dev)) {
933 spin_lock_irqsave (&tp->lock, flags);
935 tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff;
937 spin_unlock_irqrestore(&tp->lock, flags);
944 static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr)
946 struct tulip_private *np = dev->priv;
949 if (copy_from_user(ðcmd, useraddr, sizeof(ethcmd)))
953 case ETHTOOL_GDRVINFO: {
954 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
955 strcpy(info.driver, DRV_NAME);
956 strcpy(info.version, DRV_VERSION);
957 strcpy(info.bus_info, np->pdev->slot_name);
958 if (copy_to_user(useraddr, &info, sizeof(info)))
968 /* Provide ioctl() calls to examine the MII xcvr state. */
969 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
971 struct tulip_private *tp = dev->priv;
972 long ioaddr = dev->base_addr;
973 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
974 const unsigned int phy_idx = 0;
975 int phy = tp->phys[phy_idx] & 0x1f;
976 unsigned int regnum = data->reg_num;
977 unsigned long Value32;
978 unsigned long *mem_addr;
982 return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
984 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
985 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
988 else if (tp->flags & HAS_NWAY)
990 else if (tp->chip_id == COMET)
995 case SIOCGMIIREG: /* Read MII PHY register. */
996 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
997 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
998 int csr12 = inl (ioaddr + CSR12);
999 int csr14 = inl (ioaddr + CSR14);
1002 if (((csr14<<5) & 0x1000) ||
1003 (dev->if_port == 5 && tp->nwayset))
1004 data->val_out = 0x1000;
1006 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
1007 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
1012 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
1013 ((csr12&0x06) == 6 ? 0 : 4);
1014 if (tp->chip_id != DC21041)
1015 data->val_out |= 0x6048;
1018 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
1020 ((inl(ioaddr + CSR6) >> 3) & 0x0040) +
1021 ((csr14 >> 1) & 0x20) + 1;
1022 if (tp->chip_id != DC21041)
1023 data->val_out |= ((csr14 >> 9) & 0x03C0);
1025 case 5: data->val_out = tp->lpar; break;
1026 default: data->val_out = 0; break;
1029 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
1033 case SIOCSMIIREG: /* Write MII PHY register. */
1034 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
1035 if (!capable (CAP_NET_ADMIN))
1039 if (data->phy_id == phy) {
1040 u16 value = data->val_in;
1042 case 0: /* Check for autonegotiation on or reset. */
1043 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
1044 if (tp->full_duplex_lock)
1045 tp->full_duplex = (value & 0x0100) ? 1 : 0;
1048 tp->advertising[phy_idx] =
1049 tp->mii_advertise = data->val_in;
1053 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
1054 u16 value = data->val_in;
1056 if ((value & 0x1200) == 0x1200) {
1057 if (tp->chip_id == PNIC2) {
1058 pnic2_start_nway (dev);
1060 t21142_start_nway (dev);
1063 } else if (regnum == 4)
1064 tp->sym_advertise = value;
1066 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
1070 case SIOCDEVPRIVATE + 0x08: //for read memory
1071 mem_addr = (unsigned long*)rq->ifr_data;
1072 Value32 = *mem_addr;
1073 *mem_addr = le32_to_cpu((*((volatile unsigned long *)(Value32))));
1076 case SIOCDEVPRIVATE + 0x09: //for write memory
1077 //*(mem_addr) -->address
1078 //*(mem_addr+1) -->value
1079 mem_addr = (unsigned long*)rq->ifr_data;
1080 Value32 = *mem_addr;
1081 (*((volatile unsigned long *)(Value32))) = cpu_to_le32(*(mem_addr+1));
1091 /* Set or clear the multicast filter for this adaptor.
1092 Note that we only use exclusion around actually queueing the
1093 new frame, not around filling tp->setup_frame. This is non-deterministic
1094 when re-entered but still correct. */
1097 #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
1099 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
1101 struct tulip_private *tp = (struct tulip_private *)dev->priv;
1103 struct dev_mc_list *mclist;
1107 memset(hash_table, 0, sizeof(hash_table));
1108 set_bit_le(255, hash_table); /* Broadcast entry */
1109 /* This should work on big-endian machines as well. */
1110 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1111 i++, mclist = mclist->next) {
1112 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
1114 set_bit_le(index, hash_table);
1116 for (i = 0; i < 32; i++) {
1117 *setup_frm++ = hash_table[i];
1118 *setup_frm++ = hash_table[i];
1120 setup_frm = &tp->setup_frame[13*6];
1123 /* Fill the final entry with our physical address. */
1124 eaddrs = (u16 *)dev->dev_addr;
1125 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1126 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1127 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1130 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1132 struct tulip_private *tp = (struct tulip_private *)dev->priv;
1133 struct dev_mc_list *mclist;
1137 /* We have <= 14 addresses so we can use the wonderful
1138 16 address perfect filtering of the Tulip. */
1139 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1140 i++, mclist = mclist->next) {
1141 eaddrs = (u16 *)mclist->dmi_addr;
1142 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1143 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1144 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1146 /* Fill the unused entries with the broadcast address. */
1147 memset(setup_frm, 0xff, (15-i)*12);
1148 setup_frm = &tp->setup_frame[15*6];
1150 /* Fill the final entry with our physical address. */
1151 eaddrs = (u16 *)dev->dev_addr;
1152 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1153 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1154 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1158 static void set_rx_mode(struct net_device *dev)
1160 struct tulip_private *tp = (struct tulip_private *)dev->priv;
1161 long ioaddr = dev->base_addr;
1164 csr6 = inl(ioaddr + CSR6) & ~0x00D5;
1166 tp->csr6 &= ~0x00D5;
1167 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1168 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1169 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1170 /* Unconditionally log net taps. */
1171 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1172 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1173 /* Too many to filter well -- accept all multicasts. */
1174 tp->csr6 |= AcceptAllMulticast;
1175 csr6 |= AcceptAllMulticast;
1176 } else if (tp->flags & MC_HASH_ONLY) {
1177 /* Some work-alikes have only a 64-entry hash filter table. */
1178 /* Should verify correctness on big-endian/__powerpc__ */
1179 struct dev_mc_list *mclist;
1181 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1182 tp->csr6 |= AcceptAllMulticast;
1183 csr6 |= AcceptAllMulticast;
1185 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1187 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1188 i++, mclist = mclist->next) {
1189 if (tp->flags & COMET_MAC_ADDR)
1190 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1192 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1194 mc_filter[filterbit >> 5] |= cpu_to_le32(1 << (filterbit & 31));
1195 if (tulip_debug > 2) {
1196 printk(KERN_INFO "%s: Added filter for %2.2x:%2.2x:%2.2x:"
1197 "%2.2x:%2.2x:%2.2x %8.8x bit %d.\n", dev->name,
1198 mclist->dmi_addr[0], mclist->dmi_addr[1],
1199 mclist->dmi_addr[2], mclist->dmi_addr[3],
1200 mclist->dmi_addr[4], mclist->dmi_addr[5],
1201 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1204 if (mc_filter[0] == tp->mc_filter[0] &&
1205 mc_filter[1] == tp->mc_filter[1])
1207 else if (tp->flags & IS_ASIX) {
1208 outl(2, ioaddr + CSR13);
1209 outl(mc_filter[0], ioaddr + CSR14);
1210 outl(3, ioaddr + CSR13);
1211 outl(mc_filter[1], ioaddr + CSR14);
1212 } else if (tp->flags & COMET_MAC_ADDR) {
1213 mc_filter[0] = 0xffffffff; //LIC01252005
1214 mc_filter[1] = 0xffffffff; //LIC01252005
1215 outl(mc_filter[0], ioaddr + 0xAC);
1216 outl(mc_filter[1], ioaddr + 0xB0);
1218 tp->mc_filter[0] = mc_filter[0];
1219 tp->mc_filter[1] = mc_filter[1];
1222 unsigned long flags;
1224 /* Note that only the low-address shortword of setup_frame is valid!
1225 The values are doubled for big-endian architectures. */
1226 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1227 build_setup_frame_hash(tp->setup_frame, dev);
1229 build_setup_frame_perfect(tp->setup_frame, dev);
1232 spin_lock_irqsave(&tp->lock, flags);
1234 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1235 /* Same setup recently queued, we need not add it. */
1237 u32 tx_flags = 0x08000000 | 192;
1241 /* Now add this frame to the Tx list. */
1243 entry = tp->cur_tx++ % TX_RING_SIZE;
1246 /* Avoid a chip errata by prefixing a dummy entry. */
1247 tp->tx_buffers[entry].skb = NULL;
1248 tp->tx_buffers[entry].mapping = 0;
1249 tp->tx_ring[entry].length =
1250 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1251 tp->tx_ring[entry].buffer1 = 0;
1252 /* Must set DescOwned later to avoid race with chip */
1254 entry = tp->cur_tx++ % TX_RING_SIZE;
1257 tp->tx_buffers[entry].skb = NULL;
1258 tp->tx_buffers[entry].mapping =
1259 pci_map_single(tp->pdev, tp->setup_frame,
1260 sizeof(tp->setup_frame),
1262 /* Put the setup frame on the Tx list. */
1263 if (entry == TX_RING_SIZE-1)
1264 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1265 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1266 tp->tx_ring[entry].buffer1 =
1267 cpu_to_le32(tp->tx_buffers[entry].mapping);
1268 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1270 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1271 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1272 netif_stop_queue(dev);
1274 /* Trigger an immediate transmit demand. */
1275 outl(0, ioaddr + CSR1);
1278 spin_unlock_irqrestore(&tp->lock, flags);
1281 outl(csr6, ioaddr + CSR6);
1284 #ifdef CONFIG_TULIP_MWI
1285 static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1286 struct net_device *dev)
1288 struct tulip_private *tp = dev->priv;
1293 if (tulip_debug > 3)
1294 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pdev->slot_name);
1296 tp->csr0 = csr0 = 0;
1298 /* if we have any cache line size at all, we can do MRM */
1301 /* ...and barring hardware bugs, MWI */
1302 if (!(tp->chip_id == DC21143 && tp->revision == 65))
1305 /* set or disable MWI in the standard PCI command bit.
1306 * Check for the case where mwi is desired but not available
1308 if (csr0 & MWI) pci_set_mwi(pdev);
1309 else pci_clear_mwi(pdev);
1311 /* read result from hardware (in case bit refused to enable) */
1312 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1313 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1316 /* if cache line size hardwired to zero, no MWI */
1317 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1318 if ((csr0 & MWI) && (cache == 0)) {
1320 pci_clear_mwi(pdev);
1323 /* assign per-cacheline-size cache alignment and
1324 * burst length values
1328 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1331 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1334 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1341 /* if we have a good cache line size, we by now have a good
1342 * csr0, so save it and exit
1347 /* we don't have a good csr0 or cache line size, disable MWI */
1349 pci_clear_mwi(pdev);
1353 /* sane defaults for burst length and cache alignment
1354 * originally from de4x5 driver
1356 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1360 if (tulip_debug > 2)
1361 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1362 pdev->slot_name, cache, csr0);
1366 static int __devinit tulip_init_one (struct pci_dev *pdev,
1367 const struct pci_device_id *ent)
1369 struct tulip_private *tp;
1370 /* See note below on the multiport cards. */
1371 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1372 static int last_irq;
1373 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1377 u8 ee_data[EEPROM_SIZE];
1378 struct net_device *dev;
1380 static int board_idx = -1;
1381 int chip_idx = ent->driver_data;
1382 // unsigned int t2104x_mode = 0;
1383 unsigned int eeprom_missing = 0;
1384 unsigned int force_csr0 = 0;
1387 static int did_version; /* Already printed version info. */
1388 if (tulip_debug > 0 && did_version++ == 0)
1389 printk (KERN_INFO "%s", version);
1395 * Lan media wire a tulip chip to a wan interface. Needs a very
1396 * different driver (lmc driver)
1399 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1400 printk (KERN_ERR PFX "skipping LMC card.\n");
1405 * Early DM9100's need software CRC and the DMFE driver
1408 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1411 /* Read Chip revision */
1412 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
1413 if(dev_rev < 0x02000030)
1415 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1421 * Looks for early PCI chipsets where people report hangs
1422 * without the workarounds being on.
1425 /* Intel Saturn. Switch to 8 long words burst, 8 long word cache aligned
1426 Aries might need this too. The Saturn errata are not pretty reading but
1427 thankfully its an old 486 chipset.
1430 if (pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424, NULL)) {
1431 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1434 /* The dreaded SiS496 486 chipset. Same workaround as above. */
1435 if (pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, NULL)) {
1436 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1440 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1441 if (chip_idx == AX88140) {
1442 if ((csr0 & 0x3f00) == 0)
1446 /* PNIC doesn't have MWI/MRL/MRM... */
1447 if (chip_idx == LC82C168)
1448 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1450 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1451 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1452 csr0 &= ~0x01f100ff;
1454 #if defined(__sparc__)
1455 /* DM9102A needs 32-dword alignment/burst length on sparc - chip bug? */
1456 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1457 csr0 = (csr0 & ~0xff00) | 0xe000;
1461 * And back to business
1464 i = pci_enable_device(pdev);
1466 printk (KERN_ERR PFX
1467 "Cannot enable tulip board #%d, aborting\n",
1472 ioaddr = pci_resource_start (pdev, 0);
1475 /* alloc_etherdev ensures aligned and zeroed private structures */
1476 dev = alloc_etherdev (sizeof (*tp));
1478 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1482 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1483 printk (KERN_ERR PFX "%s: I/O region (0x%lx@0x%lx) too small, "
1484 "aborting\n", pdev->slot_name,
1485 pci_resource_len (pdev, 0),
1486 pci_resource_start (pdev, 0));
1487 goto err_out_free_netdev;
1490 /* grab all resources from both PIO and MMIO regions, as we
1491 * don't want anyone else messing around with our hardware */
1492 if (pci_request_regions (pdev, "tulip"))
1493 goto err_out_free_netdev;
1496 ioaddr = (unsigned long) ioremap (pci_resource_start (pdev, 1),
1497 tulip_tbl[chip_idx].io_size);
1499 goto err_out_free_res;
1502 pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev);
1505 * initialize private data structure 'tp'
1506 * it is zeroed and aligned in alloc_etherdev
1510 tp->rx_ring = pci_alloc_consistent(pdev,
1511 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1512 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1515 goto err_out_mtable;
1516 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1517 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1519 tp->chip_id = chip_idx;
1520 tp->flags = tulip_tbl[chip_idx].flags;
1522 tp->base_addr = ioaddr;
1523 tp->revision = chip_rev;
1525 spin_lock_init(&tp->lock);
1526 spin_lock_init(&tp->mii_lock);
1527 init_timer(&tp->timer);
1528 tp->timer.data = (unsigned long)dev;
1529 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1531 dev->base_addr = ioaddr;
1533 #ifdef CONFIG_TULIP_MWI
1534 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1535 tulip_mwi_config (pdev, dev);
1537 /* MWI is broken for DC21143 rev 65... */
1538 if (chip_idx == DC21143 && chip_rev == 65)
1542 /* Stop the chip's Tx and Rx processes. */
1543 tulip_stop_rxtx(tp);
1545 pci_set_master(pdev);
1547 /* Clear the missed-packet counter. */
1550 // if (chip_idx == DC21041) {
1551 // if (inl(ioaddr + CSR9) & 0x8000) {
1552 // chip_idx = DC21040;
1559 /* The station address ROM is read byte serially. The register must
1560 be polled, waiting for the value to be read bit serially from the
1564 if (chip_idx == DC21040) {
1565 outl(0, ioaddr + CSR9); /* Reset the pointer with a dummy write. */
1566 for (i = 0; i < 6; i++) {
1567 int value, boguscnt = 100000;
1569 value = inl(ioaddr + CSR9);
1570 while (value < 0 && --boguscnt > 0);
1571 dev->dev_addr[i] = value;
1572 sum += value & 0xff;
1574 } else if (chip_idx == LC82C168) {
1575 for (i = 0; i < 3; i++) {
1576 int value, boguscnt = 100000;
1577 outl(0x600 | i, ioaddr + 0x98);
1579 value = inl(ioaddr + CSR9);
1580 while (value < 0 && --boguscnt > 0);
1581 put_unaligned(le16_to_cpu(value), ((u16*)dev->dev_addr) + i);
1582 sum += value & 0xffff;
1584 } else if (chip_idx == COMET) {
1585 /* No need to read the EEPROM. */
1587 u32 addr_high = inl(ioaddr + 0xA8);
1590 sp = (char *)&addr_high;
1594 put_unaligned(le32_to_cpu(inl(ioaddr + 0xA4)), (u32 *)dev->dev_addr);
1595 put_unaligned(addr_high, (u16 *)(dev->dev_addr + 4));
1597 for (i = 0; i < 6; i ++)
1598 sum += dev->dev_addr[i];
1600 /* A serial EEPROM interface, we read now and sort it out later. */
1602 int ee_addr_size = tulip_read_eeprom(ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
1604 for (i = 0; i < sizeof(ee_data)/2; i++)
1605 ((u16 *)ee_data)[i] =
1606 le16_to_cpu(tulip_read_eeprom(ioaddr, i, ee_addr_size));
1608 /* DEC now has a specification (see Notes) but early board makers
1609 just put the address in the first EEPROM locations. */
1610 /* This does memcmp(eedata, eedata+16, 8) */
1611 for (i = 0; i < 8; i ++)
1612 if (ee_data[i] != ee_data[16+i])
1614 if (chip_idx == CONEXANT) {
1615 /* Check that the tuple type and length is correct. */
1616 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1619 if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1621 sa_offset = 2; /* Grrr, damn Matrox boards. */
1624 #ifdef CONFIG_DDB5476
1625 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 6)) {
1626 /* DDB5476 MAC address in first EEPROM locations. */
1628 /* No media table either */
1629 tp->flags &= ~HAS_MEDIA_TABLE;
1632 #ifdef CONFIG_DDB5477
1633 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
1634 /* DDB5477 MAC address in first EEPROM locations. */
1636 /* No media table either */
1637 tp->flags &= ~HAS_MEDIA_TABLE;
1640 #ifdef CONFIG_MIPS_COBALT
1641 if ((pdev->bus->number == 0) &&
1642 ((PCI_SLOT(pdev->devfn) == 7) ||
1643 (PCI_SLOT(pdev->devfn) == 12))) {
1644 /* Cobalt MAC address in first EEPROM locations. */
1646 /* No media table either */
1647 tp->flags &= ~HAS_MEDIA_TABLE;
1651 /* 3x5 HSC (J3514A) has a broken srom */
1652 if(ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1653 /* pci_vendor_id and subsystem_id are swapped */
1654 ee_data[0] = ee_data[2];
1655 ee_data[1] = ee_data[3];
1659 /* srom need to be byte-swaped and shifted up 1 word.
1660 * This shift needs to happen at the end of the MAC
1661 * first because of the 2 byte overlap.
1663 for(i = 4; i >= 0; i -= 2) {
1664 ee_data[17 + i + 3] = ee_data[17 + i];
1665 ee_data[16 + i + 5] = ee_data[16 + i];
1669 for (i = 0; i < 6; i ++) {
1670 dev->dev_addr[i] = ee_data[i + sa_offset];
1671 sum += ee_data[i + sa_offset];
1674 // printk("\nMAC %02x:%02x:%02x:%02x:%02x:%02x\n", dev->dev_addr[0],dev->dev_addr[1],dev->dev_addr[2],
1675 // dev->dev_addr[3],dev->dev_addr[4],dev->dev_addr[5]);
1676 /* Lite-On boards have the address byte-swapped. */
1677 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0)
1678 && dev->dev_addr[1] == 0x00)
1679 for (i = 0; i < 6; i+=2) {
1680 char tmp = dev->dev_addr[i];
1681 dev->dev_addr[i] = dev->dev_addr[i+1];
1682 dev->dev_addr[i+1] = tmp;
1684 /* On the Zynx 315 Etherarray and other multiport boards only the
1685 first Tulip has an EEPROM.
1686 On Sparc systems the mac address is held in the OBP property
1687 "local-mac-address".
1688 The addresses of the subsequent ports are derived from the first.
1689 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1690 that here as well. */
1691 if (sum == 0 || sum == 6*0xff) {
1692 // printk("sum=0 or 0xffffffff\n");
1693 #if defined(__sparc__)
1694 struct pcidev_cookie *pcp = pdev->sysdata;
1697 for (i = 0; i < 5; i++)
1698 dev->dev_addr[i] = last_phys_addr[i];
1699 dev->dev_addr[i] = last_phys_addr[i] + 1;
1700 #if defined(__sparc__)
1701 if ((pcp != NULL) && prom_getproplen(pcp->prom_node,
1702 "local-mac-address") == 6) {
1703 prom_getproperty(pcp->prom_node, "local-mac-address",
1707 #if defined(__i386__) /* Patch up x86 BIOS bug. */
1713 for (i = 0; i < 6; i++)
1714 last_phys_addr[i] = dev->dev_addr[i];
1718 /* The lower four bits are the media type. */
1719 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1720 if (options[board_idx] & MEDIA_MASK)
1721 tp->default_port = options[board_idx] & MEDIA_MASK;
1722 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1723 tp->full_duplex = 1;
1724 if (mtu[board_idx] > 0)
1725 dev->mtu = mtu[board_idx];
1727 if (dev->mem_start & MEDIA_MASK)
1728 tp->default_port = dev->mem_start & MEDIA_MASK;
1729 if (tp->default_port) {
1730 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1731 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1733 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1734 tp->full_duplex = 1;
1736 if (tp->full_duplex)
1737 tp->full_duplex_lock = 1;
1739 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1740 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1741 tp->mii_advertise = media2advert[tp->default_port - 9];
1742 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1745 if (tp->flags & HAS_MEDIA_TABLE) {
1746 memcpy(tp->eeprom, ee_data, sizeof(tp->eeprom));
1748 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1749 tulip_parse_eeprom(dev);
1750 strcpy(dev->name, "eth%d"); /* un-hack */
1753 if ((tp->flags & ALWAYS_CHECK_MII) ||
1754 (tp->mtable && tp->mtable->has_mii) ||
1755 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1756 if (tp->mtable && tp->mtable->has_mii) {
1757 for (i = 0; i < tp->mtable->leafcount; i++)
1758 if (tp->mtable->mleaf[i].media == 11) {
1760 tp->saved_if_port = dev->if_port;
1761 tulip_select_media(dev, 2);
1762 dev->if_port = tp->saved_if_port;
1767 /* Find the connected MII xcvrs.
1768 Doing this in open() would allow detecting external xcvrs
1769 later, but takes much time. */
1770 tulip_find_mii (dev, board_idx);
1773 /* The Tulip-specific entries in the device structure. */
1774 dev->open = tulip_open;
1775 dev->hard_start_xmit = tulip_start_xmit;
1776 dev->tx_timeout = tulip_tx_timeout;
1777 dev->watchdog_timeo = TX_TIMEOUT;
1778 dev->stop = tulip_close;
1779 dev->get_stats = tulip_get_stats;
1780 dev->do_ioctl = private_ioctl;
1781 dev->set_multicast_list = set_rx_mode;
1783 if (register_netdev(dev))
1784 goto err_out_free_ring;
1786 printk(KERN_INFO "%s: %s rev %d at %#3lx,",
1787 dev->name, tulip_tbl[chip_idx].chip_name, chip_rev, ioaddr);
1788 pci_set_drvdata(pdev, dev);
1790 // if (t2104x_mode == 1)
1791 // printk(" 21040 compatible mode,");
1792 // else if (t2104x_mode == 2)
1793 // printk(" 21041 mode,");
1794 // if (eeprom_missing)
1795 // printk(" EEPROM not present,");
1796 //for (i = 0; i < 6; i++)
1797 // printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
1798 printk(" %02x:%02x:%02x:%02x:%02x:%02x", dev->dev_addr[0],dev->dev_addr[1],dev->dev_addr[2],
1799 dev->dev_addr[3],dev->dev_addr[4],dev->dev_addr[5]);
1800 printk(", IRQ %d.\n", irq);
1802 if (tp->chip_id == PNIC2)
1803 tp->link_change = pnic2_lnk_change;
1804 else if ((tp->flags & HAS_NWAY) || tp->chip_id == DC21041)
1805 tp->link_change = t21142_lnk_change;
1806 else if (tp->flags & HAS_PNICNWAY)
1807 tp->link_change = pnic_lnk_change;
1809 /* Reset the xcvr interface and turn on heartbeat. */
1812 if (tp->sym_advertise == 0)
1813 tp->sym_advertise = 0x0061;
1814 outl(0x00000000, ioaddr + CSR13);
1815 outl(0xFFFFFFFF, ioaddr + CSR14);
1816 outl(0x00000008, ioaddr + CSR15); /* Listen on AUI also. */
1817 outl(inl(ioaddr + CSR6) | csr6_fd, ioaddr + CSR6);
1818 outl(0x0000EF01, ioaddr + CSR13);
1821 outl(0x00000000, ioaddr + CSR13);
1822 outl(0x00000004, ioaddr + CSR13);
1828 outl(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1831 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1832 outl(csr6_mask_defstate, ioaddr + CSR6);
1833 outl(0x0000, ioaddr + CSR13);
1834 outl(0x0000, ioaddr + CSR14);
1835 outl(csr6_mask_hdcap, ioaddr + CSR6);
1837 t21142_start_nway(dev);
1840 /* just do a reset for sanity sake */
1841 outl(0x0000, ioaddr + CSR13);
1842 outl(0x0000, ioaddr + CSR14);
1845 if ( ! tp->mii_cnt) {
1848 outl(csr6_ttm | csr6_ca, ioaddr + CSR6);
1849 outl(0x30, ioaddr + CSR12);
1850 outl(0x0001F078, ioaddr + CSR6);
1851 outl(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1856 outl(0x00000000, ioaddr + CSR6);
1857 outl(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1858 outl(0x00000001, ioaddr + CSR13);
1862 outl(0x01a80000, ioaddr + CSR6);
1863 outl(0xFFFFFFFF, ioaddr + CSR14);
1864 outl(0x00001000, ioaddr + CSR12);
1867 /* No initialization necessary. */
1871 /* put the chip in snooze mode until opened */
1872 tulip_set_power_state (tp, 0, 1);
1877 pci_free_consistent (pdev,
1878 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1879 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1880 tp->rx_ring, tp->rx_ring_dma);
1886 iounmap((void *)ioaddr);
1890 pci_release_regions (pdev);
1892 err_out_free_netdev:
1900 static int tulip_suspend (struct pci_dev *pdev, u32 state)
1902 struct net_device *dev = pci_get_drvdata(pdev);
1904 if (dev && netif_running (dev) && netif_device_present (dev)) {
1905 netif_device_detach (dev);
1907 /* pci_power_off(pdev, -1); */
1913 static int tulip_resume(struct pci_dev *pdev)
1915 struct net_device *dev = pci_get_drvdata(pdev);
1917 if (dev && netif_running (dev) && !netif_device_present (dev)) {
1919 pci_enable_device (pdev);
1921 /* pci_power_on(pdev); */
1923 netif_device_attach (dev);
1928 #endif /* CONFIG_PM */
1931 static void __devexit tulip_remove_one (struct pci_dev *pdev)
1933 struct net_device *dev = pci_get_drvdata (pdev);
1934 struct tulip_private *tp;
1940 pci_free_consistent (pdev,
1941 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1942 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1943 tp->rx_ring, tp->rx_ring_dma);
1944 unregister_netdev (dev);
1948 iounmap((void *)dev->base_addr);
1951 pci_release_regions (pdev);
1952 pci_set_drvdata (pdev, NULL);
1954 /* pci_power_off (pdev, -1); */
1958 static struct pci_driver tulip_driver = {
1960 id_table: tulip_pci_tbl,
1961 probe: tulip_init_one,
1962 remove: __devexit_p(tulip_remove_one),
1964 suspend: tulip_suspend,
1965 resume: tulip_resume,
1966 #endif /* CONFIG_PM */
1970 static int __init tulip_init (void)
1973 printk (KERN_INFO "%s", version);
1976 /* copy module parms into globals */
1977 tulip_rx_copybreak = rx_copybreak;
1978 tulip_max_interrupt_work = max_interrupt_work;
1980 /* probe for and init boards */
1981 return pci_module_init (&tulip_driver);
1985 static void __exit tulip_cleanup (void)
1987 pci_unregister_driver (&tulip_driver);
1991 module_init(tulip_init);
1992 module_exit(tulip_cleanup);