drivers/net/wan/8253x/8253x.h

   1 /* -*- linux-c -*- */
   2 /* $Id: 8253x.h,v 1.1.1.1 2005/04/11 02:50:31 jack Exp $
   3  * sab82532.h: Register Definitions for the Siemens SAB82532 DUSCC
   4  *
   5  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   6  *
   7  * Modified Aug 1, 2000 Francois Wautier
   8  * Modified for complete driver Joachim Martillo
   9  */
  10
  11 /* Modifications:
  12  * Copyright (C) 2001 By Joachim Martillo, Telford Tools, Inc.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version
  17  * 2 of the License, or (at your option) any later version.
  18  *
  19  **/
  20
  21 #ifndef _SAB82532_H
  22 #define _SAB82532_H
  23
  24 #include <linux/types.h>
  25 #include <linux/delay.h>
  26 #include <linux/serial.h>       /* need struct async_icount for ioctl */
  27 #include <linux/netdevice.h>
  28
  29 #include "8253xioc.h"
  30 #include "ring.h"
  31
  32 #define SAB8253X_MAX_TEC_DELAY  200000 /* 1 character time (at 50 baud) */
  33 #define SAB8253X_MAX_CEC_DELAY   50000 /* 2.5 TX CLKs (at 50 baud) */
  34
  35 #define SERIAL_TYPE_SYNCTTY 3   /* check tty driver to make sure okay */
  36                                 /* SERIAL_TYPE_NORMAL and SERIAL_TYPE_CALLOUT */
  37                                 /* seem to be used by the tty driver */
  38                                 /* only to print out a warning not to */
  39                                 /* use callout devices - next version of */
  40                                 /* the code, for now want to be able to */
  41                                 /* maintain some of the structure of */
  42                                 /* a 2.2.* driver for those that are */
  43                                 /* running old kernels. */
  44
  45 #define READB(port, rreg) (*port->readbyte)(port,\
  46         (unsigned char *)&(port->regs->async_read.rreg))
  47 #define WRITEB(port, rreg, val) (*port->writebyte)(port,\
  48         (unsigned char *)&(port->regs->async_write.rreg), val)
  49 #ifdef DEFINE_VARIABLE
  50 static unsigned char tmpval;
  51 #endif
  52         /* Used in the macro below -- don't create a variable called tmpval*/
  53 #define SET_REG_BIT(port,rreg,bit)\
  54         tmpval=(*port->readbyte)(port,\
  55                 (unsigned char *)&(port->regs->async_read.rreg));\
  56         tmpval |= bit;\
  57         (*port->writebyte)(port,\
  58                 (unsigned char *)&(port->regs->async_write.rreg), tmpval);
  59 #define CLEAR_REG_BIT(port,rreg,bit)\
  60         tmpval=(*port->readbyte)(port,\
  61                 (unsigned char *)&(port->regs->async_read.rreg));\
  62         tmpval &= ~(bit);\
  63         (*port->writebyte)(port,\
  64                 (unsigned char *)&(port->regs->async_write.rreg), tmpval);
  65 #define MASK_REG_BIT(port,rreg,bit)\
  66         tmpval=(*port->readbyte)(port,\
  67                 (unsigned char *)&(port->regs->async_read.rreg));\
  68         tmpval &= bit;\
  69         (*port->writebyte)(port,\
  70                 (unsigned char *)&(port->regs->async_write.rreg), tmpval);
  71 #define READ_X_WRITEB(port,rreg,op,val)\
  72         tmpval=(*port->readbyte)(port,\
  73                 (unsigned char *)&(port->regs->async_read.rreg));\
  74         tmpval op= val;\
  75         (*port->writebyte)(port,\
  76                 (unsigned char *)&(port->regs->async_write.rreg), tmpval);
  77
  78
  79 struct sab82532_async_rd_regs
  80 {
  81         volatile unsigned char  rfifo[0x20];    /* Receive FIFO                         */
  82         volatile unsigned char  star;           /* Status Register                      */
  83         volatile unsigned char  rsta;           /* actually an HDLC register */
  84         volatile unsigned char  mode;           /* Mode Register                        */
  85         volatile unsigned char  timr;           /* Timer Register                       */
  86         volatile unsigned char  xon;            /* XON Character                        */
  87         volatile unsigned char  xoff;           /* XOFF Character                       */
  88         volatile unsigned char  tcr;            /* Termination Character Register       */
  89         volatile unsigned char  dafo;           /* Data Format                          */
  90         volatile unsigned char  rfc;            /* RFIFO Control Register               */
  91         volatile unsigned char  __pad2;
  92         volatile unsigned char  rbcl;           /* Receive Byte Count Low               */
  93         volatile unsigned char  rbch;           /* Receive Byte Count High              */
  94         volatile unsigned char  ccr0;           /* Channel Configuration Register 0     */
  95         volatile unsigned char  ccr1;           /* Channel Configuration Register 1     */
  96         volatile unsigned char  ccr2;           /* Channel Configuration Register 2     */
  97         volatile unsigned char  ccr3;           /* Channel Configuration Register 3     */
  98         volatile unsigned char  __pad3[4];
  99         volatile unsigned char  vstr;           /* Version Status Register              */
 100         volatile unsigned char  __pad4[3];
 101         volatile unsigned char  gis;            /* Global Interrupt Status              */
 102         volatile unsigned char  ipc;            /* Interrupt Port Configuration         */
 103         volatile unsigned char  isr0;           /* Interrupt Status 0                   */
 104         volatile unsigned char  isr1;           /* Interrupt Status 1                   */
 105         volatile unsigned char  pvr;            /* Port Value Register                  */
 106         volatile unsigned char  pis;            /* Port Interrupt Status                */
 107         volatile unsigned char  pcr;            /* Port Configuration Register          */
 108         volatile unsigned char  ccr4;           /* Channel Configuration Register 4     */
 109 };
 110
 111 struct sab82532_async_wr_regs
 112 {
 113         unsigned char   xfifo[0x20];    /* Transmit FIFO                        */
 114         unsigned char   cmdr;           /* Command Register                     */
 115         unsigned char   __pad1;
 116         unsigned char   mode;
 117         unsigned char   timr;
 118         unsigned char   xon;
 119         unsigned char   xoff;
 120         unsigned char   tcr;
 121         unsigned char   dafo;
 122         unsigned char   rfc;
 123         unsigned char   __pad2;
 124         unsigned char   xbcl;           /* Transmit Byte Count Low              */
 125         unsigned char   xbch;           /* Transmit Byte Count High             */
 126         unsigned char   ccr0;
 127         unsigned char   ccr1;
 128         unsigned char   ccr2;
 129         unsigned char   ccr3;
 130         unsigned char   tsax;           /* Time-Slot Assignment Reg. Transmit   */
 131         unsigned char   tsar;           /* Time-Slot Assignment Reg. Receive    */
 132         unsigned char   xccr;           /* Transmit Channel Capacity Register   */
 133         unsigned char   rccr;           /* Receive Channel Capacity Register    */
 134         unsigned char   bgr;            /* Baud Rate Generator Register         */
 135         unsigned char   tic;            /* Transmit Immediate Character         */
 136         unsigned char   mxn;            /* Mask XON Character                   */
 137         unsigned char   mxf;            /* Mask XOFF Character                  */
 138         unsigned char   iva;            /* Interrupt Vector Address             */
 139         unsigned char   ipc;
 140         unsigned char   imr0;           /* Interrupt Mask Register 0            */
 141         unsigned char   imr1;           /* Interrupt Mask Register 1            */
 142         unsigned char   pvr;
 143         unsigned char   pim;            /* Port Interrupt Mask                  */
 144         unsigned char   pcr;
 145         unsigned char   ccr4;
 146 };
 147
 148 struct sab82532_async_rw_regs
 149 {       /* Read/Write registers                 */
 150         volatile unsigned char  __pad1[0x20];
 151         volatile unsigned char  __pad2;
 152         volatile unsigned char  __pad3;
 153         volatile unsigned char  mode;
 154         volatile unsigned char  timr;
 155         volatile unsigned char  xon;
 156         volatile unsigned char  xoff;
 157         volatile unsigned char  tcr;
 158         volatile unsigned char  dafo;
 159         volatile unsigned char  rfc;
 160         volatile unsigned char  __pad4;
 161         volatile unsigned char  __pad5;
 162         volatile unsigned char  __pad6;
 163         volatile unsigned char  ccr0;
 164         volatile unsigned char  ccr1;
 165         volatile unsigned char  ccr2;
 166         volatile unsigned char  ccr3;
 167         volatile unsigned char  __pad7;
 168         volatile unsigned char  __pad8;
 169         volatile unsigned char  __pad9;
 170         volatile unsigned char  __pad10;
 171         volatile unsigned char  __pad11;
 172         volatile unsigned char  __pad12;
 173         volatile unsigned char  __pad13;
 174         volatile unsigned char  __pad14;
 175         volatile unsigned char  __pad15;
 176         volatile unsigned char  ipc;
 177         volatile unsigned char  __pad16;
 178         volatile unsigned char  __pad17;
 179         volatile unsigned char  pvr;
 180         volatile unsigned char  __pad18;
 181         volatile unsigned char  pcr;
 182         volatile unsigned char  ccr4;
 183 };
 184
 185 union sab82532_async_regs
 186 {
 187         __volatile__ struct sab82532_async_rd_regs      r;
 188         __volatile__ struct sab82532_async_wr_regs      w;
 189         __volatile__ struct sab82532_async_rw_regs      rw;
 190 };
 191
 192 /* not really used yet */
 193 struct sab82532_hdlc_rd_regs
 194 {
 195         volatile unsigned char  rfifo[0x20];    /* Receive FIFO                         */
 196         volatile unsigned char  star;           /* Status Register                      */
 197         volatile unsigned char  rsta;
 198         volatile unsigned char  mode;           /* Mode Register                        */
 199         volatile unsigned char  timr;           /* Timer Register                       */
 200         volatile unsigned char  xad1;           /* Tx Address High 1                    */
 201         volatile unsigned char  xad2;           /* Tx Address High 2                    */
 202         volatile unsigned char  __pad1[2];
 203         volatile unsigned char  ral1;           /* Rx Address Low 1                     */
 204         volatile unsigned char  rhcr;           /* Received HDLC Control                */
 205         volatile unsigned char  rbcl;           /* Receive Byte Count Low               */
 206         volatile unsigned char  rbch;           /* Receive Byte Count High              */
 207         volatile unsigned char  ccr0;           /* Channel Configuration Register 0     */
 208         volatile unsigned char  ccr1;           /* Channel Configuration Register 1     */
 209         volatile unsigned char  ccr2;           /* Channel Configuration Register 2     */
 210         volatile unsigned char  ccr3;           /* Channel Configuration Register 3     */
 211         volatile unsigned char  __pad2[4];
 212         volatile unsigned char  vstr;           /* Version Status Register              */
 213         volatile unsigned char  __pad3[3];
 214         volatile unsigned char  gis;            /* Global Interrupt Status              */
 215         volatile unsigned char  ipc;            /* Interrupt Port Configuration         */
 216         volatile unsigned char  isr0;           /* Interrupt Status 0                   */
 217         volatile unsigned char  isr1;           /* Interrupt Status 1                   */
 218         volatile unsigned char  pvr;            /* Port Value Register                  */
 219         volatile unsigned char  pis;            /* Port Interrupt Status                */
 220         volatile unsigned char  pcr;            /* Port Configuration Register          */
 221         volatile unsigned char  ccr4;           /* Channel Configuration Register 4     */
 222 };
 223
 224 struct sab82532_hdlc_wr_regs
 225 {
 226         unsigned char   xfifo[0x20];    /* Transmit FIFO                        */
 227         unsigned char   cmdr;           /* Command Register                     */
 228         unsigned char   pre;            /* Preamble                             */
 229         unsigned char   mode;
 230         unsigned char   timr;
 231         unsigned char   xad1;           /* Tx Address High 1                    */
 232         unsigned char   xad2;           /* Tx Address High 2                    */
 233         unsigned char   rah1;           /* Rx Address High 1                    */
 234         unsigned char   rah2;           /* Rx Address High 2                    */
 235         unsigned char   ral1;           /* Rx Address Low 1                     */
 236         unsigned char   ral2;           /* Rx Address Low 2                     */
 237         unsigned char   xbcl;           /* Transmit Byte Count Low              */
 238         unsigned char   xbch;           /* Transmit Byte Count High             */
 239         unsigned char   ccr0;
 240         unsigned char   ccr1;
 241         unsigned char   ccr2;
 242         unsigned char   ccr3;
 243         unsigned char   tsax;           /* Time-Slot Assignment Reg. Transmit   */
 244         unsigned char   tsar;           /* Time-Slot Assignment Reg. Receive    */
 245         unsigned char   xccr;           /* Transmit Channel Capacity Register   */
 246         unsigned char   rccr;           /* Receive Channel Capacity Register    */
 247         unsigned char   bgr;            /* Baud Rate Generator Register         */
 248         unsigned char   rlcr;           /* Rx Frame Length Check                */
 249         unsigned char   aml;            /* Address Mask Low                     */
 250         unsigned char   amh;            /* Address Mask High                    */
 251         unsigned char   iva;            /* Interrupt Vector Address             */
 252         unsigned char   ipc;
 253         unsigned char   imr0;           /* Interrupt Mask Register 0            */
 254         unsigned char   imr1;           /* Interrupt Mask Register 1            */
 255         unsigned char   pvr;
 256         unsigned char   pim;            /* Port Interrupt Mask                  */
 257         unsigned char   pcr;
 258         unsigned char   ccr4;
 259 };
 260
 261 union sab82532_regs
 262 {
 263         __volatile__ struct sab82532_async_rd_regs      async_read;
 264         __volatile__ struct sab82532_async_wr_regs      async_write;
 265         __volatile__ struct sab82532_hdlc_rd_regs       hdlc_read;
 266         __volatile__ struct sab82532_hdlc_wr_regs       hdlc_write;
 267 };
 268
 269 /*
 270  * Modem signal definition
 271  */
 272
 273 typedef struct mctlsig
 274 {
 275         unsigned char *reg;     /* chip register offset */
 276         unsigned char inverted; /* interpret the results as inverted */
 277         unsigned char mask;     /* bit within that register */
 278         unsigned char val;      /* cached value */
 279         unsigned int irq;       /* address of correct isr register */
 280         unsigned char irqmask;  /*  */
 281         unsigned char cnst;     /* A value that should always be set for
 282                                  * this signal register */
 283 } mctlsig_t, MCTLSIG;
 284
 285 union sab8253x_irq_status
 286 {
 287         unsigned int stat;
 288         unsigned char images[4];
 289         struct
 290         {
 291                 unsigned char isr0;
 292                 unsigned char isr1;
 293                 unsigned char pis;
 294         } sreg;
 295 };
 296                                 /* the following are deprecated */
 297                                 /* older version of structure above */
 298                                 /* used array*/
 299 #define      ISR0_IDX 0
 300 #define      ISR1_IDX 1
 301 #define       PIS_IDX 2
 302
 303 /*
 304  * Each port has a structure like this associated to it.
 305  * All the port are linked with the  next fields
 306  * All the port of one chip are linked with the  next_by_chip
 307  */
 308
 309 #define FUNCTION_NR     0
 310 #define FUNCTION_AO     1
 311 #define FUNCTION_NA     2
 312 #define FUNCTION_UN     3
 313
 314 typedef struct sab_port
 315 {
 316         int                             magic;
 317         union sab82532_regs             *regs;
 318         struct sab_chip                 *chip;
 319         struct sab_board                *board;
 320         struct tty_struct               *tty;
 321         unsigned char                   *xmit_buf;
 322         int                              xmit_head; /* put characters on write */
 323         int                              xmit_tail; /* read from here -- in writeb or writefifo */
 324         int                              xmit_cnt;
 325
 326         /*
 327          * Various linked list pertinent to this link
 328          */
 329         struct sab_port * next;
 330         struct sab_port * next_by_chip;
 331         struct sab_port * next_by_board;
 332         struct sab_port * next_by_cim;
 333
 334         struct net_device *dev;
 335         struct net_device *next_dev;
 336
 337         struct fasync_struct * async_queue;
 338         struct sk_buff_head *sab8253xbuflist; /* need to keep */
 339                                 /* a list of all */
 340                                 /* skbuffs so that */
 341                                 /* we can guarantee */
 342                                 /* freeing all when */
 343                                 /* the PPC is stopped */
 344                                 /* on close*/
 345         struct sk_buff_head *sab8253xc_rcvbuflist; /* used for passing */
 346                                 /* buffers from interrupt */
 347                                 /* receive process*/
 348
 349
 350         DCONTROL2 dcontrol2;
 351         DCONTROL2 active2;
 352         DCONTROL2 sabnext2;
 353
 354         int                     DoingInterrupt;
 355         int                     irq;
 356         int                     flags;         /* suggested by serial.h
 357                                                 * but this driver is
 358                                                 * more general */
 359         int                     syncflags;
 360         int                     type;          /* SAB82532/8 version */
 361         unsigned int            function;
 362         int                     read_status_mask;
 363         int                     ignore_status_mask;
 364         int                     timeout;
 365         int                     xmit_fifo_size;
 366         int                     recv_fifo_size;
 367         int                     custom_divisor;
 368         unsigned long           baud;
 369         unsigned int            ebrg;
 370         unsigned int            cec_timeout;
 371         unsigned int            tec_timeout;
 372
 373         int                     x_char;
 374         int                     close_delay;
 375         unsigned short          closing_wait;
 376         unsigned short          closing_wait2;
 377         int                     all_sent;
 378         int                     is_console;
 379 #define OPEN_NOT 0
 380 #define OPEN_ASYNC 1
 381 #define OPEN_SYNC 2
 382 #define OPEN_BSC 3
 383 #define OPEN_RAW 4
 384 #define OPEN_SYNC_NET 5
 385 #define OPEN_SYNC_CHAR 6
 386         unsigned int            open_type; /* Sync? Async?, int better for hw bps */
 387         unsigned char           interrupt_mask0;
 388         unsigned char           interrupt_mask1;
 389                                 /* Modem signals */
 390         mctlsig_t               dtr;
 391         mctlsig_t               dsr;
 392         mctlsig_t               dcd;
 393         mctlsig_t               cts;
 394         mctlsig_t               rts;
 395         mctlsig_t               txclkdir; /* Direction of TxClk */
 396         unsigned long           custspeed; /* Custom speed */
 397         unsigned long           event;
 398         unsigned long           last_active;
 399         int                     line;
 400         int                     count;
 401         int                     blocked_open;
 402         long                    session;
 403         long                    pgrp;
 404         struct tq_struct        tqueue;
 405         struct tq_struct        tqueue_hangup;
 406         struct async_icount     icount;
 407         struct termios          normal_termios;
 408         struct termios          callout_termios;
 409         wait_queue_head_t       open_wait;
 410         wait_queue_head_t       close_wait;
 411         wait_queue_head_t       delta_msr_wait;
 412         wait_queue_head_t       read_wait;
 413         wait_queue_head_t       write_wait;
 414
 415   /*
 416    * Pointer to FIFO access routines.  These are individualized
 417    *  by hardware because different hardware may have different
 418    *  ways to get to the FIFOs.
 419    */
 420
 421         void                    (*readfifo)(struct sab_port *port,
 422                                             unsigned char *buf,
 423                                             u32 nbytes);
 424         void                    (*writefifo)(struct sab_port *port);
 425
 426   /*
 427    * Pointer to register access routines.  These are individualized
 428    *  by hardware because different hardware may have different
 429    *  ways to get to the register.
 430    */
 431         unsigned char           (*readbyte)(struct sab_port *port,
 432                                             unsigned char *reg);
 433         void                    (*writebyte)(struct sab_port *port,
 434                                              unsigned char *reg,
 435                                              unsigned char val);
 436         u16                     (*readword)(struct sab_port *port,
 437                                             u16 *reg);
 438         void                    (*writeword)(struct sab_port *port,
 439                                              u16 *reg,
 440                                              u16 val);
 441
 442   /*
 443    * Pointer to protocol functions
 444    *
 445    */
 446
 447         unsigned int portno;
 448         void (*receive_chars)(struct sab_port *port,
 449                               union sab8253x_irq_status *stat);
 450         void (*transmit_chars)(struct sab_port *port,
 451                                union sab8253x_irq_status *stat);
 452         void (*check_status)(struct sab_port *port,
 453                              union sab8253x_irq_status *stat);
 454         unsigned int receive_test;
 455         unsigned int transmit_test;
 456         unsigned int check_status_test;
 457         struct channelcontrol ccontrol;
 458
 459         unsigned int tx_full;
 460         unsigned int rx_empty;
 461         struct counters Counters;
 462         struct net_device_stats stats;
 463
 464                                 /* collect statistics for netstat */
 465                                 /* etc.  those programs don't know */
 466                                 /* about priorities*/
 467
 468         int                     msgbufindex;
 469         char                    msgbuf[RXSIZE];
 470         unsigned int            buffergreedy;
 471         unsigned int            sigmode;
 472 } sab_port_t, SAB_PORT;
 473
 474 /*
 475  * per-parallel port structure
 476  */
 477
 478 /* SAB82538 4 8-bits parallel ports
 479  * To summarize the use of the parallel port:
 480  *                    RS-232
 481  * Parallel port A -- TxClkdir control  (output) ports 0 - 7
 482  * Parallel port B -- DTR               (output) ports 0 - 7
 483  * Parallel port C -- DSR               (input)  ports 0 - 7
 484  * Parallel port D -- driver power down (output) drivers 0 - 3
 485  *
 486  * SAB82532 (Aurora) 1 8-bit parallel port
 487  * To summarize the use of the parallel port:
 488  *                    RS-232
 489  *  A       B        I/O     descr
 490  * P0      P4      output  TxClk ctrl
 491  * P1      P5      output  DTR
 492  * P2      P6      input   DSR
 493  * P3      P7      output  485 control
 494  *
 495  * Note that this new version of the driver
 496  * does not support the SPARC motherboard ESCC2
 497  *
 498  * SAB82532 (Sun) 1 8-bit parallel port
 499  * To summarize the use of the parallel port:
 500  *                    RS-232
 501  *  A       B        I/O     descr
 502  * P0      P3      input    DSR
 503  * P1      P2      output    DTR
 504  * P5      P6      input     ?
 505  * P4      P7      output    ?
 506  *
 507  */
 508                                 /* not sure how usefule */
 509 typedef struct sabparport
 510 {
 511   /* cached values: */
 512         unsigned char    pp_pcr;
 513         unsigned char    pp_pim;
 514         unsigned char    pp_pvr;
 515
 516         /* register offsets: */
 517         unsigned int     pp_pcrreg;
 518         unsigned int     pp_pimreg;
 519         unsigned int     pp_pisreg;
 520         unsigned int     pp_pvrreg;
 521 } sabparport_t, SABPARPORT;
 522
 523 #define ESCC2   2
 524 #define ESCC8   8
 525
 526 /*
 527  * Per-chip structure
 528  */
 529
 530
 531 typedef struct sab_chip
 532 {
 533         unsigned int            chip_type;
 534         struct sab_board        *c_board;       /* Parent board */
 535         struct aura_cim         *c_cim;         /* if present */
 536         unsigned char           c_chipno;       /* chip number */
 537         unsigned char           c_revision;     /* the revision code from the VSTR */
 538         unsigned char           c_nports;       /* number of ports per chip */
 539         void                    *c_regs;        /* base address for chip registers */
 540         struct sab_port         *c_portbase;
 541         struct sab_chip         *next;          /* the next chip in the chip chain */
 542         struct sab_chip         *next_by_board;    /* the next chip on the board */
 543         struct sab_chip         *next_by_cim;
 544         void                    (*int_disable)(struct sab_chip* chip);
 545 } sab_chip_t, SAB_CHIP;
 546
 547
 548 /* Some useful facts */
 549 #define SAB82532_REG_SIZE               0x40
 550 #define SAB82538_REG_SIZE               0x40
 551
 552 /* RFIFO Status Byte */
 553 #define SAB82532_RSTAT_PE               0x80
 554 #define SAB82532_RSTAT_FE               0x40
 555 #define SAB82532_RSTAT_PARITY           0x01
 556
 557 /* Status Register (STAR) */
 558 #define SAB82532_STAR_XDOV              0x80
 559 #define SAB82532_STAR_XFW               0x40
 560 #define SAB82532_STAR_RFNE              0x20
 561 #define SAB82532_STAR_FCS               0x10
 562 #define SAB82532_STAR_TEC               0x08
 563 #define SAB82532_STAR_RLI               0x08
 564 #define SAB82532_STAR_CEC               0x04
 565 #define SAB82532_STAR_CTS               0x02
 566
 567 /* Command Register (CMDR) */
 568 #define SAB82532_CMDR_RMC               0x80
 569 #define SAB82532_CMDR_RRES              0x40
 570 #define SAB82532_CMDR_RHR               0x40
 571 #define SAB82532_CMDR_RFRD              0x20
 572 #define SAB82532_CMDR_STI               0x10
 573 #define SAB82532_CMDR_XF                0x08
 574 #define SAB82532_CMDR_XTF               0x08
 575 #define SAB82532_CMDR_XME               0x02
 576 #define SAB82532_CMDR_XRES              0x01
 577
 578                                 /* leaving them for reference */
 579                                 /* they are now defined in 8253xioc.h*/
 580 #if 0
 581 /* Mode Register (MODE) */
 582 #define SAB82532_MODE_TM0               0x80
 583 #define SAB82532_MODE_FRTS              0x40
 584 #define SAB82532_MODE_FCTS              0x20
 585 #define SAB82532_MODE_FLON              0x10
 586 #define SAB82532_MODE_TCPU              0x10
 587 #define SAB82532_MODE_RAC               0x08
 588 #define SAB82532_MODE_RTS               0x04
 589 #define SAB82532_MODE_TRS               0x02
 590 #define SAB82532_MODE_TLP               0x01
 591 #endif
 592
 593 /* Receive Status Register (READ)  */
 594 #define SAB82532_RSTA_VFR               0x80
 595 #define SAB82532_RSTA_RDO               0x40
 596 #define SAB82532_RSTA_CRC               0x20
 597 #define SAB82532_RSTA_RAB               0x10
 598
 599 /* Timer Register (TIMR) */
 600 #define SAB82532_TIMR_CNT_MASK          0xe0
 601 #define SAB82532_TIMR_VALUE_MASK        0x1f
 602
 603 /* Data Format (DAFO) */
 604 #define SAB82532_DAFO_XBRK              0x40
 605 #define SAB82532_DAFO_STOP              0x20
 606 #define SAB82532_DAFO_PAR_SPACE         0x00
 607 #define SAB82532_DAFO_PAR_ODD           0x08
 608 #define SAB82532_DAFO_PAR_EVEN          0x10
 609 #define SAB82532_DAFO_PAR_MARK          0x18
 610 #define SAB82532_DAFO_PARE              0x04
 611 #define SAB82532_DAFO_CHL8              0x00
 612 #define SAB82532_DAFO_CHL7              0x01
 613 #define SAB82532_DAFO_CHL6              0x02
 614 #define SAB82532_DAFO_CHL5              0x03
 615
 616 /* RFIFO Control Register (RFC) */
 617 #define SAB82532_RFC_DPS                0x40
 618 #define SAB82532_RFC_DXS                0x20
 619 #define SAB82532_RFC_RFDF               0x10
 620 #define SAB82532_RFC_RFTH_1             0x00
 621 #define SAB82532_RFC_RFTH_4             0x04
 622 #define SAB82532_RFC_RFTH_16            0x08
 623 #define SAB82532_RFC_RFTH_32            0x0c
 624 #define SAB82532_RFC_TCDE               0x01
 625
 626 /* Received Byte Count High (RBCH) */
 627 #define SAB82532_RBCH_DMA               0x80
 628 #define SAB82532_RBCH_CAS               0x20
 629 #define SAB82532_RBCH_OV                0x10
 630 #define SAB82532_RBCH_HMSK              0x0F
 631
 632 /* Transmit Byte Count High (XBCH) */
 633 #define SAB82532_XBCH_DMA               0x80
 634 #define SAB82532_XBCH_CAS               0x20
 635 #define SAB82532_XBCH_XC                0x10
 636
 637                                 /* leaving them for reference */
 638                                 /* they are now defined in 8253xioc.h*/
 639 #if 0
 640 /* Channel Configuration Register 0 (CCR0) */
 641 #define SAB82532_CCR0_PU                0x80
 642 #define SAB82532_CCR0_MCE               0x40
 643 #define SAB82532_CCR0_SC_NRZ            0x00
 644 #define SAB82532_CCR0_SC_NRZI           0x08
 645 #define SAB82532_CCR0_SC_FM0            0x10
 646 #define SAB82532_CCR0_SC_FM1            0x14
 647 #define SAB82532_CCR0_SC_MANCH          0x18
 648 #define SAB82532_CCR0_SM_HDLC           0x00
 649 #define SAB82532_CCR0_SM_SDLC_LOOP      0x01
 650 #define SAB82532_CCR0_SM_BISYNC         0x02
 651 #define SAB82532_CCR0_SM_ASYNC          0x03
 652
 653 /* Channel Configuration Register 1 (CCR1) */
 654 #define SAB82532_CCR1_SFLG              0x80
 655 #define SAB82532_CCR1_ODS               0x10
 656 #define SAB82532_CCR1_BCR               0x08
 657 #define SAB82532_CCR1_IFF               0x08
 658 #define SAB82532_CCR1_ITF               0x00
 659 #define SAB82532_CCR1_CM_MASK           0x07
 660
 661 /* Channel Configuration Register 2 (CCR2) */
 662 #define SAB82532_CCR2_SOC1              0x80
 663 #define SAB82532_CCR2_SOC0              0x40
 664 #define SAB82532_CCR2_BR9               0x80
 665 #define SAB82532_CCR2_BR8               0x40
 666 #define SAB82532_CCR2_BDF               0x20
 667 #define SAB82532_CCR2_SSEL              0x10
 668 #define SAB82532_CCR2_XCS0              0x20
 669 #define SAB82532_CCR2_RCS0              0x10
 670 #define SAB82532_CCR2_TOE               0x08
 671 #define SAB82532_CCR2_RWX               0x04
 672 #define SAB82532_CCR2_C32               0x02
 673 #define SAB82532_CCR2_DIV               0x01
 674
 675 /* Channel Configuration Register 3 (CCR3) */
 676 #define SAB82532_CCR3_PSD               0x01
 677 #define SAB82532_CCR3_RCRC              0x04
 678 #endif
 679
 680 /* Time Slot Assignment Register Transmit (TSAX) */
 681 #define SAB82532_TSAX_TSNX_MASK         0xfc
 682 #define SAB82532_TSAX_XCS2              0x02    /* see also CCR2 */
 683 #define SAB82532_TSAX_XCS1              0x01
 684
 685 /* Time Slot Assignment Register Receive (TSAR) */
 686 #define SAB82532_TSAR_TSNR_MASK         0xfc
 687 #define SAB82532_TSAR_RCS2              0x02    /* see also CCR2 */
 688 #define SAB82532_TSAR_RCS1              0x01
 689
 690 /* Version Status Register (VSTR) */
 691 #define SAB85232_REG_VSTR               0x34
 692 #define SAB82532_VSTR_CD                0x80
 693 #define SAB82532_VSTR_DPLA              0x40
 694 #define SAB82532_VSTR_VN_MASK           0x0f
 695 #define SAB82532_VSTR_VN_1              0x00
 696 #define SAB82532_VSTR_VN_2              0x01
 697 #define SAB82532_VSTR_VN_3_2            0x02
 698
 699 /* Global Interrupt Status Register (GIS) */
 700 #define SAB82532_GIS_PI                 0x80
 701 #define SAB82532_GIS_ISA1               0x08
 702 #define SAB82532_GIS_ISA0               0x04
 703 #define SAB82532_GIS_ISB1               0x02
 704 #define SAB82532_GIS_ISB0               0x01
 705 #define SAB82532_GIS_MASK               0x8f
 706 #define SAB82538_GIS_PIA                0x80
 707 #define SAB82538_GIS_PIB                0x40
 708 #define SAB82538_GIS_PIC                0x20
 709 #define SAB82538_GIS_PID                0x10
 710 #define SAB82538_GIS_CII                0x08
 711 #define SAB82538_GIS_CHNL_MASK          0x07
 712 #define SAB82538_GIS_MASK               0x28  /* Port C and CII ! */
 713
 714 /* Interrupt Vector Address (IVA) */
 715 #define SAB82532_REG_IVA                0x38
 716 #define SAB82532_IVA_MASK               0xf1
 717 #define SAB82538_IVA_ROT                0x02
 718
 719 /* Interrupt Port Configuration (IPC) */
 720 #define SAB82532_REG_IPC                0x39
 721 #define SAB82532_IPC_VIS                0x80
 722 #define SAB82532_IPC_SLA1               0x10
 723 #define SAB82532_IPC_SLA0               0x08
 724 #define SAB82532_IPC_CASM               0x04
 725 #define SAB82532_IPC_IC_OPEN_DRAIN      0x00
 726 #define SAB82532_IPC_IC_ACT_LOW         0x01
 727 #define SAB82532_IPC_IC_ACT_HIGH        0x03
 728
 729 /* Interrupt Status Register 0 (ISR0) */
 730 #define SAB82532_ISR0_TCD               0x80
 731 #define SAB82532_ISR0_RME               0x80
 732 #define SAB82532_ISR0_TIME              0x40
 733 #define SAB82532_ISR0_RFS               0x40
 734 #define SAB82532_ISR0_PERR              0x20
 735 #define SAB82532_ISR0_FERR              0x10
 736 #define SAB82532_ISR0_PLLA              0x08
 737 #define SAB82532_ISR0_CDSC              0x04
 738 #define SAB82532_ISR0_RFO               0x02
 739 #define SAB82532_ISR0_RPF               0x01
 740
 741 /* Interrupt Status Register 1 (ISR1) */
 742 #define SAB82532_ISR1_BRK               0x80
 743 #define SAB82532_ISR1_BRKT              0x40
 744 #define SAB82532_ISR1_RDO               0x40
 745 #define SAB82532_ISR1_ALLS              0x20
 746 #define SAB82532_ISR1_XOFF              0x10
 747 #define SAB82532_ISR1_XDU               0x10
 748 #define SAB82532_ISR1_TIN               0x08
 749 #define SAB82532_ISR1_CSC               0x04
 750 #define SAB82532_ISR1_XON               0x02
 751 #define SAB82532_ISR1_XPR               0x01
 752
 753 /* Interrupt Mask Register 0 (IMR0) */
 754 #define SAB82532_IMR0_TCD               0x80
 755 #define SAB82532_IMR0_RME               0x80
 756 #define SAB82532_IMR0_TIME              0x40
 757 #define SAB82532_IMR0_RFS               0x40
 758 #define SAB82532_IMR0_PERR              0x20
 759 #define SAB82532_IMR0_RSC               0x20
 760 #define SAB82532_IMR0_FERR              0x10
 761 #define SAB82532_IMR0_PCE               0x10
 762 #define SAB82532_IMR0_PLLA              0x08
 763 #define SAB82532_IMR0_CDSC              0x04
 764 #define SAB82532_IMR0_RFO               0x02
 765 #define SAB82532_IMR0_RPF               0x01
 766
 767 /* Interrupt Mask Register 1 (IMR1) */
 768 #define SAB82532_IMR1_BRK               0x80
 769 #define SAB82532_IMR1_EOP               0x80
 770 #define SAB82532_IMR1_BRKT              0x40
 771 #define SAB82532_IMR1_RDO               0x40
 772 #define SAB82532_IMR1_ALLS              0x20
 773 #define SAB82532_IMR1_XOFF              0x10
 774 #define SAB82532_IMR1_EXE               0x10
 775 #define SAB82532_IMR1_TIN               0x08
 776 #define SAB82532_IMR1_CSC               0x04
 777 #define SAB82532_IMR1_XON               0x02
 778 #define SAB82532_IMR1_XMR               0x02
 779 #define SAB82532_IMR1_XPR               0x01
 780
 781 /* Port Value Register (PVR) */
 782 #define SAB82532_REG_PVR                 0x3c
 783 #define SAB82538_REG_PVR_A               0x3c
 784 #define SAB82538_REG_PVR_B               0xbc
 785 #define SAB82538_REG_PVR_C               0x13c
 786 #define SAB82538_REG_PVR_D               0x1bc
 787
 788 /* Port Value Register (PIM) */
 789 #define SAB82532_REG_PIM                 0x3d
 790 #define SAB82538_REG_PIM_A               0x3d
 791 #define SAB82538_REG_PIM_B               0xbd
 792 #define SAB82538_REG_PIM_C               0x13d
 793 #define SAB82538_REG_PIM_D               0x1bd
 794 /* Port Value Register (PIS) */
 795 #define SAB82532_REG_PIS                 0x3d
 796 #define SAB82538_REG_PIS_A               0x3d
 797 #define SAB82538_REG_PIS_B               0xbd
 798 #define SAB82538_REG_PIS_C               0x13d
 799 #define SAB82538_REG_PIS_D               0x1bd
 800
 801 /* Port Value Register (PCR) */
 802 #define SAB82532_REG_PCR                 0x3e
 803 #define SAB82538_REG_PCR_A               0x3e
 804 #define SAB82538_REG_PCR_B               0xbe
 805 #define SAB82538_REG_PCR_C               0x13e
 806 #define SAB82538_REG_PCR_D               0x1be
 807
 808                                 /* leaving them for reference */
 809                                 /* they are now defined in 8253xioc.h*/
 810
 811 #if 0
 812 /* Channel Configuration Register 4 (CCR4) */
 813 #define SAB82532_CCR4_MCK4              0x80/* needs to be set when board clock */
 814                                             /* over 10 Mhz (?)*/
 815 #define SAB82532_CCR4_EBRG              0x40
 816 #define SAB82532_CCR4_TST1              0x20
 817 #define SAB82532_CCR4_ICD               0x10
 818 #endif
 819
 820
 821 /* Port Interrupt Status Register (PIS) */
 822 #define SAB82532_PIS_SYNC_B             0x08
 823 #define SAB82532_PIS_DTR_B              0x04
 824 #define SAB82532_PIS_DTR_A              0x02
 825 #define SAB82532_PIS_SYNC_A             0x01
 826
 827
 828 /* More things useful */
 829 #define SAB_MAGIC 5977
 830
 831 /* When computing the baudrate, we "encode" it by multiplying
 832  * the actual baudrate by 2. This way we can use 134.5
 833  */
 834 #define ENCODEBR(x)  ((x)<<1)
 835
 836 /*
 837  * Raise a modem signal y on port x, tmpval must exist! */
 838 #define RAISE(xx,y) \
 839 { \
 840           unsigned char __tmpval__; \
 841           __tmpval__= (xx)->readbyte((xx),(xx)->y.reg);\
 842           if((xx)->y.inverted)\
 843             __tmpval__ &= ~((xx)->y.mask);\
 844           else\
 845             __tmpval__ |= (xx)->y.mask;\
 846           __tmpval__ |= (xx)->y.cnst;\
 847           (xx)->y.val=1;\
 848           (xx)->writebyte((xx),(xx)->y.reg,__tmpval__);\
 849 }
 850 /*
 851  * Lower a modem signal y on port x, __tmpval__ must exist! */
 852 #define LOWER(xx,y) \
 853 {\
 854           unsigned char __tmpval__; \
 855           __tmpval__= (xx)->readbyte((xx),(xx)->y.reg);\
 856           if((xx)->y.inverted)\
 857             __tmpval__ |= (xx)->y.mask;\
 858           else\
 859             __tmpval__ &= ~((xx)->y.mask);\
 860           __tmpval__ |= (xx)->y.cnst;\
 861           (xx)->y.val=0;\
 862           (xx)->writebyte((xx),(xx)->y.reg,__tmpval__);\
 863 }
 864
 865 #define ISON(xx,y) \
 866           ((xx)->y.inverted != (((xx)->readbyte((xx),(xx)->y.reg)&(xx)->y.mask) ==(xx)->y.mask) )
 867 /*
 868  * Now let's define all those functions we need else where.
 869  *
 870  * This should probably be reorganized
 871  */
 872 extern void sab8253x_setup_ttydriver(void);
 873 extern int finish_sab8253x_setup_ttydriver(void);
 874 extern void sab8253x_setup_ttyport(struct sab_port *port);
 875 extern void sab8253x_cleanup_ttydriver(void);
 876 extern void sab8253x_start_txS(struct sab_port *port);
 877
 878 static int inline sab8253x_serial_paranoia_check(struct sab_port *port,
 879                                                  kdev_t device, const char *routine)
 880 {
 881 #ifdef SERIAL_PARANOIA_CHECK
 882         static const char *badmagic =
 883                 "Warning: bad magic number for serial struct (%s) in %s\n";
 884         static const char *badinfo =
 885                 "Warning: null sab8253x for (%s) in %s\n";
 886
 887         if (!port)
 888         {
 889                 printk(badinfo, kdevname(device), routine);
 890                 return 1;
 891         }
 892         if (port->magic != SAB_MAGIC)
 893         {
 894                 printk(badmagic, kdevname(device), routine);
 895                 return 1;
 896         }
 897 #endif
 898         return 0;
 899 }
 900
 901 static void inline sab8253x_cec_wait(struct sab_port *port)
 902 {
 903         int timeout = port->cec_timeout;
 904
 905 #if 1                           /* seems to work for 82532s */
 906         while ((READB(port, star) & SAB82532_STAR_CEC) && --timeout)
 907         {
 908                 udelay(1);
 909         }
 910 #else
 911         if (READB(port,star) & SAB82532_STAR_CEC)
 912         {
 913                 udelay(1);
 914         }
 915 #endif
 916 }
 917
 918 extern void sab8253x_transmit_charsS(struct sab_port *port, union sab8253x_irq_status *stat);
 919 extern void sab8253x_flush_charsS(struct tty_struct *tty);
 920 extern void sab8253x_set_termiosS(struct tty_struct *tty, struct termios *old_termios);
 921 extern void sab8253x_stopS(struct tty_struct *tty);
 922 extern void sab8253x_startS(struct tty_struct *tty);
 923 extern void sab8253x_send_xcharS(struct tty_struct *tty, char ch);
 924 extern void sab8253x_transmit_charsN(struct sab_port *port,
 925                                      union sab8253x_irq_status *stat);
 926 extern SAB_PORT  *AuraPortRoot;
 927
 928 #define MAX_SAB8253X_RCV_QUEUE_LEN 50
 929
 930 struct ebrg_struct
 931 {
 932         int     baud;
 933         int     n;
 934         int     m;
 935 };
 936
 937 extern task_queue tq_8253x_serial;
 938
 939 extern int sab8253x_openS(struct tty_struct *tty, struct file * filp);
 940 extern void sab8253x_closeS(struct tty_struct *tty, struct file * filp);
 941 extern int sab8253x_writeS(struct tty_struct * tty, int from_user,
 942                            const unsigned char *buf, int count);
 943 extern void sab8253x_throttleS(struct tty_struct * tty);
 944 extern void sab8253x_unthrottleS(struct tty_struct * tty);
 945 extern void sab8253x_hangupS(struct tty_struct *tty);
 946 extern void sab8253x_breakS(struct tty_struct *tty, int break_state);
 947 extern void Sab8253xCleanUpTransceiveN(SAB_PORT* priv);
 948
 949                                 /* used for running routines in the */
 950                                 /* soft int part of the driver */
 951                                 /* at one time the flip buffer routines */
 952                                 /* seem to have been too time consuming */
 953                                 /* to invoke in the hardware interrupt */
 954                                 /* routing -- I am not so sure there is */
 955                                 /* a problem with modern processor and */
 956                                 /* memory speeds, but maybe there is a */
 957                                 /* requirement that certain tty routines */
 958                                 /* not be executed with ints turned off.*/
 959
 960 static void inline sab8253x_sched_event(struct sab_port *port, int event)
 961 {
 962         port->event |= 1 << event;
 963         queue_task(&port->tqueue, &tq_8253x_serial);
 964         mark_bh(AURORA_BH);
 965 }
 966
 967 extern unsigned int
 968 sab8253x_baud(sab_port_t *port, unsigned long encbaud,
 969               unsigned char *bgr, unsigned char *ccr2,
 970               unsigned char *ccr4, unsigned long *truebaudp);
 971 extern void Sab8253xFreeAllReceiveListSKBUFFS(SAB_PORT* priv);
 972 extern int Sab8253xSetUpLists(SAB_PORT *priv);
 973 extern int Sab8253xCountTransmitDescriptors(SAB_PORT *port);
 974 extern int Sab8253xCountTransmit(SAB_PORT *port);
 975 extern void sab8253x_init_lineS(struct sab_port *port);
 976 extern void sab8253x_init_lineS(struct sab_port *port);
 977 extern int getccr2configS(struct sab_port *port);
 978 extern void sab8253x_change_speedN(struct sab_port *port);
 979 extern void sab8253x_shutdownN(struct sab_port *port);
 980 extern int sab8253x_startupN(struct sab_port *port);
 981 extern int sab8253x_block_til_ready(struct tty_struct *tty, struct file * filp,
 982                                     struct sab_port *port);
 983 extern void sab8253x_wait_until_sent(struct tty_struct *tty, int timeout);
 984 extern void sab8253x_flush_buffer(struct tty_struct *tty);
 985 extern void aura_sp502_program(SAB_PORT *port, unsigned int index);
 986 #endif