1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
3 * Authors: Phil Blundell <Philip.Blundell@pobox.com>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell <campbell@torque.net>
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
18 /* This driver should work with any hardware that is broadly compatible
19 * with that in the IBM PC. This applies to the majority of integrated
20 * I/O chipsets that are commonly available. The expected register
27 * In addition, there are some optional registers:
31 * base+0x400 ECP config A
32 * base+0x401 ECP config B
33 * base+0x402 ECP control
35 * All registers are 8 bits wide and read/write. If your hardware differs
36 * only in register addresses (eg because your registers are on 32-bit
37 * word boundaries) then you can alter the constants in parport_pc.h to
40 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
41 * but rather will start at port->base_hi.
44 #include <linux/config.h>
45 #include <linux/module.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
49 #include <linux/errno.h>
50 #include <linux/interrupt.h>
51 #include <linux/ioport.h>
52 #include <linux/kernel.h>
53 #include <linux/slab.h>
54 #include <linux/pci.h>
55 #include <linux/sysctl.h>
59 #include <asm/uaccess.h>
61 #include <linux/parport.h>
62 #include <linux/parport_pc.h>
63 #include <asm/parport.h>
65 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
76 #define ECR_MODE_MASK 0xe0
77 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
82 #define DPRINTK printk
84 #define DPRINTK(stuff...)
89 static struct superio_struct { /* For Super-IO chips autodetection */
93 } superios[NR_SUPERIOS] __devinitdata = { {0,},};
95 static int user_specified __devinitdata = 0;
96 #if defined(CONFIG_PARPORT_PC_FIFO) || defined(CONFIG_PARPORT_PC_SUPERIO)
97 static int verbose_probing;
99 static int registered_parport;
101 /* frob_control, but for ECR */
102 static void frob_econtrol (struct parport *pb, unsigned char m,
105 unsigned char ectr = 0;
108 ectr = inb (ECONTROL (pb));
110 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
111 m, v, ectr, (ectr & ~m) ^ v);
113 outb ((ectr & ~m) ^ v, ECONTROL (pb));
116 static void __inline__ frob_set_mode (struct parport *p, int mode)
118 frob_econtrol (p, ECR_MODE_MASK, mode << 5);
121 #ifdef CONFIG_PARPORT_PC_FIFO
122 /* Safely change the mode bits in the ECR
125 -EBUSY: Could not drain FIFO in some finite amount of time,
128 static int change_mode(struct parport *p, int m)
130 const struct parport_pc_private *priv = p->physport->private_data;
134 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
137 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
141 /* Bits <7:5> contain the mode. */
142 oecr = inb (ECONTROL (p));
143 mode = (oecr >> 5) & 0x7;
144 if (mode == m) return 0;
146 if (mode >= 2 && !(priv->ctr & 0x20)) {
147 /* This mode resets the FIFO, so we may
148 * have to wait for it to drain first. */
149 long expire = jiffies + p->physport->cad->timeout;
152 case ECR_PPF: /* Parallel Port FIFO mode */
153 case ECR_ECP: /* ECP Parallel Port mode */
154 /* Busy wait for 200us */
155 for (counter = 0; counter < 40; counter++) {
156 if (inb (ECONTROL (p)) & 0x01)
158 if (signal_pending (current)) break;
163 while (!(inb (ECONTROL (p)) & 0x01)) {
164 if (time_after_eq (jiffies, expire))
165 /* The FIFO is stuck. */
167 __set_current_state (TASK_INTERRUPTIBLE);
168 schedule_timeout ((HZ + 99) / 100);
169 if (signal_pending (current))
175 if (mode >= 2 && m >= 2) {
176 /* We have to go through mode 001 */
178 oecr |= ECR_PS2 << 5;
189 #ifdef CONFIG_PARPORT_1284
190 /* Find FIFO lossage; FIFO is reset */
191 static int get_fifo_residue (struct parport *p)
195 const struct parport_pc_private *priv = p->physport->private_data;
197 /* Adjust for the contents of the FIFO. */
198 for (residue = priv->fifo_depth; ; residue--) {
199 if (inb (ECONTROL (p)) & 0x2)
206 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
209 /* Reset the FIFO. */
210 frob_set_mode (p, ECR_PS2);
212 /* Now change to config mode and clean up. FIXME */
213 frob_set_mode (p, ECR_CNF);
214 cnfga = inb (CONFIGA (p));
215 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
217 if (!(cnfga & (1<<2))) {
218 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
222 /* Don't care about partial PWords until support is added for
223 * PWord != 1 byte. */
225 /* Back to PS2 mode. */
226 frob_set_mode (p, ECR_PS2);
228 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
231 #endif /* IEEE 1284 support */
232 #endif /* FIFO support */
235 * Clear TIMEOUT BIT in EPP MODE
237 * This is also used in SPP detection.
239 static int clear_epp_timeout(struct parport *pb)
243 if (!(parport_pc_read_status(pb) & 0x01))
246 /* To clear timeout some chips require double read */
247 parport_pc_read_status(pb);
248 r = parport_pc_read_status(pb);
249 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
250 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
251 r = parport_pc_read_status(pb);
259 * Most of these aren't static because they may be used by the
260 * parport_xxx_yyy macros. extern __inline__ versions of several
261 * of these are in parport_pc.h.
264 static void parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
266 parport_generic_irq(irq, (struct parport *) dev_id, regs);
269 void parport_pc_write_data(struct parport *p, unsigned char d)
274 unsigned char parport_pc_read_data(struct parport *p)
276 return inb (DATA (p));
279 void parport_pc_write_control(struct parport *p, unsigned char d)
281 const unsigned char wm = (PARPORT_CONTROL_STROBE |
282 PARPORT_CONTROL_AUTOFD |
283 PARPORT_CONTROL_INIT |
284 PARPORT_CONTROL_SELECT);
286 /* Take this out when drivers have adapted to the newer interface. */
288 printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
289 p->name, p->cad->name);
290 parport_pc_data_reverse (p);
293 __parport_pc_frob_control (p, wm, d & wm);
296 unsigned char parport_pc_read_control(struct parport *p)
298 const unsigned char wm = (PARPORT_CONTROL_STROBE |
299 PARPORT_CONTROL_AUTOFD |
300 PARPORT_CONTROL_INIT |
301 PARPORT_CONTROL_SELECT);
302 const struct parport_pc_private *priv = p->physport->private_data;
303 return priv->ctr & wm; /* Use soft copy */
306 unsigned char parport_pc_frob_control (struct parport *p, unsigned char mask,
309 const unsigned char wm = (PARPORT_CONTROL_STROBE |
310 PARPORT_CONTROL_AUTOFD |
311 PARPORT_CONTROL_INIT |
312 PARPORT_CONTROL_SELECT);
314 /* Take this out when drivers have adapted to the newer interface. */
316 printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
317 p->name, p->cad->name,
318 (val & 0x20) ? "reverse" : "forward");
320 parport_pc_data_reverse (p);
322 parport_pc_data_forward (p);
325 /* Restrict mask and val to control lines. */
329 return __parport_pc_frob_control (p, mask, val);
332 unsigned char parport_pc_read_status(struct parport *p)
334 return inb (STATUS (p));
337 void parport_pc_disable_irq(struct parport *p)
339 __parport_pc_frob_control (p, 0x10, 0);
342 void parport_pc_enable_irq(struct parport *p)
344 if (p->irq != PARPORT_IRQ_NONE)
345 __parport_pc_frob_control (p, 0x10, 0x10);
348 void parport_pc_data_forward (struct parport *p)
350 __parport_pc_frob_control (p, 0x20, 0);
353 void parport_pc_data_reverse (struct parport *p)
355 __parport_pc_frob_control (p, 0x20, 0x20);
358 void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
362 dev->port->irq != PARPORT_IRQ_NONE)
366 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
370 void parport_pc_save_state(struct parport *p, struct parport_state *s)
372 const struct parport_pc_private *priv = p->physport->private_data;
373 s->u.pc.ctr = priv->ctr;
375 s->u.pc.ecr = inb (ECONTROL (p));
378 void parport_pc_restore_state(struct parport *p, struct parport_state *s)
380 struct parport_pc_private *priv = p->physport->private_data;
381 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
382 outb (c, CONTROL (p));
385 ECR_WRITE (p, s->u.pc.ecr);
388 #ifdef CONFIG_PARPORT_1284
389 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
390 size_t length, int flags)
394 if (flags & PARPORT_W91284PIC) {
395 unsigned char status;
396 size_t left = length;
398 /* use knowledge about data lines..:
399 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
400 * pError is 1 if there are 16 bytes in the Warp's FIFO
402 status = inb (STATUS (port));
404 while (!(status & 0x08) && (got < length)) {
405 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
406 /* can grab 16 bytes from warp fifo */
407 if (!((long)buf & 0x03)) {
408 insl (EPPDATA (port), buf, 4);
410 insb (EPPDATA (port), buf, 16);
416 /* grab single byte from the warp fifo */
417 *((char *)buf)++ = inb (EPPDATA (port));
421 status = inb (STATUS (port));
423 /* EPP timeout should never occur... */
424 printk (KERN_DEBUG "%s: EPP timeout occured while talking to "
425 "w91284pic (should not have done)\n", port->name);
426 clear_epp_timeout (port);
431 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
432 if (!(((long)buf | length) & 0x03)) {
433 insl (EPPDATA (port), buf, (length >> 2));
435 insb (EPPDATA (port), buf, length);
437 if (inb (STATUS (port)) & 0x01) {
438 clear_epp_timeout (port);
443 for (; got < length; got++) {
444 *((char*)buf)++ = inb (EPPDATA(port));
445 if (inb (STATUS (port)) & 0x01) {
447 clear_epp_timeout (port);
455 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
456 size_t length, int flags)
460 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
461 if (!(((long)buf | length) & 0x03)) {
462 outsl (EPPDATA (port), buf, (length >> 2));
464 outsb (EPPDATA (port), buf, length);
466 if (inb (STATUS (port)) & 0x01) {
467 clear_epp_timeout (port);
472 for (; written < length; written++) {
473 outb (*((char*)buf)++, EPPDATA(port));
474 if (inb (STATUS(port)) & 0x01) {
475 clear_epp_timeout (port);
483 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
484 size_t length, int flags)
488 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
489 insb (EPPADDR (port), buf, length);
490 if (inb (STATUS (port)) & 0x01) {
491 clear_epp_timeout (port);
496 for (; got < length; got++) {
497 *((char*)buf)++ = inb (EPPADDR (port));
498 if (inb (STATUS (port)) & 0x01) {
499 clear_epp_timeout (port);
507 static size_t parport_pc_epp_write_addr (struct parport *port,
508 const void *buf, size_t length,
513 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
514 outsb (EPPADDR (port), buf, length);
515 if (inb (STATUS (port)) & 0x01) {
516 clear_epp_timeout (port);
521 for (; written < length; written++) {
522 outb (*((char*)buf)++, EPPADDR (port));
523 if (inb (STATUS (port)) & 0x01) {
524 clear_epp_timeout (port);
532 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
533 size_t length, int flags)
537 frob_set_mode (port, ECR_EPP);
538 parport_pc_data_reverse (port);
539 parport_pc_write_control (port, 0x4);
540 got = parport_pc_epp_read_data (port, buf, length, flags);
541 frob_set_mode (port, ECR_PS2);
546 static size_t parport_pc_ecpepp_write_data (struct parport *port,
547 const void *buf, size_t length,
552 frob_set_mode (port, ECR_EPP);
553 parport_pc_write_control (port, 0x4);
554 parport_pc_data_forward (port);
555 written = parport_pc_epp_write_data (port, buf, length, flags);
556 frob_set_mode (port, ECR_PS2);
561 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
562 size_t length, int flags)
566 frob_set_mode (port, ECR_EPP);
567 parport_pc_data_reverse (port);
568 parport_pc_write_control (port, 0x4);
569 got = parport_pc_epp_read_addr (port, buf, length, flags);
570 frob_set_mode (port, ECR_PS2);
575 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
576 const void *buf, size_t length,
581 frob_set_mode (port, ECR_EPP);
582 parport_pc_write_control (port, 0x4);
583 parport_pc_data_forward (port);
584 written = parport_pc_epp_write_addr (port, buf, length, flags);
585 frob_set_mode (port, ECR_PS2);
589 #endif /* IEEE 1284 support */
591 #ifdef CONFIG_PARPORT_PC_FIFO
592 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
593 const void *buf, size_t length)
596 const unsigned char *bufp = buf;
597 size_t left = length;
598 long expire = jiffies + port->physport->cad->timeout;
599 const int fifo = FIFO (port);
600 int poll_for = 8; /* 80 usecs */
601 const struct parport_pc_private *priv = port->physport->private_data;
602 const int fifo_depth = priv->fifo_depth;
604 port = port->physport;
606 /* We don't want to be interrupted every character. */
607 parport_pc_disable_irq (port);
608 /* set nErrIntrEn and serviceIntr */
609 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
612 parport_pc_data_forward (port); /* Must be in PS2 mode */
616 unsigned char ecrval = inb (ECONTROL (port));
619 if (current->need_resched && time_before (jiffies, expire))
620 /* Can't yield the port. */
623 /* Anyone else waiting for the port? */
624 if (port->waithead) {
625 printk (KERN_DEBUG "Somebody wants the port\n");
630 /* FIFO is full. Wait for interrupt. */
632 /* Clear serviceIntr */
633 ECR_WRITE (port, ecrval & ~(1<<2));
635 ret = parport_wait_event (port, HZ);
638 if (!time_before (jiffies, expire)) {
640 printk (KERN_DEBUG "FIFO write timed out\n");
643 ecrval = inb (ECONTROL (port));
644 if (!(ecrval & (1<<2))) {
645 if (current->need_resched &&
646 time_before (jiffies, expire))
655 /* Can't fail now. */
656 expire = jiffies + port->cad->timeout;
659 if (signal_pending (current))
663 /* FIFO is empty. Blast it full. */
664 const int n = left < fifo_depth ? left : fifo_depth;
665 outsb (fifo, bufp, n);
669 /* Adjust the poll time. */
670 if (i < (poll_for - 2)) poll_for--;
672 } else if (i++ < poll_for) {
674 ecrval = inb (ECONTROL (port));
678 /* Half-full (call me an optimist) */
684 dump_parport_state ("leave fifo_write_block_pio", port);
685 return length - left;
688 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
689 const void *buf, size_t length)
692 unsigned long dmaflag;
693 size_t left = length;
694 const struct parport_pc_private *priv = port->physport->private_data;
695 dma_addr_t dma_addr, dma_handle;
696 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
697 unsigned long start = (unsigned long) buf;
698 unsigned long end = (unsigned long) buf + length - 1;
700 dump_parport_state ("enter fifo_write_block_dma", port);
701 if (end < MAX_DMA_ADDRESS) {
702 /* If it would cross a 64k boundary, cap it at the end. */
703 if ((start ^ end) & ~0xffffUL)
704 maxlen = 0x10000 - (start & 0xffff);
706 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
709 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
710 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
711 dma_addr = priv->dma_handle;
715 port = port->physport;
717 /* We don't want to be interrupted every character. */
718 parport_pc_disable_irq (port);
719 /* set nErrIntrEn and serviceIntr */
720 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
723 parport_pc_data_forward (port); /* Must be in PS2 mode */
726 long expire = jiffies + port->physport->cad->timeout;
733 if (!dma_handle) /* bounce buffer ! */
734 memcpy(priv->dma_buf, buf, count);
736 dmaflag = claim_dma_lock();
737 disable_dma(port->dma);
738 clear_dma_ff(port->dma);
739 set_dma_mode(port->dma, DMA_MODE_WRITE);
740 set_dma_addr(port->dma, dma_addr);
741 set_dma_count(port->dma, count);
744 frob_econtrol (port, 1<<3, 1<<3);
746 /* Clear serviceIntr */
747 frob_econtrol (port, 1<<2, 0);
749 enable_dma(port->dma);
750 release_dma_lock(dmaflag);
752 /* assume DMA will be successful */
755 if (dma_handle) dma_addr += count;
757 /* Wait for interrupt. */
759 ret = parport_wait_event (port, HZ);
762 if (!time_before (jiffies, expire)) {
764 printk (KERN_DEBUG "DMA write timed out\n");
767 /* Is serviceIntr set? */
768 if (!(inb (ECONTROL (port)) & (1<<2))) {
769 if (current->need_resched)
775 dmaflag = claim_dma_lock();
776 disable_dma(port->dma);
777 clear_dma_ff(port->dma);
778 count = get_dma_residue(port->dma);
779 release_dma_lock(dmaflag);
781 if (current->need_resched)
782 /* Can't yield the port. */
785 /* Anyone else waiting for the port? */
786 if (port->waithead) {
787 printk (KERN_DEBUG "Somebody wants the port\n");
791 /* update for possible DMA residue ! */
794 if (dma_handle) dma_addr -= count;
797 /* Maybe got here through break, so adjust for DMA residue! */
798 dmaflag = claim_dma_lock();
799 disable_dma(port->dma);
800 clear_dma_ff(port->dma);
801 left += get_dma_residue(port->dma);
802 release_dma_lock(dmaflag);
804 /* Turn off DMA mode */
805 frob_econtrol (port, 1<<3, 0);
808 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
810 dump_parport_state ("leave fifo_write_block_dma", port);
811 return length - left;
814 /* Parallel Port FIFO mode (ECP chipsets) */
815 size_t parport_pc_compat_write_block_pio (struct parport *port,
816 const void *buf, size_t length,
822 const struct parport_pc_private *priv = port->physport->private_data;
824 /* Special case: a timeout of zero means we cannot call schedule().
825 * Also if O_NONBLOCK is set then use the default implementation. */
826 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
827 return parport_ieee1284_write_compat (port, buf,
830 /* Set up parallel port FIFO mode.*/
831 parport_pc_data_forward (port); /* Must be in PS2 mode */
832 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
833 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
834 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
836 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
838 /* Write the data to the FIFO. */
839 if (port->dma != PARPORT_DMA_NONE)
840 written = parport_pc_fifo_write_block_dma (port, buf, length);
842 written = parport_pc_fifo_write_block_pio (port, buf, length);
845 /* For some hardware we don't want to touch the mode until
846 * the FIFO is empty, so allow 4 seconds for each position
849 expire = jiffies + (priv->fifo_depth * HZ * 4);
851 /* Wait for the FIFO to empty */
852 r = change_mode (port, ECR_PS2);
856 } while (time_before (jiffies, expire));
859 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
861 /* Prevent further data transfer. */
862 frob_set_mode (port, ECR_TST);
864 /* Adjust for the contents of the FIFO. */
865 for (written -= priv->fifo_depth; ; written++) {
866 if (inb (ECONTROL (port)) & 0x2) {
870 outb (0, FIFO (port));
873 /* Reset the FIFO and return to PS2 mode. */
874 frob_set_mode (port, ECR_PS2);
877 r = parport_wait_peripheral (port,
879 PARPORT_STATUS_BUSY);
882 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
885 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
891 #ifdef CONFIG_PARPORT_1284
892 size_t parport_pc_ecp_write_block_pio (struct parport *port,
893 const void *buf, size_t length,
899 const struct parport_pc_private *priv = port->physport->private_data;
901 /* Special case: a timeout of zero means we cannot call schedule().
902 * Also if O_NONBLOCK is set then use the default implementation. */
903 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
904 return parport_ieee1284_ecp_write_data (port, buf,
907 /* Switch to forward mode if necessary. */
908 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
909 /* Event 47: Set nInit high. */
910 parport_frob_control (port,
912 | PARPORT_CONTROL_AUTOFD,
914 | PARPORT_CONTROL_AUTOFD);
916 /* Event 49: PError goes high. */
917 r = parport_wait_peripheral (port,
918 PARPORT_STATUS_PAPEROUT,
919 PARPORT_STATUS_PAPEROUT);
921 printk (KERN_DEBUG "%s: PError timeout (%d) "
922 "in ecp_write_block_pio\n", port->name, r);
926 /* Set up ECP parallel port mode.*/
927 parport_pc_data_forward (port); /* Must be in PS2 mode */
928 parport_pc_frob_control (port,
929 PARPORT_CONTROL_STROBE |
930 PARPORT_CONTROL_AUTOFD,
932 r = change_mode (port, ECR_ECP); /* ECP FIFO */
933 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
934 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
936 /* Write the data to the FIFO. */
937 if (port->dma != PARPORT_DMA_NONE)
938 written = parport_pc_fifo_write_block_dma (port, buf, length);
940 written = parport_pc_fifo_write_block_pio (port, buf, length);
943 /* For some hardware we don't want to touch the mode until
944 * the FIFO is empty, so allow 4 seconds for each position
947 expire = jiffies + (priv->fifo_depth * (HZ * 4));
949 /* Wait for the FIFO to empty */
950 r = change_mode (port, ECR_PS2);
954 } while (time_before (jiffies, expire));
957 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
959 /* Prevent further data transfer. */
960 frob_set_mode (port, ECR_TST);
962 /* Adjust for the contents of the FIFO. */
963 for (written -= priv->fifo_depth; ; written++) {
964 if (inb (ECONTROL (port)) & 0x2) {
968 outb (0, FIFO (port));
971 /* Reset the FIFO and return to PS2 mode. */
972 frob_set_mode (port, ECR_PS2);
974 /* Host transfer recovery. */
975 parport_pc_data_reverse (port); /* Must be in PS2 mode */
977 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
978 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
980 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
981 "in ecp_write_block_pio\n", port->name, r);
983 parport_frob_control (port,
984 PARPORT_CONTROL_INIT,
985 PARPORT_CONTROL_INIT);
986 r = parport_wait_peripheral (port,
987 PARPORT_STATUS_PAPEROUT,
988 PARPORT_STATUS_PAPEROUT);
990 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
991 "in ecp_write_block_pio\n", port->name, r);
994 r = parport_wait_peripheral (port,
996 PARPORT_STATUS_BUSY);
999 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
1002 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1007 size_t parport_pc_ecp_read_block_pio (struct parport *port,
1008 void *buf, size_t length, int flags)
1010 size_t left = length;
1013 const int fifo = FIFO(port);
1014 const struct parport_pc_private *priv = port->physport->private_data;
1015 const int fifo_depth = priv->fifo_depth;
1018 port = port->physport;
1019 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
1020 dump_parport_state ("enter fcn", port);
1022 /* Special case: a timeout of zero means we cannot call schedule().
1023 * Also if O_NONBLOCK is set then use the default implementation. */
1024 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1025 return parport_ieee1284_ecp_read_data (port, buf,
1028 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
1029 /* If the peripheral is allowed to send RLE compressed
1030 * data, it is possible for a byte to expand to 128
1031 * bytes in the FIFO. */
1034 fifofull = fifo_depth;
1037 /* If the caller wants less than a full FIFO's worth of data,
1038 * go through software emulation. Otherwise we may have to throw
1040 if (length < fifofull)
1041 return parport_ieee1284_ecp_read_data (port, buf,
1044 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
1045 /* change to reverse-idle phase (must be in forward-idle) */
1047 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
1048 parport_frob_control (port,
1049 PARPORT_CONTROL_AUTOFD
1050 | PARPORT_CONTROL_STROBE,
1051 PARPORT_CONTROL_AUTOFD);
1052 parport_pc_data_reverse (port); /* Must be in PS2 mode */
1054 /* Event 39: Set nInit low to initiate bus reversal */
1055 parport_frob_control (port,
1056 PARPORT_CONTROL_INIT,
1058 /* Event 40: Wait for nAckReverse (PError) to go low */
1059 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
1061 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
1062 "in ecp_read_block_pio\n", port->name, r);
1067 /* Set up ECP FIFO mode.*/
1068 /* parport_pc_frob_control (port,
1069 PARPORT_CONTROL_STROBE |
1070 PARPORT_CONTROL_AUTOFD,
1071 PARPORT_CONTROL_AUTOFD); */
1072 r = change_mode (port, ECR_ECP); /* ECP FIFO */
1073 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
1075 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1077 /* the first byte must be collected manually */
1078 dump_parport_state ("pre 43", port);
1079 /* Event 43: Wait for nAck to go low */
1080 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1082 /* timed out while reading -- no data */
1083 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1087 *bufp++ = inb (DATA (port));
1089 dump_parport_state ("43-44", port);
1090 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1091 parport_pc_frob_control (port,
1092 PARPORT_CONTROL_AUTOFD,
1094 dump_parport_state ("pre 45", port);
1095 /* Event 45: Wait for nAck to go high */
1096 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1097 dump_parport_state ("post 45", port);
1100 /* timed out while waiting for peripheral to respond to ack */
1101 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1103 /* keep hold of the byte we've got already */
1106 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1107 parport_pc_frob_control (port,
1108 PARPORT_CONTROL_AUTOFD,
1109 PARPORT_CONTROL_AUTOFD);
1112 dump_parport_state ("rev idle", port);
1113 /* Do the transfer. */
1114 while (left > fifofull) {
1116 long int expire = jiffies + port->cad->timeout;
1117 unsigned char ecrval = inb (ECONTROL (port));
1119 if (current->need_resched && time_before (jiffies, expire))
1120 /* Can't yield the port. */
1123 /* At this point, the FIFO may already be full. In
1124 * that case ECP is already holding back the
1125 * peripheral (assuming proper design) with a delayed
1126 * handshake. Work fast to avoid a peripheral
1129 if (ecrval & 0x01) {
1130 /* FIFO is empty. Wait for interrupt. */
1131 dump_parport_state ("FIFO empty", port);
1133 /* Anyone else waiting for the port? */
1134 if (port->waithead) {
1135 printk (KERN_DEBUG "Somebody wants the port\n");
1139 /* Clear serviceIntr */
1140 ECR_WRITE (port, ecrval & ~(1<<2));
1142 dump_parport_state ("waiting", port);
1143 ret = parport_wait_event (port, HZ);
1144 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1148 if (!time_before (jiffies, expire)) {
1150 dump_parport_state ("timeout", port);
1151 printk (KERN_DEBUG "PIO read timed out\n");
1154 ecrval = inb (ECONTROL (port));
1155 if (!(ecrval & (1<<2))) {
1156 if (current->need_resched &&
1157 time_before (jiffies, expire)) {
1163 /* Depending on how the FIFO threshold was
1164 * set, how long interrupt service took, and
1165 * how fast the peripheral is, we might be
1166 * lucky and have a just filled FIFO. */
1170 if (ecrval & 0x02) {
1172 dump_parport_state ("FIFO full", port);
1173 insb (fifo, bufp, fifo_depth);
1179 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1181 /* FIFO not filled. We will cycle this loop for a while
1182 * and either the peripheral will fill it faster,
1183 * tripping a fast empty with insb, or we empty it. */
1184 *bufp++ = inb (fifo);
1188 /* scoop up anything left in the FIFO */
1189 while (left && !(inb (ECONTROL (port) & 0x01))) {
1190 *bufp++ = inb (fifo);
1194 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1195 dump_parport_state ("rev idle2", port);
1199 /* Go to forward idle mode to shut the peripheral up (event 47). */
1200 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1202 /* event 49: PError goes high */
1203 r = parport_wait_peripheral (port,
1204 PARPORT_STATUS_PAPEROUT,
1205 PARPORT_STATUS_PAPEROUT);
1208 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1212 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1216 int lost = get_fifo_residue (port);
1218 /* Shouldn't happen with compliant peripherals. */
1219 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1223 dump_parport_state ("fwd idle", port);
1224 return length - left;
1227 #endif /* IEEE 1284 support */
1228 #endif /* Allowed to use FIFO/DMA */
1232 * ******************************************
1233 * INITIALISATION AND MODULE STUFF BELOW HERE
1234 * ******************************************
1238 void parport_pc_inc_use_count(void)
1245 void parport_pc_dec_use_count(void)
1252 struct parport_operations parport_pc_ops =
1254 parport_pc_write_data,
1255 parport_pc_read_data,
1257 parport_pc_write_control,
1258 parport_pc_read_control,
1259 parport_pc_frob_control,
1261 parport_pc_read_status,
1263 parport_pc_enable_irq,
1264 parport_pc_disable_irq,
1266 parport_pc_data_forward,
1267 parport_pc_data_reverse,
1269 parport_pc_init_state,
1270 parport_pc_save_state,
1271 parport_pc_restore_state,
1273 parport_pc_inc_use_count,
1274 parport_pc_dec_use_count,
1276 parport_ieee1284_epp_write_data,
1277 parport_ieee1284_epp_read_data,
1278 parport_ieee1284_epp_write_addr,
1279 parport_ieee1284_epp_read_addr,
1281 parport_ieee1284_ecp_write_data,
1282 parport_ieee1284_ecp_read_data,
1283 parport_ieee1284_ecp_write_addr,
1285 parport_ieee1284_write_compat,
1286 parport_ieee1284_read_nibble,
1287 parport_ieee1284_read_byte,
1290 #ifdef CONFIG_PARPORT_PC_SUPERIO
1291 /* Super-IO chipset detection, Winbond, SMSC */
1292 static void __devinit show_parconfig_smsc37c669(int io, int key)
1294 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1295 static const char *modes[]={ "SPP and Bidirectional (PS/2)",
1316 if (verbose_probing) {
1317 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1318 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1319 cr1,cr4,cra,cr23,cr26,cr27);
1321 /* The documentation calls DMA and IRQ-Lines by letters, so
1322 the board maker can/will wire them
1323 appropriately/randomly... G=reserved H=IDE-irq, */
1324 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1325 "fifo threshold=%d\n", cr23*4,
1326 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1327 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1328 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1329 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1330 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1331 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1332 (cr4 & 0x40) ? "1.7" : "1.9");
1335 /* Heuristics ! BIOS setup for this mainboard device limits
1336 the choices to standard settings, i.e. io-address and IRQ
1337 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1338 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1339 if(cr23*4 >=0x100) { /* if active */
1340 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1343 printk(KERN_INFO "Super-IO: too many chips!\n");
1348 superios[i].io = 0x3bc;
1349 superios[i].irq = 7;
1352 superios[i].io = 0x378;
1353 superios[i].irq = 7;
1356 superios[i].io = 0x278;
1357 superios[i].irq = 5;
1360 if((d==1) || (d==3))
1363 superios[i].dma= PARPORT_DMA_NONE;
1369 static void __devinit show_parconfig_winbond(int io, int key)
1371 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1372 static const char *modes[] = {
1373 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1378 "EPP-1.7 and SPP", /* 5 */
1380 "ECP and EPP-1.7" };
1381 static char *irqtypes[] = { "pulsed low, high-Z", "follows nACK" };
1383 /* The registers are called compatible-PnP because the
1384 register layout is modelled after ISA-PnP, the access
1385 method is just another ... */
1388 outb(0x07,io); /* Register 7: Select Logical Device */
1389 outb(0x01,io+1); /* LD1 is Parallel Port */
1404 if (verbose_probing) {
1405 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1406 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1407 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1408 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1409 if ((cr74 & 0x07) > 3)
1410 printk("dma=none\n");
1412 printk("dma=%d\n",cr74 & 0x07);
1413 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1414 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1415 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1418 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1419 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1422 printk(KERN_INFO "Super-IO: too many chips!\n");
1424 superios[i].io = (cr60<<8)|cr61;
1425 superios[i].irq = cr70&0x0f;
1426 superios[i].dma = (((cr74 & 0x07) > 3) ?
1427 PARPORT_DMA_NONE : (cr74 & 0x07));
1432 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1434 const char *type = "unknown";
1437 if (devid == devrev)
1438 /* simple heuristics, we happened to read some
1439 non-winbond register */
1442 id=(devid<<8) | devrev;
1444 /* Values are from public data sheets pdf files, I can just
1445 confirm 83977TF is correct :-) */
1446 if (id == 0x9771) type="83977F/AF";
1447 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1448 else if (id == 0x9774) type="83977ATF";
1449 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1450 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1451 else if ((id & ~0x0f) == 0x5210) type="83627";
1452 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1453 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1454 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1455 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1456 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1459 if (verbose_probing)
1460 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1461 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1462 efer, key, devid, devrev, oldid, type);
1465 show_parconfig_winbond(efer,key);
1468 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1470 const char *type = "unknown";
1471 void (*func)(int io, int key);
1474 if (devid == devrev)
1475 /* simple heuristics, we happened to read some
1476 non-smsc register */
1480 id=(devid<<8) | devrev;
1482 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1483 else if (id==0x6582) type="37c665IR";
1484 else if (devid==0x65) type="37c665GT";
1485 else if (devid==0x66) type="37c666GT";
1487 if (verbose_probing)
1488 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1489 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1490 efer, key, devid, devrev, type);
1497 static void __devinit winbond_check(int io, int key)
1499 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1501 /* First probe without key */
1510 outb(key,io); /* Write Magic Sequence to EFER, extended
1511 funtion enable register */
1512 outb(0x20,io); /* Write EFIR, extended function index register */
1513 devid=inb(io+1); /* Read EFDR, extended function data register */
1518 outb(0xaa,io); /* Magic Seal */
1520 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1521 return; /* protection against false positives */
1523 decode_winbond(io,key,devid,devrev,oldid);
1526 static void __devinit winbond_check2(int io,int key)
1528 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1530 /* First probe without the key */
1538 outb(key,io); /* Write Magic Byte to EFER, extended
1539 funtion enable register */
1540 outb(0x20,io+2); /* Write EFIR, extended function index register */
1541 devid=inb(io+2); /* Read EFDR, extended function data register */
1546 outb(0xaa,io); /* Magic Seal */
1548 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1549 return; /* protection against false positives */
1551 decode_winbond(io,key,devid,devrev,oldid);
1554 static void __devinit smsc_check(int io, int key)
1556 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1558 /* First probe without the key */
1569 outb(key,io); /* Write Magic Sequence to EFER, extended
1570 funtion enable register */
1571 outb(0x0d,io); /* Write EFIR, extended function index register */
1572 oldid=inb(io+1); /* Read EFDR, extended function data register */
1579 outb(0xaa,io); /* Magic Seal */
1581 if ((x_id == id) && (x_oldrev == oldrev) &&
1582 (x_oldid == oldid) && (x_rev == rev))
1583 return; /* protection against false positives */
1585 decode_smsc(io,key,oldid,oldrev);
1589 static void __devinit detect_and_report_winbond (void)
1591 if (verbose_probing)
1592 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1593 winbond_check(0x3f0,0x87);
1594 winbond_check(0x370,0x87);
1595 winbond_check(0x2e ,0x87);
1596 winbond_check(0x4e ,0x87);
1597 winbond_check(0x3f0,0x86);
1598 winbond_check2(0x250,0x88);
1599 winbond_check2(0x250,0x89);
1602 static void __devinit detect_and_report_smsc (void)
1604 if (verbose_probing)
1605 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1606 smsc_check(0x3f0,0x55);
1607 smsc_check(0x370,0x55);
1608 smsc_check(0x3f0,0x44);
1609 smsc_check(0x370,0x44);
1611 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1613 static int __devinit get_superio_dma (struct parport *p)
1616 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1619 return superios[i].dma;
1620 return PARPORT_DMA_NONE;
1623 static int __devinit get_superio_irq (struct parport *p)
1626 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1629 return superios[i].irq;
1630 return PARPORT_IRQ_NONE;
1634 /* --- Mode detection ------------------------------------- */
1637 * Checks for port existence, all ports support SPP MODE
1639 * 0 : No parallel port at this adress
1640 * PARPORT_MODE_PCSPP : SPP port detected
1641 * (if the user specified an ioport himself,
1642 * this shall always be the case!)
1645 static int __devinit parport_SPP_supported(struct parport *pb)
1650 * first clear an eventually pending EPP timeout
1651 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1652 * that does not even respond to SPP cycles if an EPP
1653 * timeout is pending
1655 clear_epp_timeout(pb);
1657 /* Do a simple read-write test to make sure the port exists. */
1659 outb (w, CONTROL (pb));
1661 /* Is there a control register that we can read from? Some
1662 * ports don't allow reads, so read_control just returns a
1663 * software copy. Some ports _do_ allow reads, so bypass the
1664 * software copy here. In addition, some bits aren't
1666 r = inb (CONTROL (pb));
1667 if ((r & 0xf) == w) {
1669 outb (w, CONTROL (pb));
1670 r = inb (CONTROL (pb));
1671 outb (0xc, CONTROL (pb));
1673 return PARPORT_MODE_PCSPP;
1677 /* That didn't work, but the user thinks there's a
1679 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
1680 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1682 /* Try the data register. The data lines aren't tri-stated at
1683 * this stage, so we expect back what we wrote. */
1685 parport_pc_write_data (pb, w);
1686 r = parport_pc_read_data (pb);
1689 parport_pc_write_data (pb, w);
1690 r = parport_pc_read_data (pb);
1692 return PARPORT_MODE_PCSPP;
1695 if (user_specified) {
1696 /* Didn't work, but the user is convinced this is the
1698 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
1699 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1700 printk (KERN_INFO "parport 0x%lx: You gave this address, "
1701 "but there is probably no parallel port there!\n",
1705 /* It's possible that we can't read the control register or
1706 * the data register. In that case just believe the user. */
1708 return PARPORT_MODE_PCSPP;
1715 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1716 * on these cards actually accesses the CTR.
1718 * Modern cards don't do this but reading from ECR will return 0xff
1719 * regardless of what is written here if the card does NOT support
1722 * We first check to see if ECR is the same as CTR. If not, the low
1723 * two bits of ECR aren't writable, so we check by writing ECR and
1724 * reading it back to see if it's what we expect.
1726 static int __devinit parport_ECR_present(struct parport *pb)
1728 struct parport_pc_private *priv = pb->private_data;
1729 unsigned char r = 0xc;
1731 outb (r, CONTROL (pb));
1732 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1733 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1735 r = inb (CONTROL (pb));
1736 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1737 goto no_reg; /* Sure that no ECR register exists */
1740 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1743 ECR_WRITE (pb, 0x34);
1744 if (inb (ECONTROL (pb)) != 0x35)
1748 outb (0xc, CONTROL (pb));
1750 /* Go to mode 000 */
1751 frob_set_mode (pb, ECR_SPP);
1756 outb (0xc, CONTROL (pb));
1760 #ifdef CONFIG_PARPORT_1284
1761 /* Detect PS/2 support.
1763 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1764 * allows us to read data from the data lines. In theory we would get back
1765 * 0xff but any peripheral attached to the port may drag some or all of the
1766 * lines down to zero. So if we get back anything that isn't the contents
1767 * of the data register we deem PS/2 support to be present.
1769 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1770 * drivers, but an external peripheral with sufficiently beefy drivers of
1771 * its own can overpower them and assert its own levels onto the bus, from
1772 * where they can then be read back as normal. Ports with this property
1773 * and the right type of device attached are likely to fail the SPP test,
1774 * (as they will appear to have stuck bits) and so the fact that they might
1775 * be misdetected here is rather academic.
1778 static int __devinit parport_PS2_supported(struct parport *pb)
1782 clear_epp_timeout(pb);
1784 /* try to tri-state the buffer */
1785 parport_pc_data_reverse (pb);
1787 parport_pc_write_data(pb, 0x55);
1788 if (parport_pc_read_data(pb) != 0x55) ok++;
1790 parport_pc_write_data(pb, 0xaa);
1791 if (parport_pc_read_data(pb) != 0xaa) ok++;
1793 /* cancel input mode */
1794 parport_pc_data_forward (pb);
1797 pb->modes |= PARPORT_MODE_TRISTATE;
1799 struct parport_pc_private *priv = pb->private_data;
1800 priv->ctr_writable &= ~0x20;
1806 #ifdef CONFIG_PARPORT_PC_FIFO
1807 static int __devinit parport_ECP_supported(struct parport *pb)
1810 int config, configb;
1812 struct parport_pc_private *priv = pb->private_data;
1813 /* Translate ECP intrLine to ISA irq value */
1814 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1816 /* If there is no ECR, we have no hope of supporting ECP. */
1820 /* Find out FIFO depth */
1821 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1822 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
1823 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1824 outb (0xaa, FIFO (pb));
1827 * Using LGS chipset it uses ECR register, but
1828 * it doesn't support ECP or FIFO MODE
1831 ECR_WRITE (pb, ECR_SPP << 5);
1835 priv->fifo_depth = i;
1836 if (verbose_probing)
1837 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1839 /* Find out writeIntrThreshold */
1840 frob_econtrol (pb, 1<<2, 1<<2);
1841 frob_econtrol (pb, 1<<2, 0);
1842 for (i = 1; i <= priv->fifo_depth; i++) {
1845 if (inb (ECONTROL (pb)) & (1<<2))
1849 if (i <= priv->fifo_depth) {
1850 if (verbose_probing)
1851 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1854 /* Number of bytes we know we can write if we get an
1858 priv->writeIntrThreshold = i;
1860 /* Find out readIntrThreshold */
1861 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1862 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1863 frob_set_mode (pb, ECR_TST); /* Test FIFO */
1864 frob_econtrol (pb, 1<<2, 1<<2);
1865 frob_econtrol (pb, 1<<2, 0);
1866 for (i = 1; i <= priv->fifo_depth; i++) {
1867 outb (0xaa, FIFO (pb));
1868 if (inb (ECONTROL (pb)) & (1<<2))
1872 if (i <= priv->fifo_depth) {
1873 if (verbose_probing)
1874 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1877 /* Number of bytes we can read if we get an interrupt. */
1880 priv->readIntrThreshold = i;
1882 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1883 ECR_WRITE (pb, 0xf4); /* Configuration mode */
1884 config = inb (CONFIGA (pb));
1885 pword = (config >> 4) & 0x7;
1889 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1894 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1898 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1904 priv->pword = pword;
1906 if (verbose_probing) {
1907 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1909 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1910 config & 0x80 ? "Level" : "Pulses");
1912 configb = inb (CONFIGB (pb));
1913 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1914 pb->base, config, configb);
1915 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1916 if ((configb >>3) & 0x07)
1917 printk("%d",intrline[(configb >>3) & 0x07]);
1919 printk("<none or set by other means>");
1921 if( (configb & 0x03 ) == 0x00)
1922 printk("<none or set by other means>\n");
1924 printk("%d\n",configb & 0x07);
1927 /* Go back to mode 000 */
1928 frob_set_mode (pb, ECR_SPP);
1934 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1936 const struct parport_pc_private *priv = pb->private_data;
1943 oecr = inb (ECONTROL (pb));
1944 ECR_WRITE (pb, ECR_PS2 << 5);
1945 result = parport_PS2_supported(pb);
1946 ECR_WRITE (pb, oecr);
1950 /* EPP mode detection */
1952 static int __devinit parport_EPP_supported(struct parport *pb)
1954 const struct parport_pc_private *priv = pb->private_data;
1958 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1959 * when EPP is possible and is set high when an EPP timeout
1960 * occurs (EPP uses the HALT line to stop the CPU while it does
1961 * the byte transfer, an EPP timeout occurs if the attached
1962 * device fails to respond after 10 micro seconds).
1964 * This bit is cleared by either reading it (National Semi)
1965 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1966 * This bit is always high in non EPP modes.
1969 /* If EPP timeout bit clear then EPP available */
1970 if (!clear_epp_timeout(pb)) {
1971 return 0; /* No way to clear timeout */
1974 /* Check for Intel bug. */
1977 for (i = 0x00; i < 0x80; i += 0x20) {
1979 if (clear_epp_timeout (pb)) {
1980 /* Phony EPP in ECP. */
1986 pb->modes |= PARPORT_MODE_EPP;
1988 /* Set up access functions to use EPP hardware. */
1989 pb->ops->epp_read_data = parport_pc_epp_read_data;
1990 pb->ops->epp_write_data = parport_pc_epp_write_data;
1991 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1992 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1997 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1999 struct parport_pc_private *priv = pb->private_data;
2007 oecr = inb (ECONTROL (pb));
2008 /* Search for SMC style EPP+ECP mode */
2009 ECR_WRITE (pb, 0x80);
2010 outb (0x04, CONTROL (pb));
2011 result = parport_EPP_supported(pb);
2013 ECR_WRITE (pb, oecr);
2016 /* Set up access functions to use ECP+EPP hardware. */
2017 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
2018 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
2019 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
2020 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
2026 #else /* No IEEE 1284 support */
2028 /* Don't bother probing for modes we know we won't use. */
2029 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
2030 #ifdef CONFIG_PARPORT_PC_FIFO
2031 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
2033 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
2034 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
2035 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
2037 #endif /* No IEEE 1284 support */
2039 /* --- IRQ detection -------------------------------------- */
2041 /* Only if supports ECP mode */
2042 static int __devinit programmable_irq_support(struct parport *pb)
2045 unsigned char oecr = inb (ECONTROL (pb));
2046 static const int lookup[8] = {
2047 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
2050 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
2052 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
2053 irq = lookup[intrLine];
2055 ECR_WRITE (pb, oecr);
2059 static int __devinit irq_probe_ECP(struct parport *pb)
2065 irqs = probe_irq_on();
2067 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
2068 ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
2069 ECR_WRITE (pb, ECR_TST << 5);
2071 /* If Full FIFO sure that writeIntrThreshold is generated */
2072 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
2073 outb (0xaa, FIFO (pb));
2075 pb->irq = probe_irq_off(irqs);
2076 ECR_WRITE (pb, ECR_SPP << 5);
2079 pb->irq = PARPORT_IRQ_NONE;
2085 * This detection seems that only works in National Semiconductors
2086 * This doesn't work in SMC, LGS, and Winbond
2088 static int __devinit irq_probe_EPP(struct parport *pb)
2090 #ifndef ADVANCED_DETECT
2091 return PARPORT_IRQ_NONE;
2096 if (pb->modes & PARPORT_MODE_PCECR)
2097 oecr = inb (ECONTROL (pb));
2100 irqs = probe_irq_on();
2102 if (pb->modes & PARPORT_MODE_PCECR)
2103 frob_econtrol (pb, 0x10, 0x10);
2105 clear_epp_timeout(pb);
2106 parport_pc_frob_control (pb, 0x20, 0x20);
2107 parport_pc_frob_control (pb, 0x10, 0x10);
2108 clear_epp_timeout(pb);
2110 /* Device isn't expecting an EPP read
2111 * and generates an IRQ.
2113 parport_pc_read_epp(pb);
2116 pb->irq = probe_irq_off (irqs);
2117 if (pb->modes & PARPORT_MODE_PCECR)
2118 ECR_WRITE (pb, oecr);
2119 parport_pc_write_control(pb, 0xc);
2122 pb->irq = PARPORT_IRQ_NONE;
2125 #endif /* Advanced detection */
2128 static int __devinit irq_probe_SPP(struct parport *pb)
2130 /* Don't even try to do this. */
2131 return PARPORT_IRQ_NONE;
2134 /* We will attempt to share interrupt requests since other devices
2135 * such as sound cards and network cards seem to like using the
2138 * When ECP is available we can autoprobe for IRQs.
2139 * NOTE: If we can autoprobe it, we can register the IRQ.
2141 static int __devinit parport_irq_probe(struct parport *pb)
2143 struct parport_pc_private *priv = pb->private_data;
2146 pb->irq = programmable_irq_support(pb);
2148 if (pb->irq == PARPORT_IRQ_NONE)
2149 pb->irq = irq_probe_ECP(pb);
2152 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2153 (pb->modes & PARPORT_MODE_EPP))
2154 pb->irq = irq_probe_EPP(pb);
2156 clear_epp_timeout(pb);
2158 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2159 pb->irq = irq_probe_EPP(pb);
2161 clear_epp_timeout(pb);
2163 if (pb->irq == PARPORT_IRQ_NONE)
2164 pb->irq = irq_probe_SPP(pb);
2166 if (pb->irq == PARPORT_IRQ_NONE)
2167 pb->irq = get_superio_irq(pb);
2172 /* --- DMA detection -------------------------------------- */
2174 /* Only if chipset conforms to ECP ISA Interface Standard */
2175 static int __devinit programmable_dma_support (struct parport *p)
2177 unsigned char oecr = inb (ECONTROL (p));
2180 frob_set_mode (p, ECR_CNF);
2182 dma = inb (CONFIGB(p)) & 0x07;
2183 /* 000: Indicates jumpered 8-bit DMA if read-only.
2184 100: Indicates jumpered 16-bit DMA if read-only. */
2185 if ((dma & 0x03) == 0)
2186 dma = PARPORT_DMA_NONE;
2188 ECR_WRITE (p, oecr);
2192 static int __devinit parport_dma_probe (struct parport *p)
2194 const struct parport_pc_private *priv = p->private_data;
2196 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2197 if (p->dma == PARPORT_DMA_NONE) {
2198 /* ask known Super-IO chips proper, although these
2199 claim ECP compatible, some don't report their DMA
2200 conforming to ECP standards */
2201 p->dma = get_superio_dma(p);
2207 /* --- Initialisation code -------------------------------- */
2209 struct parport *parport_pc_probe_port (unsigned long int base,
2210 unsigned long int base_hi,
2212 struct pci_dev *dev)
2214 struct parport_pc_private *priv;
2215 struct parport_operations *ops;
2217 struct parport *p = &tmp;
2218 int probedirq = PARPORT_IRQ_NONE;
2219 if (check_region(base, 3)) return NULL;
2220 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2222 printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
2225 ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
2227 printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
2232 memcpy (ops, &parport_pc_ops, sizeof (struct parport_operations));
2234 priv->ctr_writable = ~0x10;
2236 priv->fifo_depth = 0;
2238 priv->dma_handle = 0;
2241 p->base_hi = base_hi;
2244 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2246 p->private_data = priv;
2249 if (base_hi && !check_region(base_hi,3))
2250 parport_ECR_present(p);
2252 if (base != 0x3bc) {
2253 if (!check_region(base+0x3, 5)) {
2254 if (!parport_EPP_supported(p))
2255 parport_ECPEPP_supported(p);
2258 if (!parport_SPP_supported (p)) {
2265 parport_ECPPS2_supported(p);
2267 parport_PS2_supported (p);
2269 if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
2270 PARPORT_DMA_NONE, ops))) {
2276 p->base_hi = base_hi;
2277 p->modes = tmp.modes;
2278 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2279 p->private_data = priv;
2281 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2282 if (p->base_hi && priv->ecr)
2283 printk(" (0x%lx)", p->base_hi);
2286 if (p->irq == PARPORT_IRQ_AUTO) {
2287 p->irq = PARPORT_IRQ_NONE;
2288 parport_irq_probe(p);
2289 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2290 p->irq = PARPORT_IRQ_NONE;
2291 parport_irq_probe(p);
2293 p->irq = PARPORT_IRQ_NONE;
2295 if (p->irq != PARPORT_IRQ_NONE) {
2296 printk(", irq %d", p->irq);
2297 priv->ctr_writable |= 0x10;
2299 if (p->dma == PARPORT_DMA_AUTO) {
2300 p->dma = PARPORT_DMA_NONE;
2301 parport_dma_probe(p);
2304 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2305 is mandatory (see above) */
2306 p->dma = PARPORT_DMA_NONE;
2308 #ifdef CONFIG_PARPORT_PC_FIFO
2309 if (parport_ECP_supported(p) &&
2310 p->dma != PARPORT_DMA_NOFIFO &&
2311 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2312 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2313 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2314 #ifdef CONFIG_PARPORT_1284
2315 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2316 /* currently broken, but working on it.. (FB) */
2317 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2318 #endif /* IEEE 1284 support */
2319 if (p->dma != PARPORT_DMA_NONE) {
2320 printk(", dma %d", p->dma);
2321 p->modes |= PARPORT_MODE_DMA;
2323 else printk(", using FIFO");
2326 /* We can't use the DMA channel after all. */
2327 p->dma = PARPORT_DMA_NONE;
2328 #endif /* Allowed to use FIFO/DMA */
2331 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2335 printmode(TRISTATE);
2342 #ifndef CONFIG_PARPORT_1284
2344 #endif /* CONFIG_PARPORT_1284 */
2346 if (probedirq != PARPORT_IRQ_NONE)
2347 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2348 parport_proc_register(p);
2350 request_region (p->base, 3, p->name);
2352 request_region (p->base + 3, p->size - 3, p->name);
2353 if (p->modes & PARPORT_MODE_ECP)
2354 request_region (p->base_hi, 3, p->name);
2356 if (p->irq != PARPORT_IRQ_NONE) {
2357 if (request_irq (p->irq, parport_pc_interrupt,
2359 printk (KERN_WARNING "%s: irq %d in use, "
2360 "resorting to polled operation\n",
2362 p->irq = PARPORT_IRQ_NONE;
2363 p->dma = PARPORT_DMA_NONE;
2366 #ifdef CONFIG_PARPORT_PC_FIFO
2367 if (p->dma != PARPORT_DMA_NONE) {
2368 if (request_dma (p->dma, p->name)) {
2369 printk (KERN_WARNING "%s: dma %d in use, "
2370 "resorting to PIO operation\n",
2372 p->dma = PARPORT_DMA_NONE;
2375 pci_alloc_consistent(priv->dev,
2378 if (! priv->dma_buf) {
2379 printk (KERN_WARNING "%s: "
2380 "cannot get buffer for DMA, "
2381 "resorting to PIO operation\n",
2384 p->dma = PARPORT_DMA_NONE;
2388 #endif /* CONFIG_PARPORT_PC_FIFO */
2391 /* Done probing. Now put the port into a sensible start-up state. */
2394 * Put the ECP detected port in PS2 mode.
2395 * Do this also for ports that have ECR but don't do ECP.
2397 ECR_WRITE (p, 0x34);
2399 parport_pc_write_data(p, 0);
2400 parport_pc_data_forward (p);
2402 /* Now that we've told the sharing engine about the port, and
2403 found out its characteristics, let the high-level drivers
2405 parport_announce_port (p);
2410 void parport_pc_unregister_port (struct parport *p)
2412 #ifdef CONFIG_PARPORT_PC_FIFO
2413 struct parport_pc_private *priv = p->private_data;
2414 #endif /* CONFIG_PARPORT_PC_FIFO */
2415 struct parport_operations *ops = p->ops;
2416 if (p->dma != PARPORT_DMA_NONE)
2418 if (p->irq != PARPORT_IRQ_NONE)
2419 free_irq(p->irq, p);
2420 release_region(p->base, 3);
2422 release_region(p->base + 3, p->size - 3);
2423 if (p->modes & PARPORT_MODE_ECP)
2424 release_region(p->base_hi, 3);
2425 parport_proc_unregister(p);
2426 #ifdef CONFIG_PARPORT_PC_FIFO
2428 pci_free_consistent(priv->dev, PAGE_SIZE,
2431 #endif /* CONFIG_PARPORT_PC_FIFO */
2432 kfree (p->private_data);
2433 parport_unregister_port(p);
2434 kfree (ops); /* hope no-one cached it */
2439 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2440 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
2443 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2445 u32 ite8872_lpt, ite8872_lpthi;
2446 u8 ite8872_irq, type;
2450 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
2452 // make sure which one chip
2453 for(i = 0; i < 5; i++) {
2454 if (check_region (inta_addr[i], 0x8) >= 0) {
2456 pci_write_config_dword (pdev, 0x60,
2457 0xe7000000 | inta_addr[i]);
2458 pci_write_config_dword (pdev, 0x78,
2459 0x00000000 | inta_addr[i]);
2460 test = inb (inta_addr[i]);
2461 if (test != 0xff) break;
2465 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2469 type = inb (inta_addr[i] + 0x18);
2474 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2475 ite8872set = 0x64200000;
2478 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2479 ite8872set = 0x64200000;
2482 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2483 ite8872set = 0x64e00000;
2486 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2489 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2492 printk (KERN_INFO "parport_pc: unknown ITE887x\n");
2493 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2494 "output to Rich.Liu@ite.com.tw\n");
2498 pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
2499 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
2500 ite8872_lpt &= 0x0000ff00;
2501 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
2502 ite8872_lpthi &= 0x0000ff00;
2503 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2504 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2505 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2506 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2508 pci_write_config_dword (pdev, 0x9c,
2509 ite8872set | (ite8872_irq * 0x11111));
2511 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2512 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2514 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2517 /* Let the user (or defaults) steer us away from interrupts */
2519 if (autoirq != PARPORT_IRQ_AUTO)
2520 irq = PARPORT_IRQ_NONE;
2522 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
2523 irq, PARPORT_DMA_NONE, NULL)) {
2525 "parport_pc: ITE 8872 parallel port: io=0x%X",
2527 if (irq != PARPORT_IRQ_NONE)
2528 printk (", irq=%d", irq);
2536 /* Via support maintained by Jeff Garzik <jgarzik@pobox.com> */
2537 static int __devinit sio_via_686a_probe (struct pci_dev *pdev, int autoirq,
2542 unsigned port1, port2, have_eppecp;
2545 * unlock super i/o configuration, set 0x85_1
2547 pci_read_config_byte (pdev, 0x85, &tmp);
2549 pci_write_config_byte (pdev, 0x85, tmp);
2552 * Super I/O configuration, index port == 3f0h, data port == 3f1h
2555 /* 0xE2_1-0: Parallel Port Mode / Enable */
2559 if ((tmp & 0x03) == 0x03) {
2560 printk (KERN_INFO "parport_pc: Via 686A parallel port disabled in BIOS\n");
2564 /* 0xE6: Parallel Port I/O Base Address, bits 9-2 */
2566 port1 = inb (0x3F1) << 2;
2569 case 0x3bc: port2 = 0x7bc; break;
2570 case 0x378: port2 = 0x778; break;
2571 case 0x278: port2 = 0x678; break;
2573 printk (KERN_INFO "parport_pc: Weird Via 686A parport base 0x%X, ignoring\n",
2578 /* 0xF0_5: EPP+ECP enable */
2580 have_eppecp = (inb (0x3F1) & (1 << 5));
2583 * lock super i/o configuration, clear 0x85_1
2585 pci_read_config_byte (pdev, 0x85, &tmp);
2587 pci_write_config_byte (pdev, 0x85, tmp);
2590 * Get DMA and IRQ from PCI->ISA bridge PCI config registers
2593 /* 0x50_3-2: PnP Routing for Parallel Port DRQ */
2594 pci_read_config_byte (pdev, 0x50, &tmp);
2595 dma = ((tmp >> 2) & 0x03);
2597 /* 0x51_7-4: PnP Routing for Parallel Port IRQ */
2598 pci_read_config_byte (pdev, 0x51, &tmp);
2599 irq = ((tmp >> 4) & 0x0F);
2601 /* filter bogus IRQs */
2607 irq = PARPORT_IRQ_NONE;
2610 default: /* do nothing */
2614 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2616 dma = PARPORT_DMA_NONE;
2618 /* Let the user (or defaults) steer us away from interrupts and DMA */
2619 if (autoirq != PARPORT_IRQ_AUTO) {
2620 irq = PARPORT_IRQ_NONE;
2621 dma = PARPORT_DMA_NONE;
2623 if (autodma != PARPORT_DMA_AUTO)
2624 dma = PARPORT_DMA_NONE;
2626 /* finally, do the probe with values obtained */
2627 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
2629 "parport_pc: Via 686A parallel port: io=0x%X", port1);
2630 if (irq != PARPORT_IRQ_NONE)
2631 printk (", irq=%d", irq);
2632 if (dma != PARPORT_DMA_NONE)
2633 printk (", dma=%d", dma);
2638 printk (KERN_WARNING "parport_pc: Strange, can't probe Via 686A parallel port: io=0x%X, irq=%d, dma=%d\n",
2644 enum parport_pc_sio_types {
2645 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2650 /* each element directly indexed from enum list, above */
2651 static struct parport_pc_superio {
2652 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma);
2653 } parport_pc_superio_info[] __devinitdata = {
2654 { sio_via_686a_probe, },
2655 { sio_ite_8872_probe, },
2659 enum parport_pc_pci_cards {
2660 siig_1p_10x = last_sio,
2665 lava_parallel_dual_a,
2666 lava_parallel_dual_b,
2705 /* each element directly indexed from enum list, above
2706 * (but offset by last_sio) */
2707 static struct parport_pc_pci {
2709 struct { /* BAR (base address registers) numbers in the config
2712 int hi; /* -1 if not there, >6 for offset-method (max
2716 /* If set, this is called immediately after pci_enable_device.
2717 * If it returns non-zero, no probing will take place and the
2718 * ports will not be used. */
2719 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2721 /* If set, this is called after probing for ports. If 'failed'
2722 * is non-zero we couldn't use any of the ports. */
2723 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2724 } cards[] __devinitdata = {
2725 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2726 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2727 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2728 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2729 /* lava_parallel */ { 1, { { 0, -1 }, } },
2730 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2731 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2732 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2733 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2734 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2735 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2736 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2737 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2738 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2739 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2740 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2741 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2742 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2743 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2744 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2745 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2746 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2747 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2748 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2749 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2750 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2751 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2752 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2753 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2754 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2755 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2756 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2757 /* SYBA uses fixed offsets in
2759 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2760 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2761 /* titan_010l */ { 1, { { 3, -1 }, } },
2762 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2763 /* avlab_1p */ { 1, { { 0, 1}, } },
2764 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2765 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2766 * and 840 locks up if you write 1 to bit 2! */
2767 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2768 /* oxsemi_840 */ { 1, { { 0, -1 }, } },
2769 /* aks_0100 */ { 1, { { 0, -1 }, } },
2770 /* mobility_pp */ { 1, { { 0, 1 }, } },
2773 static struct pci_device_id parport_pc_pci_tbl[] __devinitdata = {
2774 /* Super-IO onboard chips */
2775 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2776 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2780 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2782 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2784 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2786 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2788 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2790 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2792 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2794 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2796 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2797 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2798 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2799 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2800 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2801 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2802 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2803 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2804 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2805 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2806 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2807 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2808 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2809 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2810 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2811 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2812 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2813 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2814 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2815 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2816 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2817 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2818 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2819 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2820 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2821 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2822 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2823 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2824 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2825 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2826 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2827 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2828 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2829 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2830 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2831 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
2832 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2833 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2834 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2835 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2836 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2837 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2838 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2839 { 0, } /* terminate list */
2841 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2843 static int __devinit parport_pc_pci_probe (struct pci_dev *dev,
2844 const struct pci_device_id *id)
2846 int err, count, n, i = id->driver_data;
2848 /* This is an onboard Super-IO and has already been probed */
2851 /* This is a PCI card */
2854 if ((err = pci_enable_device (dev)) != 0)
2857 if (cards[i].preinit_hook &&
2858 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
2861 for (n = 0; n < cards[i].numports; n++) {
2862 int lo = cards[i].addr[n].lo;
2863 int hi = cards[i].addr[n].hi;
2864 unsigned long io_lo, io_hi;
2865 io_lo = pci_resource_start (dev, lo);
2867 if ((hi >= 0) && (hi <= 6))
2868 io_hi = pci_resource_start (dev, hi);
2870 io_lo += hi; /* Reinterpret the meaning of
2871 "hi" as an offset (see SYBA
2873 /* TODO: test if sharing interrupts works */
2874 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
2875 "I/O at %#lx(%#lx)\n",
2876 parport_pc_pci_tbl[i + last_sio].vendor,
2877 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
2878 if (parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
2879 PARPORT_DMA_NONE, dev))
2883 if (cards[i].postinit_hook)
2884 cards[i].postinit_hook (dev, count == 0);
2886 return count == 0 ? -ENODEV : 0;
2889 static struct pci_driver parport_pc_pci_driver = {
2891 id_table: parport_pc_pci_tbl,
2892 probe: parport_pc_pci_probe,
2895 static int __init parport_pc_init_superio (int autoirq, int autodma)
2897 const struct pci_device_id *id;
2898 struct pci_dev *pdev;
2901 pci_for_each_dev(pdev) {
2902 id = pci_match_device (parport_pc_pci_tbl, pdev);
2903 if (id == NULL || id->driver_data >= last_sio)
2906 if (parport_pc_superio_info[id->driver_data].probe
2907 (pdev, autoirq, autodma)) {
2912 return ret; /* number of devices found */
2915 static struct pci_driver parport_pc_pci_driver;
2916 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
2917 #endif /* CONFIG_PCI */
2919 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
2920 static int __init __attribute__((unused))
2921 parport_pc_find_isa_ports (int autoirq, int autodma)
2925 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
2927 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
2929 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
2935 /* This function is called by parport_pc_init if the user didn't
2936 * specify any ports to probe. Its job is to find some ports. Order
2937 * is important here -- we want ISA ports to be registered first,
2938 * followed by PCI cards (for least surprise), but before that we want
2939 * to do chipset-specific tests for some onboard ports that we know
2942 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
2943 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
2945 static int __init parport_pc_find_ports (int autoirq, int autodma)
2949 #ifdef CONFIG_PARPORT_PC_SUPERIO
2950 detect_and_report_winbond ();
2951 detect_and_report_smsc ();
2954 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
2955 count += parport_pc_init_superio (autoirq, autodma);
2957 /* ISA ports and whatever (see asm/parport.h). */
2958 count += parport_pc_find_nonpci_ports (autoirq, autodma);
2960 r = pci_register_driver (&parport_pc_pci_driver);
2962 registered_parport = 1;
2969 int __init parport_pc_init (int *io, int *io_hi, int *irq, int *dma)
2971 int count = 0, i = 0;
2974 /* Only probe the ports we were given. */
2977 if ((*io_hi) == PARPORT_IOHI_AUTO)
2978 *io_hi = 0x400 + *io;
2979 if (parport_pc_probe_port(*(io++), *(io_hi++),
2980 *(irq++), *(dma++), NULL))
2982 } while (*io && (++i < PARPORT_PC_MAX_PORTS));
2984 count += parport_pc_find_ports (irq[0], dma[0]);
2990 /* Exported symbols. */
2991 EXPORT_SYMBOL (parport_pc_probe_port);
2992 EXPORT_SYMBOL (parport_pc_unregister_port);
2995 static int io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
2996 static int io_hi[PARPORT_PC_MAX_PORTS+1] =
2997 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
2998 static int dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
2999 static int irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
3000 static const char *irq[PARPORT_PC_MAX_PORTS] = { NULL, };
3001 static const char *dma[PARPORT_PC_MAX_PORTS] = { NULL, };
3003 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3004 MODULE_DESCRIPTION("PC-style parallel port driver");
3005 MODULE_LICENSE("GPL");
3007 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3008 MODULE_PARM(io, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
3009 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3010 MODULE_PARM(io_hi, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
3011 MODULE_PARM_DESC(irq, "IRQ line");
3012 MODULE_PARM(irq, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
3013 MODULE_PARM_DESC(dma, "DMA channel");
3014 MODULE_PARM(dma, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
3015 #if defined(CONFIG_PARPORT_PC_FIFO) || defined(CONFIG_PARPORT_PC_SUPERIO)
3016 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3017 MODULE_PARM(verbose_probing, "i");
3020 int init_module(void)
3022 /* Work out how many ports we have, then get parport_share to parse
3026 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++);
3028 if (parport_parse_irqs(i, irq, irqval)) return 1;
3029 if (parport_parse_dmas(i, dma, dmaval)) return 1;
3032 /* The user can make us use any IRQs or DMAs we find. */
3035 if (irq[0] && !parport_parse_irqs (1, irq, &val))
3037 case PARPORT_IRQ_NONE:
3038 case PARPORT_IRQ_AUTO:
3042 printk (KERN_WARNING
3043 "parport_pc: irq specified "
3044 "without base address. Use 'io=' "
3045 "to specify one\n");
3048 if (dma[0] && !parport_parse_dmas (1, dma, &val))
3050 case PARPORT_DMA_NONE:
3051 case PARPORT_DMA_AUTO:
3055 printk (KERN_WARNING
3056 "parport_pc: dma specified "
3057 "without base address. Use 'io=' "
3058 "to specify one\n");
3062 ret = !parport_pc_init (io, io_hi, irqval, dmaval);
3063 if (ret && registered_parport)
3064 pci_unregister_driver (&parport_pc_pci_driver);
3069 void cleanup_module(void)
3071 /* We ought to keep track of which ports are actually ours. */
3072 struct parport *p = parport_enumerate(), *tmp;
3074 if (!user_specified)
3075 pci_unregister_driver (&parport_pc_pci_driver);
3079 if (p->modes & PARPORT_MODE_PCSPP)
3080 parport_pc_unregister_port (p);