2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/cache.h>
26 #include <linux/slab.h>
29 #define DEBUG_CONFIG 1
31 # define DBGC(args) printk args
36 #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
39 pbus_assign_resources_sorted(struct pci_bus *bus)
43 struct resource_list head, *list, *tmp;
44 int idx, found_vga = 0;
47 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
48 struct pci_dev *dev = pci_dev_b(ln);
49 u16 class = dev->class >> 8;
52 /* First, disable the device to avoid side
53 effects of possibly overlapping I/O and
55 Leave VGA enabled - for obvious reason. :-)
56 Same with all sorts of bridges - they may
57 have VGA behind them. */
58 if (class == PCI_CLASS_DISPLAY_VGA
59 || class == PCI_CLASS_NOT_DEFINED_VGA)
61 else if (class >> 8 != PCI_BASE_CLASS_BRIDGE) {
62 pci_read_config_word(dev, PCI_COMMAND, &cmd);
63 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY
64 | PCI_COMMAND_MASTER);
65 pci_write_config_word(dev, PCI_COMMAND, cmd);
68 pdev_sort_resources(dev, &head);
71 for (list = head.next; list;) {
73 idx = res - &list->dev->resource[0];
74 pci_assign_resource(list->dev, idx);
83 /* Initialize bridges with base/limit values we have collected.
84 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
85 requires that if there is no I/O ports or memory behind the
86 bridge, corresponding range must be turned off by writing base
87 value greater than limit to the bridge's base/limit registers. */
89 pci_setup_bridge(struct pci_bus *bus)
91 struct pbus_set_ranges_data ranges;
92 struct pci_dev *bridge = bus->self;
95 if (!bridge || (bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
98 ranges.io_start = bus->resource[0]->start;
99 ranges.io_end = bus->resource[0]->end;
100 ranges.mem_start = bus->resource[1]->start;
101 ranges.mem_end = bus->resource[1]->end;
102 ranges.prefetch_start = bus->resource[2]->start;
103 ranges.prefetch_end = bus->resource[2]->end;
104 pcibios_fixup_pbus_ranges(bus, &ranges);
106 DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n",
107 bus->number, bridge->name));
109 /* Set up the top and bottom of the PCI I/O segment for this bus. */
110 if (bus->resource[0]->flags & IORESOURCE_IO) {
111 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
113 l |= (ranges.io_start >> 8) & 0x00f0;
114 l |= ranges.io_end & 0xf000;
115 /* Set up upper 16 bits of I/O base/limit. */
116 pci_write_config_word(bridge, PCI_IO_BASE_UPPER16,
117 ranges.io_start >> 16);
118 pci_write_config_word(bridge, PCI_IO_LIMIT_UPPER16,
119 ranges.io_end >> 16);
120 DBGC((KERN_INFO " IO window: %04lx-%04lx\n",
121 ranges.io_start, ranges.io_end));
124 /* Clear upper 16 bits of I/O base/limit. */
125 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0);
127 DBGC((KERN_INFO " IO window: disabled.\n"));
129 pci_write_config_dword(bridge, PCI_IO_BASE, l);
131 /* Set up the top and bottom of the PCI Memory segment
133 if (bus->resource[1]->flags & IORESOURCE_MEM) {
134 l = (ranges.mem_start >> 16) & 0xfff0;
135 l |= ranges.mem_end & 0xfff00000;
136 DBGC((KERN_INFO " MEM window: %08lx-%08lx\n",
137 ranges.mem_start, ranges.mem_end));
141 DBGC((KERN_INFO " MEM window: disabled.\n"));
143 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
145 /* Clear out the upper 32 bits of PREF base/limit. */
146 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
147 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
149 /* Set up PREF base/limit. */
150 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
151 l = (ranges.prefetch_start >> 16) & 0xfff0;
152 l |= ranges.prefetch_end & 0xfff00000;
153 DBGC((KERN_INFO " PREFETCH window: %08lx-%08lx\n",
154 ranges.prefetch_start, ranges.prefetch_end));
158 DBGC((KERN_INFO " PREFETCH window: disabled.\n"));
160 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
162 /* Check if we have VGA behind the bridge.
163 Enable ISA in either case (FIXME!). */
164 l = (bus->resource[0]->flags & IORESOURCE_BUS_HAS_VGA) ? 0x0c : 0x04;
165 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, l);
168 /* Check whether the bridge supports optional I/O and
169 prefetchable memory ranges. If not, the respective
170 base/limit registers must be read-only and read as 0. */
172 pci_bridge_check_ranges(struct pci_bus *bus)
176 struct pci_dev *bridge = bus->self;
177 struct resource *b_res;
179 if (!bridge || (bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
182 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
183 b_res[1].flags |= IORESOURCE_MEM;
185 pci_read_config_word(bridge, PCI_IO_BASE, &io);
187 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
188 pci_read_config_word(bridge, PCI_IO_BASE, &io);
189 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
192 b_res[0].flags |= IORESOURCE_IO;
193 /* DECchip 21050 pass 2 errata: the bridge may miss an address
194 disconnect boundary by one PCI data phase.
195 Workaround: do not use prefetching on this device. */
196 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
198 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
200 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
202 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
203 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
206 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
209 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
210 since these windows have 4K granularity and the IO ranges
211 of non-bridge PCI devices are limited to 256 bytes.
212 We must be careful with the ISA aliasing though. */
214 pbus_size_io(struct pci_bus *bus)
216 struct list_head *ln;
217 struct resource *b_res = bus->resource[0];
218 unsigned long size = 0, size1 = 0;
220 if (!(b_res->flags & IORESOURCE_IO))
223 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
224 struct pci_dev *dev = pci_dev_b(ln);
227 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
228 struct resource *r = &dev->resource[i];
229 unsigned long r_size;
231 if (r->parent || !(r->flags & IORESOURCE_IO))
233 r_size = r->end - r->start + 1;
236 /* Might be re-aligned for ISA */
241 /* ??? Reserve some resources for CardBus. */
242 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_CARDBUS)
245 /* To be fixed in 2.5: we should have sort of HAVE_ISA
246 flag in the struct pci_bus. */
247 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
248 size = (size & 0xff) + ((size & ~0xffUL) << 2);
250 size = ROUND_UP(size + size1, 4096);
255 /* Alignment of the IO window is always 4K */
257 b_res->end = b_res->start + size - 1;
260 /* Calculate the size of the bus and minimal alignment which
261 guarantees that all child resources fit in this size. */
263 pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
265 struct list_head *ln;
266 unsigned long min_align, align, size;
267 unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */
268 int order, max_order;
269 struct resource *b_res = (type & IORESOURCE_PREFETCH) ?
270 bus->resource[2] : bus->resource[1];
272 memset(aligns, 0, sizeof(aligns));
276 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
277 struct pci_dev *dev = pci_dev_b(ln);
280 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
281 struct resource *r = &dev->resource[i];
282 unsigned long r_size;
284 if (r->parent || (r->flags & mask) != type)
286 r_size = r->end - r->start + 1;
287 /* For bridges size != alignment */
288 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
289 order = ffz(~align) - 20;
291 printk(KERN_WARNING "PCI: region %s/%d "
292 "too large: %lx-%lx\n",
293 dev->slot_name, i, r->start, r->end);
300 /* Exclude ranges with size > align from
301 calculation of the alignment. */
303 aligns[order] += align;
304 if (order > max_order)
307 /* ??? Reserve some resources for CardBus. */
308 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_CARDBUS) {
309 size += 1UL << 24; /* 16 Mb */
310 aligns[24 - 20] += 1UL << 24;
316 for (order = 0; order <= max_order; order++) {
317 unsigned long align1 = 1UL << (order + 20);
321 else if (ROUND_UP(align + min_align, min_align) < align1)
322 min_align = align1 >> 1;
323 align += aligns[order];
325 size = ROUND_UP(size, min_align);
330 b_res->start = min_align;
331 b_res->end = size + min_align - 1;
335 pbus_size_bridges(struct pci_bus *bus)
337 struct list_head *ln;
338 unsigned long mask, type;
340 for (ln=bus->children.next; ln != &bus->children; ln=ln->next)
341 pbus_size_bridges(pci_bus_b(ln));
347 pci_bridge_check_ranges(bus);
351 mask = type = IORESOURCE_MEM;
352 /* If the bridge supports prefetchable range, size it separately. */
353 if (bus->resource[2] &&
354 bus->resource[2]->flags & IORESOURCE_PREFETCH) {
355 pbus_size_mem(bus, IORESOURCE_PREFETCH, IORESOURCE_PREFETCH);
356 mask |= IORESOURCE_PREFETCH; /* Size non-prefetch only. */
358 pbus_size_mem(bus, mask, type);
362 pbus_assign_resources(struct pci_bus *bus)
364 struct list_head *ln;
365 int found_vga = pbus_assign_resources_sorted(bus);
370 /* Propagate presence of the VGA to upstream bridges */
371 for (b = bus; b->parent; b = b->parent) {
372 b->resource[0]->flags |= IORESOURCE_BUS_HAS_VGA;
375 for (ln=bus->children.next; ln != &bus->children; ln=ln->next) {
376 struct pci_bus *b = pci_bus_b(ln);
378 pbus_assign_resources(b);
384 pci_assign_unassigned_resources(void)
386 struct list_head *ln;
389 /* Depth first, calculate sizes and alignments of all
390 subordinate buses. */
391 for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next)
392 pbus_size_bridges(pci_bus_b(ln));
393 /* Depth last, allocate resources and update the hardware. */
394 for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next)
395 pbus_assign_resources(pci_bus_b(ln));
397 pci_for_each_dev(dev) {
398 pdev_enable_device(dev);