1 /* $Id: cs4215.h,v 1.1.1.1 2005/04/11 02:50:34 jack Exp $
2 * drivers/sbus/audio/cs4215.h
4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
12 __u8 data[4]; /* Data mode: Time slots 5-8 */
13 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
15 __u8 offset; /* Bit offset from frame sync to time slot 1 */
16 volatile __u32 status;
17 volatile __u32 version;
25 /* Time Slot 1, Status register */
26 #define CS4215_CLB (1<<2) /* Control Latch Bit */
27 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
28 /* 0: line: 2.8V, speaker 8V */
29 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
30 #define CS4215_RSRVD_1 (1<<5)
33 /* Time Slot 2, Data Format Register */
34 #define CS4215_DFR_LINEAR16 0
35 #define CS4215_DFR_ULAW 1
36 #define CS4215_DFR_ALAW 2
37 #define CS4215_DFR_LINEAR8 3
38 #define CS4215_DFR_STEREO (1<<2)
44 { 8000, (1<<4), (0<<3) },
45 { 16000, (1<<4), (1<<3) },
46 { 27429, (1<<4), (2<<3) }, /* Actually 24428.57 */
47 { 32000, (1<<4), (3<<3) },
48 /* { NA, (1<<4), (4<<3) }, */
49 /* { NA, (1<<4), (5<<3) }, */
50 { 48000, (1<<4), (6<<3) },
51 { 9600, (1<<4), (7<<3) },
52 { 5513, (2<<4), (0<<3) }, /* Actually 5512.5 */
53 { 11025, (2<<4), (1<<3) },
54 { 18900, (2<<4), (2<<3) },
55 { 22050, (2<<4), (3<<3) },
56 { 37800, (2<<4), (4<<3) },
57 { 44100, (2<<4), (5<<3) },
58 { 33075, (2<<4), (6<<3) },
59 { 6615, (2<<4), (7<<3) },
62 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
64 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
66 /* Time Slot 3, Serial Port Control register */
67 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
68 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
69 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
70 #define CS4215_BSEL_128 (1<<2)
71 #define CS4215_BSEL_256 (2<<2)
72 #define CS4215_MCK_MAST (0<<4) /* Master clock */
73 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
74 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
75 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
76 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
78 /* Time Slot 4, Test Register */
79 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
80 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
82 /* Time Slot 5, Parallel Port Register */
83 /* Read only here and the same as the in data mode */
85 /* Time Slot 6, Reserved */
87 /* Time Slot 7, Version Register */
88 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
90 /* Time Slot 8, Reserved */
97 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
99 /* Time Slot 5, Output Setting */
100 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
101 #define CS4215_LE (1<<6) /* Line Out Enable */
102 #define CS4215_HE (1<<7) /* Headphone Enable */
104 /* Time Slot 6, Output Setting */
105 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
106 #define CS4215_SE (1<<6) /* Speaker Enable */
107 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
109 /* Time Slot 7, Input Setting */
110 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
111 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
112 #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
113 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
114 #define CS4215_PIO1 (1<<7)
116 /* Time Slot 8, Input Setting */
117 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
118 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
120 #endif /* _CS4215_H_ */