1 #ifndef __ALPHA_CIA__H__
2 #define __ALPHA_CIA__H__
4 /* Define to experiment with fitting everything into one 512MB HAE window. */
5 #define CIA_ONE_HAE_WINDOW 1
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <asm/compiler.h>
12 * CIA is the internal name for the 21171 chipset which provides
13 * memory controller and PCI access for the 21164 chip based systems.
14 * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
16 * The lineage is a bit confused, since the 21174 was reportedly started
17 * from the 21171 Pass 1 mask, and so is missing bug fixes that appear
18 * in 21171 Pass 2 and 21172, but it also contains additional features.
20 * This file is based on:
22 * DECchip 21171 Core Logic Chipset
23 * Technical Reference Manual
27 * david.rusling@reo.mts.dec.com Initial Version.
32 * CIA ADDRESS BIT DEFINITIONS
34 * 3333 3333 3322 2222 2222 1111 1111 11
35 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
36 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
38 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
41 * | Transfer Length --+
42 * +-- IO space, not cached
45 * Enable Length Transfer Byte Address
46 * adr<6:5> adr<4:3> Length Enable Adder
47 * ---------------------------------------------
48 * 00 00 Byte 1110 0x000
49 * 01 00 Byte 1101 0x020
50 * 10 00 Byte 1011 0x040
51 * 11 00 Byte 0111 0x060
53 * 00 01 Word 1100 0x008
54 * 01 01 Word 1001 0x028 <= Not supported in this code.
55 * 10 01 Word 0011 0x048
57 * 00 10 Tribyte 1000 0x010
58 * 01 10 Tribyte 0001 0x030
60 * 10 11 Longword 0000 0x058
62 * Note that byte enables are asserted low.
66 #define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
67 #define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
68 #define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
71 * 21171-CA Control and Status Registers
73 #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
74 # define CIA_REV_MASK 0xff
75 #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
76 #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
77 # define CIA_CTRL_PCI_EN (1 << 0)
78 # define CIA_CTRL_PCI_LOCK_EN (1 << 1)
79 # define CIA_CTRL_PCI_LOOP_EN (1 << 2)
80 # define CIA_CTRL_FST_BB_EN (1 << 3)
81 # define CIA_CTRL_PCI_MST_EN (1 << 4)
82 # define CIA_CTRL_PCI_MEM_EN (1 << 5)
83 # define CIA_CTRL_PCI_REQ64_EN (1 << 6)
84 # define CIA_CTRL_PCI_ACK64_EN (1 << 7)
85 # define CIA_CTRL_ADDR_PE_EN (1 << 8)
86 # define CIA_CTRL_PERR_EN (1 << 9)
87 # define CIA_CTRL_FILL_ERR_EN (1 << 10)
88 # define CIA_CTRL_MCHK_ERR_EN (1 << 11)
89 # define CIA_CTRL_ECC_CHK_EN (1 << 12)
90 # define CIA_CTRL_ASSERT_IDLE_BC (1 << 13)
91 # define CIA_CTRL_COM_IDLE_BC (1 << 14)
92 # define CIA_CTRL_CSR_IOA_BYPASS (1 << 15)
93 # define CIA_CTRL_IO_FLUSHREQ_EN (1 << 16)
94 # define CIA_CTRL_CPU_FLUSHREQ_EN (1 << 17)
95 # define CIA_CTRL_ARB_CPU_EN (1 << 18)
96 # define CIA_CTRL_EN_ARB_LINK (1 << 19)
97 # define CIA_CTRL_RD_TYPE_SHIFT 20
98 # define CIA_CTRL_RL_TYPE_SHIFT 24
99 # define CIA_CTRL_RM_TYPE_SHIFT 28
100 # define CIA_CTRL_EN_DMA_RD_PERF (1 << 31)
101 #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
102 # define CIA_CNFG_IOA_BWEN (1 << 0)
103 # define CIA_CNFG_PCI_MWEN (1 << 4)
104 # define CIA_CNFG_PCI_DWEN (1 << 5)
105 # define CIA_CNFG_PCI_WLEN (1 << 8)
106 #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
107 #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
108 #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
109 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
110 #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
111 # define CIA_CACK_EN_LOCK_EN (1 << 0)
112 # define CIA_CACK_EN_MB_EN (1 << 1)
113 # define CIA_CACK_EN_SET_DIRTY_EN (1 << 2)
114 # define CIA_CACK_EN_BC_VICTIM_EN (1 << 3)
118 * 21171-CA Diagnostic Registers
120 #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
121 #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
124 * 21171-CA Performance Monitor registers
126 #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
127 #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
130 * 21171-CA Error registers
132 #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
133 #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
134 #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
135 # define CIA_ERR_COR_ERR (1 << 0)
136 # define CIA_ERR_UN_COR_ERR (1 << 1)
137 # define CIA_ERR_CPU_PE (1 << 2)
138 # define CIA_ERR_MEM_NEM (1 << 3)
139 # define CIA_ERR_PCI_SERR (1 << 4)
140 # define CIA_ERR_PERR (1 << 5)
141 # define CIA_ERR_PCI_ADDR_PE (1 << 6)
142 # define CIA_ERR_RCVD_MAS_ABT (1 << 7)
143 # define CIA_ERR_RCVD_TAR_ABT (1 << 8)
144 # define CIA_ERR_PA_PTE_INV (1 << 9)
145 # define CIA_ERR_FROM_WRT_ERR (1 << 10)
146 # define CIA_ERR_IOA_TIMEOUT (1 << 11)
147 # define CIA_ERR_LOST_CORR_ERR (1 << 16)
148 # define CIA_ERR_LOST_UN_CORR_ERR (1 << 17)
149 # define CIA_ERR_LOST_CPU_PE (1 << 18)
150 # define CIA_ERR_LOST_MEM_NEM (1 << 19)
151 # define CIA_ERR_LOST_PERR (1 << 21)
152 # define CIA_ERR_LOST_PCI_ADDR_PE (1 << 22)
153 # define CIA_ERR_LOST_RCVD_MAS_ABT (1 << 23)
154 # define CIA_ERR_LOST_RCVD_TAR_ABT (1 << 24)
155 # define CIA_ERR_LOST_PA_PTE_INV (1 << 25)
156 # define CIA_ERR_LOST_FROM_WRT_ERR (1 << 26)
157 # define CIA_ERR_LOST_IOA_TIMEOUT (1 << 27)
158 # define CIA_ERR_VALID (1 << 31)
159 #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
160 #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
161 #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
162 #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
163 #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
164 #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
165 #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
166 #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
169 * 21171-CA System configuration registers
171 #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
172 #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
173 #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
174 #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
175 #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
176 #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
177 #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
178 #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
179 #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
180 #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
181 #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
182 #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
185 * 2117A-CA PCI Address and Scatter-Gather Registers.
187 #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
189 #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
190 #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
191 #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
193 #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
194 #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
195 #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
197 #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
198 #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
199 #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
201 #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
202 #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
203 #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
205 #define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100)
206 #define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100)
207 #define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100)
209 #define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL)
212 * 2117A-CA Address Translation Registers.
215 /* 8 tag registers, the first 4 of which are lockable. */
216 #define CIA_IOC_TB_TAGn(n) \
217 (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
219 /* 4 page registers per tag register. */
220 #define CIA_IOC_TBn_PAGEm(n,m) \
221 (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
226 #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
227 #define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
228 #define CIA_IO (IDENT_ADDR + 0x8580000000UL)
229 #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
230 #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
231 #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
232 #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
233 #define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL)
234 #define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
235 #define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL)
236 #define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL)
239 * ALCOR's GRU ASIC registers
241 #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
242 #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
243 #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
244 #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
245 #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
247 #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
248 #define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
249 #define GRU_LED (IDENT_ADDR + 0x8780000800UL)
250 #define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
252 #define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
253 #define XLT_GRU_INT_REQ_BITS 0x80003fffUL
254 #define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
257 * PYXIS interrupt control registers
259 #define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL)
260 #define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL)
261 #define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL)
262 #define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL)
263 #define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
264 #define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL)
265 #define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL)
266 #define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL)
267 #define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL)
268 #define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL)
270 /* Offset between ram physical addresses and pci64 DAC bus addresses. */
271 #define PYXIS_DAC_OFFSET (1UL << 40)
274 * Data structure for handling CIA machine checks.
277 /* System-specific info. */
278 struct el_CIA_sysdata_mcheck {
279 unsigned long cpu_err0;
280 unsigned long cpu_err1;
281 unsigned long cia_err;
282 unsigned long cia_stat;
283 unsigned long err_mask;
284 unsigned long cia_syn;
285 unsigned long mem_err0;
286 unsigned long mem_err1;
287 unsigned long pci_err0;
288 unsigned long pci_err1;
289 unsigned long pci_err2;
295 #ifndef __EXTERN_INLINE
296 #define __EXTERN_INLINE extern inline
297 #define __IO_EXTERN_INLINE
303 * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
304 * series of processors uses a sparse address mapping scheme to
305 * get at PCI memory and I/O.
308 #define vucp volatile unsigned char *
309 #define vusp volatile unsigned short *
310 #define vip volatile int *
311 #define vuip volatile unsigned int *
312 #define vulp volatile unsigned long *
314 __EXTERN_INLINE u8 cia_inb(unsigned long addr)
317 result = *(vip) ((addr << 5) + CIA_IO + 0x00);
318 return __kernel_extbl(result, addr & 3);
321 __EXTERN_INLINE void cia_outb(u8 b, unsigned long addr)
323 unsigned long w = __kernel_insbl(b, addr & 3);
324 *(vuip) ((addr << 5) + CIA_IO + 0x00) = w;
328 __EXTERN_INLINE u16 cia_inw(unsigned long addr)
331 result = *(vip) ((addr << 5) + CIA_IO + 0x08);
332 return __kernel_extwl(result, addr & 3);
335 __EXTERN_INLINE void cia_outw(u16 b, unsigned long addr)
337 unsigned long w = __kernel_inswl(b, addr & 3);
338 *(vuip) ((addr << 5) + CIA_IO + 0x08) = w;
342 __EXTERN_INLINE u32 cia_inl(unsigned long addr)
344 return *(vuip) ((addr << 5) + CIA_IO + 0x18);
347 __EXTERN_INLINE void cia_outl(u32 b, unsigned long addr)
349 *(vuip) ((addr << 5) + CIA_IO + 0x18) = b;
353 __EXTERN_INLINE u8 cia_bwx_inb(unsigned long addr)
355 /* ??? I wish I could get rid of this. But there's no ioremap
356 equivalent for I/O space. PCI I/O can be forced into the
357 CIA BWX I/O region, but that doesn't take care of legacy
360 return __kernel_ldbu(*(vucp)(addr+CIA_BW_IO));
363 __EXTERN_INLINE void cia_bwx_outb(u8 b, unsigned long addr)
365 __kernel_stb(b, *(vucp)(addr+CIA_BW_IO));
369 __EXTERN_INLINE u16 cia_bwx_inw(unsigned long addr)
371 return __kernel_ldwu(*(vusp)(addr+CIA_BW_IO));
374 __EXTERN_INLINE void cia_bwx_outw(u16 b, unsigned long addr)
376 __kernel_stw(b, *(vusp)(addr+CIA_BW_IO));
380 __EXTERN_INLINE u32 cia_bwx_inl(unsigned long addr)
382 return *(vuip)(addr+CIA_BW_IO);
385 __EXTERN_INLINE void cia_bwx_outl(u32 b, unsigned long addr)
387 *(vuip)(addr+CIA_BW_IO) = b;
393 * Memory functions. 64-bit and 32-bit accesses are done through
394 * dense memory space, everything else through sparse space.
396 * For reading and writing 8 and 16 bit quantities we need to
397 * go through one of the three sparse address mapping regions
398 * and use the HAE_MEM CSR to provide some bits of the address.
399 * The following few routines use only sparse address region 1
400 * which gives 1Gbyte of accessible space which relates exactly
401 * to the amount of PCI memory mapping *into* system address space.
402 * See p 6-17 of the specification but it looks something like this:
407 * 9876543210987654321098765432109876543210
408 * 1ZZZZ0.PCI.QW.Address............BBLL
412 * LL = Transfer length
417 * 10987654321098765432109876543210
418 * HHH....PCI.QW.Address........ 00
420 * HHH = 31:29 HAE_MEM CSR
424 __EXTERN_INLINE u8 cia_readb(unsigned long addr)
426 unsigned long result;
428 addr &= CIA_MEM_R1_MASK;
429 result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x00);
430 return __kernel_extbl(result, addr & 3);
433 __EXTERN_INLINE u16 cia_readw(unsigned long addr)
435 unsigned long result;
437 addr &= CIA_MEM_R1_MASK;
438 result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x08);
439 return __kernel_extwl(result, addr & 3);
442 __EXTERN_INLINE void cia_writeb(u8 b, unsigned long addr)
446 addr &= CIA_MEM_R1_MASK;
447 w = __kernel_insbl(b, addr & 3);
448 *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = w;
451 __EXTERN_INLINE void cia_writew(u16 b, unsigned long addr)
455 addr &= CIA_MEM_R1_MASK;
456 w = __kernel_inswl(b, addr & 3);
457 *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = w;
460 __EXTERN_INLINE u32 cia_readl(unsigned long addr)
465 __EXTERN_INLINE u64 cia_readq(unsigned long addr)
470 __EXTERN_INLINE void cia_writel(u32 b, unsigned long addr)
475 __EXTERN_INLINE void cia_writeq(u64 b, unsigned long addr)
480 __EXTERN_INLINE unsigned long cia_ioremap(unsigned long addr,
482 __attribute__((unused)))
484 return addr + CIA_DENSE_MEM;
487 __EXTERN_INLINE void cia_iounmap(unsigned long addr)
492 __EXTERN_INLINE u8 cia_bwx_readb(unsigned long addr)
494 return __kernel_ldbu(*(vucp)addr);
497 __EXTERN_INLINE u16 cia_bwx_readw(unsigned long addr)
499 return __kernel_ldwu(*(vusp)addr);
502 __EXTERN_INLINE u32 cia_bwx_readl(unsigned long addr)
507 __EXTERN_INLINE u64 cia_bwx_readq(unsigned long addr)
512 __EXTERN_INLINE void cia_bwx_writeb(u8 b, unsigned long addr)
514 __kernel_stb(b, *(vucp)addr);
517 __EXTERN_INLINE void cia_bwx_writew(u16 b, unsigned long addr)
519 __kernel_stw(b, *(vusp)addr);
522 __EXTERN_INLINE void cia_bwx_writel(u32 b, unsigned long addr)
527 __EXTERN_INLINE void cia_bwx_writeq(u64 b, unsigned long addr)
532 __EXTERN_INLINE unsigned long cia_bwx_ioremap(unsigned long addr,
535 return addr + CIA_BW_MEM;
538 __EXTERN_INLINE void cia_bwx_iounmap(unsigned long addr)
543 __EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
545 return addr >= IDENT_ADDR + 0x8000000000UL;
556 #ifdef CONFIG_ALPHA_PYXIS
557 # define __inb(p) cia_bwx_inb((unsigned long)(p))
558 # define __inw(p) cia_bwx_inw((unsigned long)(p))
559 # define __inl(p) cia_bwx_inl((unsigned long)(p))
560 # define __outb(x,p) cia_bwx_outb((x),(unsigned long)(p))
561 # define __outw(x,p) cia_bwx_outw((x),(unsigned long)(p))
562 # define __outl(x,p) cia_bwx_outl((x),(unsigned long)(p))
563 # define __readb(a) cia_bwx_readb((unsigned long)(a))
564 # define __readw(a) cia_bwx_readw((unsigned long)(a))
565 # define __readl(a) cia_bwx_readl((unsigned long)(a))
566 # define __readq(a) cia_bwx_readq((unsigned long)(a))
567 # define __writeb(x,a) cia_bwx_writeb((x),(unsigned long)(a))
568 # define __writew(x,a) cia_bwx_writew((x),(unsigned long)(a))
569 # define __writel(x,a) cia_bwx_writel((x),(unsigned long)(a))
570 # define __writeq(x,a) cia_bwx_writeq((x),(unsigned long)(a))
571 # define __ioremap(a,s) cia_bwx_ioremap((unsigned long)(a),(s))
572 # define __iounmap(a) cia_bwx_iounmap((unsigned long)(a))
573 # define inb(p) __inb(p)
574 # define inw(p) __inw(p)
575 # define inl(p) __inl(p)
576 # define outb(x,p) __outb((x),(p))
577 # define outw(x,p) __outw((x),(p))
578 # define outl(x,p) __outl((x),(p))
579 # define __raw_readb(a) __readb(a)
580 # define __raw_readw(a) __readw(a)
581 # define __raw_readl(a) __readl(a)
582 # define __raw_readq(a) __readq(a)
583 # define __raw_writeb(x,a) __writeb((x),(a))
584 # define __raw_writew(x,a) __writew((x),(a))
585 # define __raw_writel(x,a) __writel((x),(a))
586 # define __raw_writeq(x,a) __writeq((x),(a))
588 # define __inb(p) cia_inb((unsigned long)(p))
589 # define __inw(p) cia_inw((unsigned long)(p))
590 # define __inl(p) cia_inl((unsigned long)(p))
591 # define __outb(x,p) cia_outb((x),(unsigned long)(p))
592 # define __outw(x,p) cia_outw((x),(unsigned long)(p))
593 # define __outl(x,p) cia_outl((x),(unsigned long)(p))
594 # define __readb(a) cia_readb((unsigned long)(a))
595 # define __readw(a) cia_readw((unsigned long)(a))
596 # define __readl(a) cia_readl((unsigned long)(a))
597 # define __readq(a) cia_readq((unsigned long)(a))
598 # define __writeb(x,a) cia_writeb((x),(unsigned long)(a))
599 # define __writew(x,a) cia_writew((x),(unsigned long)(a))
600 # define __writel(x,a) cia_writel((x),(unsigned long)(a))
601 # define __writeq(x,a) cia_writeq((x),(unsigned long)(a))
602 # define __ioremap(a,s) cia_ioremap((unsigned long)(a),(s))
603 # define __iounmap(a) cia_iounmap((unsigned long)(a))
604 # define __raw_readl(a) __readl(a)
605 # define __raw_readq(a) __readq(a)
606 # define __raw_writel(v,a) __writel((v),(a))
607 # define __raw_writeq(v,a) __writeq((v),(a))
610 #define __is_ioaddr(a) cia_is_ioaddr((unsigned long)(a))
612 #endif /* __WANT_IO_DEF */
614 #ifdef __IO_EXTERN_INLINE
615 #undef __EXTERN_INLINE
616 #undef __IO_EXTERN_INLINE
619 #endif /* __KERNEL__ */
621 #endif /* __ALPHA_CIA__H__ */