2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <linux/cache.h>
18 #include <linux/config.h>
19 #include <linux/threads.h>
22 * Default implementation of macro that returns current
23 * instruction pointer ("program counter").
25 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
28 * CPU type and hardware bug flags. Kept separately for each CPU.
29 * Members of this structure are referenced in head.S, so think twice
30 * before touching them. [mj]
34 __u8 x86; /* CPU family */
35 __u8 x86_vendor; /* CPU vendor */
38 char wp_works_ok; /* It doesn't on 386's */
39 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
42 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
43 __u32 x86_capability[NCAPINTS];
44 char x86_vendor_id[16];
45 char x86_model_id[64];
46 int x86_cache_size; /* in KB - valid for CPUS which support this
51 unsigned long loops_per_jiffy;
52 unsigned long *pgd_quick;
53 unsigned long *pmd_quick;
54 unsigned long *pte_quick;
55 unsigned long pgtable_cache_sz;
56 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
58 #define X86_VENDOR_INTEL 0
59 #define X86_VENDOR_CYRIX 1
60 #define X86_VENDOR_AMD 2
61 #define X86_VENDOR_UMC 3
62 #define X86_VENDOR_NEXGEN 4
63 #define X86_VENDOR_CENTAUR 5
64 #define X86_VENDOR_RISE 6
65 #define X86_VENDOR_TRANSMETA 7
66 #define X86_VENDOR_NSC 8
67 #define X86_VENDOR_UNKNOWN 0xff
70 * capabilities of CPUs
73 extern struct cpuinfo_x86 boot_cpu_data;
74 extern struct tss_struct init_tss[NR_CPUS];
77 extern struct cpuinfo_x86 cpu_data[];
78 #define current_cpu_data cpu_data[smp_processor_id()]
80 #define cpu_data (&boot_cpu_data)
81 #define current_cpu_data boot_cpu_data
84 #define cpu_has_pge (test_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability))
85 #define cpu_has_pse (test_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability))
86 #define cpu_has_pae (test_bit(X86_FEATURE_PAE, boot_cpu_data.x86_capability))
87 #define cpu_has_tsc (test_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability))
88 #define cpu_has_de (test_bit(X86_FEATURE_DE, boot_cpu_data.x86_capability))
89 #define cpu_has_vme (test_bit(X86_FEATURE_VME, boot_cpu_data.x86_capability))
90 #define cpu_has_fxsr (test_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability))
91 #define cpu_has_xmm (test_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability))
92 #define cpu_has_fpu (test_bit(X86_FEATURE_FPU, boot_cpu_data.x86_capability))
93 #define cpu_has_apic (test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability))
95 extern char ignore_irq13;
97 extern void identify_cpu(struct cpuinfo_x86 *);
98 extern void print_cpu_info(struct cpuinfo_x86 *);
99 extern void dodgy_tsc(void);
104 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
105 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
106 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
107 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
108 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
109 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
110 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
111 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
112 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
113 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
114 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
115 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
116 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
117 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
118 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
119 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
120 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
123 * Generic CPUID function
125 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
136 * CPUID functions returning a single datum
138 static inline unsigned int cpuid_eax(unsigned int op)
148 static inline unsigned int cpuid_ebx(unsigned int op)
150 unsigned int eax, ebx;
153 : "=a" (eax), "=b" (ebx)
158 static inline unsigned int cpuid_ecx(unsigned int op)
160 unsigned int eax, ecx;
163 : "=a" (eax), "=c" (ecx)
168 static inline unsigned int cpuid_edx(unsigned int op)
170 unsigned int eax, edx;
173 : "=a" (eax), "=d" (edx)
180 * Intel CPU features in CR4
182 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
183 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
184 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
185 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
186 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
187 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
188 #define X86_CR4_MCE 0x0040 /* Machine check enable */
189 #define X86_CR4_PGE 0x0080 /* enable global pages */
190 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
191 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
192 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
194 #define load_cr3(pgdir) \
195 asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)));
198 * Save the cr4 feature set we're using (ie
199 * Pentium 4MB enable and PPro Global page
200 * enable), so that any CPU's that boot up
201 * after us can get the correct flags.
203 extern unsigned long mmu_cr4_features;
205 static inline void set_in_cr4 (unsigned long mask)
207 mmu_cr4_features |= mask;
208 __asm__("movl %%cr4,%%eax\n\t"
215 static inline void clear_in_cr4 (unsigned long mask)
217 mmu_cr4_features &= ~mask;
218 __asm__("movl %%cr4,%%eax\n\t"
226 * Cyrix CPU configuration register indexes
228 #define CX86_CCR0 0xc0
229 #define CX86_CCR1 0xc1
230 #define CX86_CCR2 0xc2
231 #define CX86_CCR3 0xc3
232 #define CX86_CCR4 0xe8
233 #define CX86_CCR5 0xe9
234 #define CX86_CCR6 0xea
235 #define CX86_CCR7 0xeb
236 #define CX86_DIR0 0xfe
237 #define CX86_DIR1 0xff
238 #define CX86_ARR_BASE 0xc4
239 #define CX86_RCR_BASE 0xdc
242 * Cyrix CPU indexed register access macros
245 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
247 #define setCx86(reg, data) do { \
249 outb((data), 0x23); \
253 * Bus types (default is ISA, but people can check others with these..)
262 /* from system description table in BIOS. Mostly for MCA use, but
263 others may find it useful. */
264 extern unsigned int machine_id;
265 extern unsigned int machine_submodel_id;
266 extern unsigned int BIOS_revision;
267 extern unsigned int mca_pentium_flag;
270 * User space process size: 3GB (default).
272 #define TASK_SIZE (PAGE_OFFSET)
274 /* This decides where the kernel will search for a free chunk of vm
275 * space during mmap's.
277 #define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
280 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
282 #define IO_BITMAP_SIZE 32
283 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
284 #define INVALID_IO_BITMAP_OFFSET 0x8000
286 struct i387_fsave_struct {
294 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
295 long status; /* software status information */
298 struct i387_fxsave_struct {
309 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
310 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
312 } __attribute__ ((aligned (16)));
314 struct i387_soft_struct {
322 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
323 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
325 unsigned long entry_eip;
329 struct i387_fsave_struct fsave;
330 struct i387_fxsave_struct fxsave;
331 struct i387_soft_struct soft;
339 unsigned short back_link,__blh;
341 unsigned short ss0,__ss0h;
343 unsigned short ss1,__ss1h;
345 unsigned short ss2,__ss2h;
348 unsigned long eflags;
349 unsigned long eax,ecx,edx,ebx;
354 unsigned short es, __esh;
355 unsigned short cs, __csh;
356 unsigned short ss, __ssh;
357 unsigned short ds, __dsh;
358 unsigned short fs, __fsh;
359 unsigned short gs, __gsh;
360 unsigned short ldt, __ldth;
361 unsigned short trace, bitmap;
362 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
364 * pads the TSS to be cacheline-aligned (size is 0x100)
366 unsigned long __cacheline_filler[5];
369 struct thread_struct {
375 /* Hardware debugging registers */
376 unsigned long debugreg[8]; /* %%db0-7 debug registers */
378 unsigned long cr2, trap_no, error_code;
379 /* floating point info */
380 union i387_union i387;
381 /* virtual 86 mode info */
382 struct vm86_struct * vm86_info;
383 unsigned long screen_bitmap;
384 unsigned long v86flags, v86mask, saved_esp0;
387 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
390 #define INIT_THREAD { \
393 { [0 ... 7] = 0 }, /* debugging registers */ \
395 { { 0, }, }, /* 387 state */ \
397 0,{~0,} /* io permissions */ \
401 0,0, /* back_link, __blh */ \
402 sizeof(init_stack) + (long) &init_stack, /* esp0 */ \
403 __KERNEL_DS, 0, /* ss0 */ \
404 0,0,0,0,0,0, /* stack1, stack2 */ \
406 0,0, /* eip,eflags */ \
407 0,0,0,0, /* eax,ecx,edx,ebx */ \
408 0,0,0,0, /* esp,ebp,esi,edi */ \
409 0,0,0,0,0,0, /* es,cs,ss */ \
410 0,0,0,0,0,0, /* ds,fs,gs */ \
411 __LDT(0),0, /* ldt */ \
412 0, INVALID_IO_BITMAP_OFFSET, /* tace, bitmap */ \
413 {~0, } /* ioperm */ \
416 #define start_thread(regs, new_eip, new_esp) do { \
417 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
419 regs->xds = __USER_DS; \
420 regs->xes = __USER_DS; \
421 regs->xss = __USER_DS; \
422 regs->xcs = __USER_CS; \
423 regs->eip = new_eip; \
424 regs->esp = new_esp; \
427 /* Forward declaration, a strange C thing */
431 /* Free all resources held by a thread. */
432 extern void release_thread(struct task_struct *);
434 * create a kernel thread without removing it from tasklists
436 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
438 /* Copy and release all segment info associated with a VM */
439 extern void copy_segments(struct task_struct *p, struct mm_struct * mm);
440 extern void release_segments(struct mm_struct * mm);
443 * Return saved PC of a blocked thread.
445 static inline unsigned long thread_saved_pc(struct thread_struct *t)
447 return ((unsigned long *)t->esp)[3];
450 unsigned long get_wchan(struct task_struct *p);
451 #define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
452 #define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
454 #define THREAD_SIZE (2*PAGE_SIZE)
455 #define alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
456 #define free_task_struct(p) free_pages((unsigned long) (p), 1)
457 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
459 #define init_task (init_task_union.task)
460 #define init_stack (init_task_union.stack)
470 unsigned int reserved[5];
471 unsigned int bits[500];
474 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
475 #define MICROCODE_IOCFREE _IO('6',0)
477 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
478 static inline void rep_nop(void)
480 __asm__ __volatile__("rep;nop");
483 #define cpu_relax() rep_nop()
485 /* Prefetch instructions for Pentium III and AMD Athlon */
486 #ifdef CONFIG_MPENTIUMIII
488 #define ARCH_HAS_PREFETCH
489 extern inline void prefetch(const void *x)
491 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
494 #elif CONFIG_X86_USE_3DNOW
496 #define ARCH_HAS_PREFETCH
497 #define ARCH_HAS_PREFETCHW
498 #define ARCH_HAS_SPINLOCK_PREFETCH
500 extern inline void prefetch(const void *x)
502 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
505 extern inline void prefetchw(const void *x)
507 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
509 #define spin_lock_prefetch(x) prefetchw(x)
513 #endif /* __ASM_I386_PROCESSOR_H */