1 #ifndef _I386_STRING_I486_H_
2 #define _I386_STRING_I486_H_
5 * This string-include defines all string functions as inline
6 * functions. Use gcc. It also assumes ds=es=data space, this should be
7 * normal. Most of the string-functions are rather heavily hand-optimized,
8 * see especially strtok,strstr,str[c]spn. They should work, but are not
9 * very easy to understand. Everything is done entirely within the register
10 * set, making the functions fast and clean.
12 * Copyright (C) 1991, 1992 Linus Torvalds
13 * Revised and optimized for i486/pentium
14 * 1994/03/15 by Alberto Vignani/Davide Parodi @crf.it
16 * Split into 2 CPU specific files by Alan Cox to keep #ifdef noise down.
18 * 1999/10/5 Proper register args for newer GCCs and minor bugs
19 * fixed - Petko Manolov (petkan@spct.net)
20 * 1999/10/14 3DNow memscpy() added - Petkan
21 * 2000/05/09 extern changed to static in function definitions
22 * and a few cleanups - Petkan
25 #define __HAVE_ARCH_STRCPY
26 static inline char * strcpy(char * dest,const char *src)
28 register char *tmp= (char *)dest;
38 :"=r" (src), "=r" (tmp), "=q" (dummy)
44 #define __HAVE_ARCH_STRNCPY
45 static inline char * strncpy(char * dest,const char *src,size_t count)
47 register char *tmp= (char *)dest;
60 "2:\tmovb %2,(%1)\n\t"
65 :"=r" (src), "=r" (tmp), "=q" (dummy), "=r" (count)
66 :"0" (src), "1" (tmp), "3" (count)
72 #define __HAVE_ARCH_STRCAT
73 static inline char * strcat(char * dest,const char * src)
75 register char *tmp = (char *)(dest-1);
81 "2:\tmovb (%2),%b0\n\t"
87 :"=q" (dummy), "=r" (tmp), "=r" (src)
93 #define __HAVE_ARCH_STRNCAT
94 static inline char * strncat(char * dest,const char * src,size_t count)
96 register char *tmp = (char *)(dest-1);
112 :"=q" (dummy), "=r" (tmp), "=r" (src), "=r" (count)
113 :"1" (tmp), "2" (src), "3" (count)
118 #define __HAVE_ARCH_STRCMP
119 static inline int strcmp(const char * cs,const char * ct)
122 __asm__ __volatile__(
123 "\n1:\tmovb (%1),%b0\n\t"
136 :"=q" (__res), "=r" (cs), "=r" (ct)
142 #define __HAVE_ARCH_STRNCMP
143 static inline int strncmp(const char * cs,const char * ct,size_t count)
146 __asm__ __volatile__(
162 :"=q" (__res), "=r" (cs), "=r" (ct), "=r" (count)
163 :"1" (cs), "2" (ct), "3" (count));
167 #define __HAVE_ARCH_STRCHR
168 static inline char * strchr(const char * s, int c)
170 register char * __res;
171 __asm__ __volatile__(
173 "1:\tmovb (%1),%%al\n\t"
177 "testb %%al,%%al\n\t"
181 :"=a" (__res), "=r" (s)
186 #define __HAVE_ARCH_STRRCHR
187 static inline char * strrchr(const char * s, int c)
190 register char * __res;
191 __asm__ __volatile__(
196 "leal -1(%%esi),%0\n"
197 "2:\ttestb %%al,%%al\n\t"
199 :"=d" (__res), "=&S" (d0), "=&a" (d1)
200 :"0" (0), "1" (s), "2" (c));
205 #define __HAVE_ARCH_STRCSPN
206 static inline size_t strcspn(const char * cs, const char * ct)
209 register char * __res;
210 __asm__ __volatile__(
218 "testb %%al,%%al\n\t"
221 "movl %%edx,%%ecx\n\t"
226 :"=S" (__res), "=&a" (d0), "=&c" (d1)
227 :"0" (cs), "1" (0), "2" (0xffffffff), "g" (ct)
233 #define __HAVE_ARCH_STRLEN
234 static inline size_t strlen(const char * s)
237 * slightly slower on a 486, but with better chances of
238 * register allocation
240 register char dummy, *tmp= (char *)s;
241 __asm__ __volatile__(
247 :"=r" (tmp),"=q" (dummy)
253 /* Added by Gertjan van Wingerde to make minix and sysv module work */
254 #define __HAVE_ARCH_STRNLEN
255 static inline size_t strnlen(const char * s, size_t count)
259 __asm__ __volatile__(
262 "1:\tcmpb $0,(%0)\n\t"
269 :"=a" (__res), "=&d" (d0)
270 :"1" (count), "c" (s));
273 /* end of additional stuff */
277 * These ought to get tweaked to do some cache priming.
280 static inline void * __memcpy_by4(void * to, const void * from, size_t n)
282 register void *tmp = (void *)to;
283 register int dummy1,dummy2;
284 __asm__ __volatile__ (
285 "\n1:\tmovl (%2),%0\n\t"
291 :"=r" (dummy1), "=r" (tmp), "=r" (from), "=r" (dummy2)
292 :"1" (tmp), "2" (from), "3" (n/4)
297 static inline void * __memcpy_by2(void * to, const void * from, size_t n)
299 register void *tmp = (void *)to;
300 register int dummy1,dummy2;
301 __asm__ __volatile__ (
303 "jz 2f\n" /* only a word */
304 "1:\tmovl (%2),%0\n\t"
310 "2:\tmovw (%2),%w0\n\t"
312 :"=r" (dummy1), "=r" (tmp), "=r" (from), "=r" (dummy2)
313 :"1" (tmp), "2" (from), "3" (n/2)
318 static inline void * __memcpy_g(void * to, const void * from, size_t n)
321 register void *tmp = (void *)to;
322 __asm__ __volatile__ (
326 "1:\tshrl $1,%%ecx\n\t"
331 :"=&c" (d0), "=&D" (d1), "=&S" (d2)
332 :"0" (n), "1" ((long) tmp), "2" ((long) from)
337 #define __memcpy_c(d,s,count) \
339 __memcpy_by4((d),(s),(count)) : \
341 __memcpy_by2((d),(s),(count)) : \
342 __memcpy_g((d),(s),(count))))
344 #define __memcpy(d,s,count) \
345 (__builtin_constant_p(count) ? \
346 __memcpy_c((d),(s),(count)) : \
347 __memcpy_g((d),(s),(count)))
349 #define __HAVE_ARCH_MEMCPY
351 #include <linux/config.h>
353 #ifdef CONFIG_X86_USE_3DNOW
358 ** This CPU favours 3DNow strongly (eg AMD K6-II, K6-III, Athlon)
361 static inline void * __constant_memcpy3d(void * to, const void * from, size_t len)
364 return __memcpy_c(to, from, len);
365 return _mmx_memcpy(to, from, len);
368 static inline void *__memcpy3d(void *to, const void *from, size_t len)
371 return __memcpy_g(to, from, len);
372 return _mmx_memcpy(to, from, len);
375 #define memcpy(d, s, count) \
376 (__builtin_constant_p(count) ? \
377 __constant_memcpy3d((d),(s),(count)) : \
378 __memcpy3d((d),(s),(count)))
380 #else /* CONFIG_X86_USE_3DNOW */
387 #define memcpy(d, s, count) __memcpy(d, s, count)
389 #endif /* CONFIG_X86_USE_3DNOW */
392 extern void __struct_cpy_bug( void );
394 #define struct_cpy(x,y) \
396 if (sizeof(*(x)) != sizeof(*(y))) \
398 memcpy(x, y, sizeof(*(x))); \
402 #define __HAVE_ARCH_MEMMOVE
403 static inline void * memmove(void * dest,const void * src, size_t n)
406 register void *tmp = (void *)dest;
408 __asm__ __volatile__ (
411 :"=&c" (d0), "=&S" (d1), "=&D" (d2)
412 :"0" (n), "1" (src), "2" (tmp)
415 __asm__ __volatile__ (
420 :"=&c" (d0), "=&S" (d1), "=&D" (d2)
421 :"0" (n), "1" (n-1+(const char *)src), "2" (n-1+(char *)tmp)
427 #define __HAVE_ARCH_MEMCMP
428 static inline int memcmp(const void * cs,const void * ct,size_t count)
432 __asm__ __volatile__(
439 :"=a" (__res), "=&S" (d0), "=&D" (d1), "=&c" (d2)
440 :"0" (0), "1" (cs), "2" (ct), "3" (count));
445 #define __HAVE_ARCH_MEMCHR
446 static inline void * memchr(const void * cs,int c,size_t count)
449 register void * __res;
452 __asm__ __volatile__(
458 :"=D" (__res), "=&c" (d0)
459 :"a" (c), "0" (cs), "1" (count));
463 #define __memset_cc(s,c,count) \
465 __memset_cc_by4((s),(c),(count)) : \
467 __memset_cc_by2((s),(c),(count)) : \
468 __memset_cg((s),(c),(count))))
470 #define __memset_gc(s,c,count) \
472 __memset_gc_by4((s),(c),(count)) : \
474 __memset_gc_by2((s),(c),(count)) : \
475 __memset_gg((s),(c),(count))))
477 #define __HAVE_ARCH_MEMSET
478 #define memset(s,c,count) \
479 (__builtin_constant_p(c) ? \
480 (__builtin_constant_p(count) ? \
481 __memset_cc((s),(c),(count)) : \
482 __memset_cg((s),(c),(count))) : \
483 (__builtin_constant_p(count) ? \
484 __memset_gc((s),(c),(count)) : \
485 __memset_gg((s),(c),(count))))
487 static inline void * __memset_cc_by4(void * s, char c, size_t count)
490 * register char *tmp = s;
492 register char *tmp = (char *)s;
494 __asm__ __volatile__ (
495 "\n1:\tmovl %2,(%0)\n\t"
499 :"=r" (tmp), "=r" (dummy)
500 :"q" (0x01010101UL * (unsigned char) c), "0" (tmp), "1" (count/4)
505 static inline void * __memset_cc_by2(void * s, char c, size_t count)
507 register void *tmp = (void *)s;
509 __asm__ __volatile__ (
510 "shrl $1,%1\n\t" /* may be divisible also by 4 */
512 "\n1:\tmovl %2,(%0)\n\t"
517 :"=r" (tmp), "=r" (dummy)
518 :"q" (0x01010101UL * (unsigned char) c), "0" (tmp), "1" (count/2)
523 static inline void * __memset_gc_by4(void * s, char c, size_t count)
525 register void *tmp = (void *)s;
527 __asm__ __volatile__ (
532 "1:\tmovl %0,(%1)\n\t"
536 :"=q" (c), "=r" (tmp), "=r" (dummy)
537 :"0" ((unsigned) c), "1" (tmp), "2" (count/4)
542 static inline void * __memset_gc_by2(void * s, char c, size_t count)
544 register void *tmp = (void *)s;
545 register int dummy1,dummy2;
546 __asm__ __volatile__ (
548 "shrl $1,%2\n\t" /* may be divisible also by 4 */
553 "1:\tmovl %0,(%1)\n\t"
558 :"=q" (dummy1), "=r" (tmp), "=r" (dummy2)
559 :"0" ((unsigned) c), "1" (tmp), "2" (count/2)
564 static inline void * __memset_cg(void * s, char c, size_t count)
567 register void *tmp = (void *)s;
568 __asm__ __volatile__ (
573 "movb %%al,(%%edi)\n"
575 :"=&c" (d0), "=&D" (d1)
576 :"a" (0x0101U * (unsigned char) c), "0" (count), "1" (tmp)
581 static inline void * __memset_gg(void * s,char c,size_t count)
584 register void *tmp = (void *)s;
585 __asm__ __volatile__ (
591 "movb %%al,(%%edi)\n"
593 :"=&c" (d0), "=&D" (d1), "=&D" (d2)
594 :"0" (count), "1" (tmp), "2" (c)
601 * find the first occurrence of byte 'c', or 1 past the area if none
603 #define __HAVE_ARCH_MEMSCAN
604 static inline void * memscan(void * addr, int c, size_t size)
608 __asm__("repnz; scasb
612 : "=D" (addr), "=c" (size)
613 : "0" (addr), "1" (size), "a" (c));