2 * cpu-sa1100.c: clock scaling for the SA1100
4 * Copyright (C) 2000 2001, The Delft University of Technology
7 * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
8 * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
9 * - major rewrite for linux-2.3.99
10 * - rewritten for the more generic power management scheme in
13 * This software has been developed while working on the LART
14 * computing board (http://www.lart.tudelft.nl/), which is
15 * sponsored by the Mobile Multi-media Communications
16 * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications
17 * (http://www.ubicom.tudelft.nl/) projects.
19 * The authors can be reached at:
22 * Information and Communication Theory Group
23 * Faculty of Information Technology and Systems
24 * Delft University of Technology
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2 of the License, or
33 * (at your option) any later version.
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * Theory of operations
46 * ====================
48 * Clock scaling can be used to lower the power consumption of the CPU
49 * core. This will give you a somewhat longer running time.
51 * The SA-1100 has a single register to change the core clock speed:
53 * PPCR 0x90020014 PLL config
55 * However, the DRAM timings are closely related to the core clock
56 * speed, so we need to change these, too. The used registers are:
58 * MDCNFG 0xA0000000 DRAM config
59 * MDCAS0 0xA0000004 Access waveform
60 * MDCAS1 0xA0000008 Access waveform
61 * MDCAS2 0xA000000C Access waveform
63 * Care must be taken to change the DRAM parameters the correct way,
64 * because otherwise the DRAM becomes unusable and the kernel will
67 * The simple solution to avoid a kernel crash is to put the actual
68 * clock change in ROM and jump to that code from the kernel. The main
69 * disadvantage is that the ROM has to be modified, which is not
70 * possible on all SA-1100 platforms. Another disadvantage is that
71 * jumping to ROM makes clock switching unecessary complicated.
73 * The idea behind this driver is that the memory configuration can be
74 * changed while running from DRAM (even with interrupts turned on!)
75 * as long as all re-configuration steps yield a valid DRAM
76 * configuration. The advantages are clear: it will run on all SA-1100
77 * platforms, and the code is very simple.
79 * If you really want to understand what is going on in
80 * sa1100_update_dram_timings(), you'll have to read sections 8.2,
81 * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor
82 * Developers Manual" (available for free from Intel).
86 #include <linux/kernel.h>
87 #include <linux/types.h>
88 #include <linux/init.h>
89 #include <linux/cpufreq.h>
91 #include <asm/hardware.h>
93 extern unsigned int sa11x0_freq_to_ppcr(unsigned int khz);
94 extern unsigned int sa11x0_validatespeed(unsigned int khz);
103 } sa1100_dram_regs_t;
108 static sa1100_dram_regs_t sa1100_dram_settings[] =
110 /* { mdcnfg, mdcas0, mdcas1, mdcas2 } */ /* clock frequency */
111 { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 59.0 MHz */
112 { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 73.7 MHz */
113 { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 88.5 MHz */
114 { 103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 103.2 MHz */
115 { 118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 118.0 MHz */
116 { 132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 132.7 MHz */
117 { 147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff }, /* 147.5 MHz */
118 { 162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff }, /* 162.2 MHz */
119 { 176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff }, /* 176.9 MHz */
120 { 191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff }, /* 191.7 MHz */
121 { 206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 206.4 MHz */
122 { 221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 221.2 MHz */
123 { 235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1 }, /* 235.9 MHz */
124 { 250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 250.7 MHz */
125 { 265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 265.4 MHz */
126 { 280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87 }, /* 280.2 MHz */
127 { 0, 0, 0, 0, 0 } /* last entry */
133 static void sa1100_update_dram_timings(int current_speed, int new_speed)
135 sa1100_dram_regs_t *settings = sa1100_dram_settings;
138 while(settings->speed != 0) {
139 if(new_speed == settings->speed)
145 if(settings->speed == 0) {
146 panic("%s: couldn't find dram setting for speed %d\n",
147 __FUNCTION__, new_speed);
150 /* No risk, no fun: run with interrupts on! */
151 if(new_speed > current_speed) {
152 /* We're going FASTER, so first relax the memory
153 * timings before changing the core frequency
156 /* Half the memory access clock */
157 MDCNFG |= MDCNFG_CDB2;
159 /* The order of these statements IS important, keep 8
162 MDCAS2 = settings->mdcas2;
163 MDCAS1 = settings->mdcas1;
164 MDCAS0 = settings->mdcas0;
165 MDCNFG = settings->mdcnfg;
167 /* We're going SLOWER: first decrease the core
168 * frequency and then tighten the memory settings.
171 /* Half the memory access clock */
172 MDCNFG |= MDCNFG_CDB2;
174 /* The order of these statements IS important, keep 8
177 MDCAS0 = settings->mdcas0;
178 MDCAS1 = settings->mdcas1;
179 MDCAS2 = settings->mdcas2;
180 MDCNFG = settings->mdcnfg;
187 static int sa1100_dram_notifier(struct notifier_block *nb,
188 unsigned long val, void *data)
190 struct cpufreq_info *ci = data;
194 cpufreq_updateminmax(data, sa1100_dram_settings->speed, -1);
197 case CPUFREQ_PRECHANGE:
198 if(ci->new_freq > ci->old_freq)
199 sa1100_update_dram_timings(ci->old_freq, ci->new_freq);
202 case CPUFREQ_POSTCHANGE:
203 if(ci->new_freq < ci->old_freq)
204 sa1100_update_dram_timings(ci->old_freq, ci->new_freq);
208 printk(KERN_INFO "%s: ignoring unknown notifier type (%ld)\n",
218 static struct notifier_block sa1100_dram_block = {
219 .notifier_call = sa1100_dram_notifier,
223 static void sa1100_setspeed(unsigned int khz)
225 PPCR = sa11x0_freq_to_ppcr(khz);
228 static int __init sa1100_dram_init(void)
232 if ((processor_id & CPU_SA1100_MASK) == CPU_SA1100_ID) {
233 ret = cpufreq_register_notifier(&sa1100_dram_block);
235 cpufreq_setfunctions(sa11x0_validatespeed, sa1100_setspeed);
241 __initcall(sa1100_dram_init);