arch/cris/drivers/sync_serial.c

   1 /*
   2  * Simple synchronous serial port driver for ETRAX 100LX.
   3  *
   4  * Synchronous serial ports are used for continuous streamed data like audio.
   5  * The default setting for this driver is compatible with the STA 013 MP3
   6  * decoder. The driver can easily be tuned to fit other audio encoder/decoders
   7  * and SPI
   8  *
   9  * Copyright (c) 2001-2003 Axis Communications AB
  10  *
  11  * Author: Mikael Starvik, Johan Adolfsson
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/config.h>
  17 #include <linux/types.h>
  18 #include <linux/errno.h>
  19 #include <linux/major.h>
  20 #include <linux/sched.h>
  21 #include <linux/slab.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/poll.h>
  24 #include <linux/init.h>
  25 #include <linux/timer.h>
  26 #include <asm/irq.h>
  27 #include <asm/io.h>
  28 #include <asm/svinto.h>
  29 #include <asm/uaccess.h>
  30 #include <asm/system.h>
  31 #include <asm/sync_serial.h>
  32
  33 /* The receiver is a bit tricky beacuse of the continuous stream of data.*/
  34 /*                                                                       */
  35 /* Three DMA descriptors are linked together. Each DMA descriptor is     */
  36 /* responsible for port->bufchunk of a common buffer.                    */
  37 /*                                                                       */
  38 /* +---------------------------------------------+                       */
  39 /* |   +----------+   +----------+   +----------+ |                      */
  40 /* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+                      */
  41 /*     +----------+   +----------+   +----------+                        */
  42 /*         |            |              |                                 */
  43 /*         v            v              v                                 */
  44 /*   +-------------------------------------+                             */
  45 /*   |        BUFFER                       |                             */
  46 /*   +-------------------------------------+                             */
  47 /*      |<- data_avail ->|                                               */
  48 /*    readp          writep                                              */
  49 /*                                                                       */
  50 /* If the application keeps up the pace readp will be right after writep.*/
  51 /* If the application can't keep the pace we have to throw away data.    */
  52 /* The idea is that readp should be ready with the data pointed out by   */
  53 /* Descr[i] when the DMA has filled in Descr[i+1].                       */
  54 /* Otherwise we will discard                                             */
  55 /* the rest of the data pointed out by Descr1 and set readp to the start */
  56 /* of Descr2                                                             */
  57
  58 #define SYNC_SERIAL_MAJOR 125
  59
  60 /* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
  61 /* words can be handled */
  62 #define NUM_IN_DESCR 3
  63 #define IN_BUFFER_SIZE 12288
  64 #define OUT_BUFFER_SIZE 4096
  65
  66 #define DEFAULT_FRAME_RATE 0
  67 #define DEFAULT_WORD_RATE 7
  68
  69 /* NOTE: Enabling some debug will likely cause overrun or underrun,
  70  * especially if manual mode is use.
  71  */
  72 #define DEBUG(x)
  73 #define DEBUGREAD(x)
  74 #define DEBUGWRITE(x)
  75 #define DEBUGPOLL(x)
  76 #define DEBUGRXINT(x)
  77 #define DEBUGTXINT(x)
  78
  79 /* Define some macros to access ETRAX 100 registers */
  80 #define SETF(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
  81                                           IO_FIELD_(reg##_, field##_, val)
  82 #define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
  83                                           IO_STATE_(reg##_, field##_, _##val)
  84
  85 typedef struct sync_port
  86 {
  87         /* Etrax registers and bits*/
  88         const volatile unsigned * const status;
  89         volatile unsigned * const ctrl_data;
  90         volatile unsigned * const output_dma_first;
  91         volatile unsigned char * const output_dma_cmd;
  92         volatile unsigned char * const output_dma_clr_irq;
  93         volatile unsigned * const input_dma_first;
  94         volatile unsigned char * const input_dma_cmd;
  95         volatile unsigned * const input_dma_descr;
  96         /* 8*4 */
  97         volatile unsigned char * const input_dma_clr_irq;
  98         volatile unsigned * const data_out;
  99         const volatile unsigned * const data_in;
 100         char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
 101         char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
 102         char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */
 103
 104         char output_dma_bit; /* In R_IRQ_MASK2_RD */
 105         /* End of fields initialised in array */
 106         char started; /* 1 if port has been started */
 107         char port_nbr; /* Port 0 or 1 */
 108         char busy; /* 1 if port is busy */
 109
 110         char enabled;  /* 1 if port is enabled */
 111         char use_dma;  /* 1 if port uses dma */
 112         char cur_in_descr;
 113         char tr_running;
 114
 115         unsigned int ctrl_data_shadow; /* Register shadow */
 116         volatile unsigned int out_count; /* Remaining bytes for current transfer */
 117         unsigned char* outp; /* Current position in out_buffer */
 118         /* 16*4 */
 119         volatile unsigned char* volatile readp;  /* Next byte to be read by application */
 120         volatile unsigned char* volatile writep; /* Next byte to be written by etrax */
 121         unsigned int in_buffer_size;
 122         unsigned int inbufchunk;
 123         struct etrax_dma_descr out_descr;
 124         struct etrax_dma_descr in_descr[NUM_IN_DESCR];
 125         unsigned char out_buffer[OUT_BUFFER_SIZE];
 126         unsigned char in_buffer[IN_BUFFER_SIZE];
 127
 128         wait_queue_head_t out_wait_q;
 129         wait_queue_head_t in_wait_q;
 130 } sync_port;
 131
 132
 133 static int etrax_sync_serial_init(void);
 134 static void initialize_port(int portnbr);
 135 static inline int sync_data_avail(struct sync_port *port);
 136
 137 static int sync_serial_open(struct inode *, struct file*);
 138 static int sync_serial_release(struct inode*, struct file*);
 139 static unsigned int sync_serial_poll(struct file *filp, poll_table *wait);
 140
 141 static int sync_serial_ioctl(struct inode*, struct file*,
 142                              unsigned int cmd, unsigned long arg);
 143 static ssize_t sync_serial_write(struct file * file, const char * buf,
 144                                  size_t count, loff_t *ppos);
 145 static ssize_t sync_serial_read(struct file *file, char *buf,
 146                                 size_t count, loff_t *ppos);
 147
 148 #if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
 149      defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
 150     (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
 151      defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))
 152 #define SYNC_SER_DMA
 153 #endif
 154
 155 static void send_word(sync_port* port);
 156 static void start_dma(struct sync_port *port, const char* data, int count);
 157 static void start_dma_in(sync_port* port);
 158 #ifdef SYNC_SER_DMA
 159 static void tr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
 160 static void rx_interrupt(int irq, void *dev_id, struct pt_regs * regs);
 161 #endif
 162 #if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
 163      !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
 164     (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
 165      !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))
 166 #define SYNC_SER_MANUAL
 167 #endif
 168 #ifdef SYNC_SER_MANUAL
 169 static void manual_interrupt(int irq, void *dev_id, struct pt_regs * regs);
 170 #endif
 171
 172 /* The ports */
 173 static struct sync_port ports[]=
 174 {
 175         {
 176                 .status                = R_SYNC_SERIAL1_STATUS,
 177                 .ctrl_data             = R_SYNC_SERIAL1_CTRL,
 178                 .output_dma_first      = R_DMA_CH8_FIRST,
 179                 .output_dma_cmd        = R_DMA_CH8_CMD,
 180                 .output_dma_clr_irq    = R_DMA_CH8_CLR_INTR,
 181                 .input_dma_first       = R_DMA_CH9_FIRST,
 182                 .input_dma_cmd         = R_DMA_CH9_CMD,
 183                 .input_dma_descr       = R_DMA_CH9_DESCR,
 184                 .input_dma_clr_irq     = R_DMA_CH9_CLR_INTR,
 185                 .data_out              = R_SYNC_SERIAL1_TR_DATA,
 186                 .data_in               = R_SYNC_SERIAL1_REC_DATA,
 187                 .data_avail_bit        = IO_BITNR(R_IRQ_MASK1_RD, ser1_data),
 188                 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready),
 189                 .input_dma_descr_bit   = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr),
 190                 .output_dma_bit        = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop),
 191         },
 192         {
 193                 .status                = R_SYNC_SERIAL3_STATUS,
 194                 .ctrl_data             = R_SYNC_SERIAL3_CTRL,
 195                 .output_dma_first      = R_DMA_CH4_FIRST,
 196                 .output_dma_cmd        = R_DMA_CH4_CMD,
 197                 .output_dma_clr_irq    = R_DMA_CH4_CLR_INTR,
 198                 .input_dma_first       = R_DMA_CH5_FIRST,
 199                 .input_dma_cmd         = R_DMA_CH5_CMD,
 200                 .input_dma_descr       = R_DMA_CH5_DESCR,
 201                 .input_dma_clr_irq     = R_DMA_CH5_CLR_INTR,
 202                 .data_out              = R_SYNC_SERIAL3_TR_DATA,
 203                 .data_in               = R_SYNC_SERIAL3_REC_DATA,
 204                 .data_avail_bit        = IO_BITNR(R_IRQ_MASK1_RD, ser3_data),
 205                 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready),
 206                 .input_dma_descr_bit   = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr),
 207                 .output_dma_bit        = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop),
 208         }
 209 };
 210
 211 /* Register shadows */
 212 static unsigned sync_serial_prescale_shadow = 0;
 213 static unsigned gen_config_ii_shadow = 0;
 214
 215 #define NUMBER_OF_PORTS (sizeof(ports)/sizeof(sync_port))
 216
 217 static struct file_operations sync_serial_fops = {
 218         .owner   = THIS_MODULE,
 219         .write   = sync_serial_write,
 220         .read    = sync_serial_read,
 221         .poll    = sync_serial_poll,
 222         .ioctl   = sync_serial_ioctl,
 223         .open    = sync_serial_open,
 224         .release = sync_serial_release
 225 };
 226
 227 static int __init etrax_sync_serial_init(void)
 228 {
 229         ports[0].enabled = 0;
 230         ports[1].enabled = 0;
 231
 232         if (register_chrdev(SYNC_SERIAL_MAJOR,"sync serial", &sync_serial_fops) <0 )
 233         {
 234                 printk("unable to get major for synchronous serial port\n");
 235                 return -EBUSY;
 236         }
 237
 238         /* Deselect synchronous serial ports */
 239         SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
 240         SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
 241         *R_GEN_CONFIG_II = gen_config_ii_shadow;
 242
 243         /* Initialize Ports */
 244 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
 245         ports[0].enabled = 1;
 246         SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra);
 247         SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
 248 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
 249         ports[0].use_dma = 1;
 250         initialize_port(0);
 251         if(request_irq(24, tr_interrupt, 0, "synchronous serial 1 dma tr", &ports[0]))
 252                  panic("Can't allocate sync serial port 1 IRQ");
 253         if(request_irq(25, rx_interrupt, 0, "synchronous serial 1 dma rx", &ports[0]))
 254                 panic("Can't allocate sync serial port 1 IRQ");
 255         RESET_DMA(8); WAIT_DMA(8);
 256         RESET_DMA(9); WAIT_DMA(9);
 257         *R_DMA_CH8_CLR_INTR = IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
 258           IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
 259         *R_DMA_CH9_CLR_INTR = IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, do) |
 260           IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, do);
 261         *R_IRQ_MASK2_SET =
 262           IO_STATE(R_IRQ_MASK2_SET, dma8_eop, set) |
 263           IO_STATE(R_IRQ_MASK2_SET, dma9_descr, set);
 264         start_dma_in(&ports[0]);
 265 #else
 266         ports[0].use_dma = 0;
 267         initialize_port(0);
 268         if (request_irq(8, manual_interrupt, SA_SHIRQ | SA_INTERRUPT, "synchronous serial manual irq", &ports[0]))
 269                 panic("Can't allocate sync serial manual irq");
 270 #endif
 271 #endif
 272
 273 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
 274         ports[1].enabled = 1;
 275         SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);
 276         SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
 277 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
 278         ports[1].use_dma = 1;
 279         initialize_port(1);
 280         if(request_irq(20, tr_interrupt, 0, "synchronous serial 3 dma tr", &ports[1]))
 281                 panic("Can't allocate sync serial port 3 IRQ");
 282         if(request_irq(21, rx_interrupt, 0, "synchronous serial 3 dma rx", &ports[1]))
 283                 panic("Can't allocate sync serial port 3 IRQ");
 284         RESET_DMA(4); WAIT_DMA(4);
 285         RESET_DMA(5); WAIT_DMA(5);
 286         *R_DMA_CH4_CLR_INTR = IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
 287           IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
 288         *R_DMA_CH5_CLR_INTR = IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, do) |
 289           IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, do);
 290         *R_IRQ_MASK2_SET =
 291           IO_STATE(R_IRQ_MASK2_SET, dma4_eop, set) |
 292           IO_STATE(R_IRQ_MASK2_SET, dma5_descr, set);
 293         start_dma_in(&ports[1]);
 294 #else
 295         ports[1].use_dma = 0;
 296         initialize_port(1);
 297         if (!ports[0].enabled || ports[0].use_dma) /* Port 0 uses dma, we must manual allocate IRQ */
 298         {
 299                 if (request_irq(8, manual_interrupt, SA_SHIRQ | SA_INTERRUPT, "synchronous serial manual irq", &ports[1]))
 300                         panic("Can't allocate sync serial manual irq");
 301         }
 302 #endif
 303 #endif
 304
 305         *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */
 306
 307         /* Set up timing */
 308         *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (
 309           IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
 310           IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
 311           IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
 312           IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
 313           IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
 314           IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate, DEFAULT_FRAME_RATE) |
 315           IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) |
 316           IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
 317
 318         /* Select synchronous ports */
 319         *R_GEN_CONFIG_II = gen_config_ii_shadow;
 320
 321         printk("ETRAX 100LX synchronous serial port driver\n");
 322         return 0;
 323 }
 324
 325 static void __init initialize_port(int portnbr)
 326 {
 327         struct sync_port* port = &ports[portnbr];
 328
 329         DEBUG(printk("Init sync serial port %d\n", portnbr));
 330
 331         port->started = 0;
 332         port->port_nbr = portnbr;
 333         port->busy = 0;
 334         port->cur_in_descr = 0;
 335         port->tr_running = 0;
 336
 337         port->out_count = 0;
 338         port->outp = port->out_buffer;
 339
 340         port->readp = port->in_buffer;
 341         port->writep = port->in_buffer;
 342         port->in_buffer_size = IN_BUFFER_SIZE;
 343         port->inbufchunk = port->in_buffer_size/NUM_IN_DESCR;
 344
 345         init_waitqueue_head(&port->out_wait_q);
 346         init_waitqueue_head(&port->in_wait_q);
 347
 348         port->ctrl_data_shadow =
 349           IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz)   |
 350           IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
 351           IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore)       |
 352           IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
 353           IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal)  |
 354           IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word)    |
 355           IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on)          |
 356           IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal)    |
 357           IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped)   |
 358           IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb)       |
 359           IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable)  |
 360           IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit)  |
 361           IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8)    |
 362           IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8)     |
 363           IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled)  |
 364           IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg)   |
 365           IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
 366           IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
 367           IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal)   |
 368           IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
 369           IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
 370           IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
 371
 372         if (port->use_dma)
 373                 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, dma_enable, on);
 374         else
 375                 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, dma_enable, off);
 376
 377         *port->ctrl_data = port->ctrl_data_shadow;
 378 }
 379
 380 static inline int sync_data_avail(struct sync_port *port)
 381 {
 382         int avail;
 383         unsigned char *start;
 384         unsigned char *end;
 385
 386         start = (unsigned char*)port->readp; /* cast away volatile */
 387         end = (unsigned char*)port->writep;  /* cast away volatile */
 388         /* 0123456789  0123456789
 389          *  -----      -    -----
 390          *  ^rp  ^wp    ^wp ^rp
 391          */
 392
 393         if (end >= start)
 394                 avail = end - start;
 395         else
 396                 avail = port->in_buffer_size - (start - end);
 397         return avail;
 398 }
 399
 400 static inline int sync_data_avail_to_end(struct sync_port *port)
 401 {
 402         int avail;
 403         unsigned char *start;
 404         unsigned char *end;
 405
 406         start = (unsigned char*)port->readp; /* cast away volatile */
 407         end = (unsigned char*)port->writep;  /* cast away volatile */
 408         /* 0123456789  0123456789
 409          *  -----           -----
 410          *  ^rp  ^wp    ^wp ^rp
 411          */
 412
 413         if (end >= start)
 414                 avail = end - start;
 415         else
 416                 avail = port->in_buffer + port->in_buffer_size - start;
 417         return avail;
 418 }
 419
 420
 421 static int sync_serial_open(struct inode *inode, struct file *file)
 422 {
 423         int dev = MINOR(inode->i_rdev);
 424         sync_port* port;
 425         int mode;
 426
 427         DEBUG(printk("Open sync serial port %d\n", dev));
 428
 429         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
 430         {
 431                 DEBUG(printk("Invalid minor %d\n", dev));
 432                 return -ENODEV;
 433         }
 434         port = &ports[dev];
 435         /* Allow open this device twice (assuming one reader and one writer) */
 436         if (port->busy == 2)
 437         {
 438                 DEBUG(printk("Device is busy.. \n"));
 439                 return -EBUSY;
 440         }
 441         port->busy++;
 442         /* Start port if we use it as input */
 443         mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow);
 444         if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) ||
 445             mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) ||
 446             mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) ||
 447             mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) {
 448                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, running);
 449                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, enable);
 450                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, enable);
 451                 port->started = 1;
 452                 *port->ctrl_data = port->ctrl_data_shadow;
 453                 if (!port->use_dma)
 454                         *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
 455                 DEBUG(printk("sser%d rec started\n", dev));
 456         }
 457         return 0;
 458 }
 459
 460 static int sync_serial_release(struct inode *inode, struct file *file)
 461 {
 462         int dev = MINOR(inode->i_rdev);
 463         sync_port* port;
 464
 465         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
 466         {
 467                 DEBUG(printk("Invalid minor %d\n", dev));
 468                 return -ENODEV;
 469         }
 470         port = &ports[dev];
 471         if (port->busy)
 472                 port->busy--;
 473         if (!port->busy)
 474                 *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) |
 475                                     (1 << port->transmitter_ready_bit));
 476
 477         return 0;
 478 }
 479
 480
 481
 482 static unsigned int sync_serial_poll(struct file *file, poll_table *wait)
 483 {
 484         int dev = MINOR(file->f_dentry->d_inode->i_rdev);
 485         unsigned int mask = 0;
 486         sync_port* port;
 487         DEBUGPOLL( static unsigned int prev_mask = 0; );
 488
 489         port = &ports[dev];
 490         poll_wait(file, &port->out_wait_q, wait);
 491         poll_wait(file, &port->in_wait_q, wait);
 492         /* Some room to write */
 493         if (port->out_count < OUT_BUFFER_SIZE)
 494                 mask |=  POLLOUT | POLLWRNORM;
 495         /* At least an inbufchunk of data */
 496         if (sync_data_avail(port) >= port->inbufchunk)
 497                 mask |= POLLIN | POLLRDNORM;
 498
 499         DEBUGPOLL(if (mask != prev_mask)
 500               printk("sync_serial_poll: mask 0x%08X %s %s\n", mask,
 501                      mask&POLLOUT?"POLLOUT":"", mask&POLLIN?"POLLIN":"");
 502               prev_mask = mask;
 503               );
 504         return mask;
 505 }
 506
 507 static int sync_serial_ioctl(struct inode *inode, struct file *file,
 508                   unsigned int cmd, unsigned long arg)
 509 {
 510         int return_val = 0;
 511         unsigned long flags;
 512
 513         int dev = MINOR(file->f_dentry->d_inode->i_rdev);
 514         sync_port* port;
 515
 516         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
 517         {
 518                 DEBUG(printk("Invalid minor %d\n", dev));
 519                 return -1;
 520         }
 521         port = &ports[dev];
 522
 523         save_flags(flags);
 524         cli();
 525         /* Disable port while changing config */
 526         if (dev)
 527         {
 528                 if (port->use_dma) {
 529                         RESET_DMA(4); WAIT_DMA(4);
 530                         *R_DMA_CH4_CLR_INTR = IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
 531                                 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
 532                 }
 533                 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
 534         }
 535         else
 536         {
 537                 if (port->use_dma) {
 538                         RESET_DMA(8); WAIT_DMA(8);
 539                         *R_DMA_CH8_CLR_INTR = IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
 540                                 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
 541                 }
 542                 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
 543         }
 544         *R_GEN_CONFIG_II = gen_config_ii_shadow;
 545         restore_flags(flags);
 546
 547         switch(cmd)
 548         {
 549         case SSP_SPEED:
 550                 if (GET_SPEED(arg) == CODEC)
 551                 {
 552                         if (dev)
 553                                 SETS(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec);
 554                         else
 555                                 SETS(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec);
 556
 557                         SETF(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, prescaler, GET_FREQ(arg));
 558                         SETF(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, frame_rate, GET_FRAME_RATE(arg));
 559                         SETF(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, word_rate, GET_WORD_RATE(arg));
 560                 }
 561                 else
 562                 {
 563                         SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_baud, GET_SPEED(arg));
 564                         if (dev)
 565                                 SETS(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, clk_sel_u3, baudrate);
 566                         else
 567                                 SETS(sync_serial_prescale_shadow, R_SYNC_SERIAL_PRESCALE, clk_sel_u1, baudrate);
 568                 }
 569                 break;
 570         case SSP_MODE:
 571                 if (arg > 5)
 572                         return -EINVAL;
 573                 if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)
 574                         *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit;
 575                 else if (!port->use_dma)
 576                         *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
 577                 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg);
 578                 break;
 579         case SSP_FRAME_SYNC:
 580                 if (arg & NORMAL_SYNC)
 581                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, normal);
 582                 else if (arg & EARLY_SYNC)
 583                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, early);
 584
 585                 if (arg & BIT_SYNC)
 586                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, bit);
 587                 else if (arg & WORD_SYNC)
 588                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, word);
 589                 else if (arg & EXTENDED_SYNC)
 590                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, extended);
 591
 592                 if (arg & SYNC_ON)
 593                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
 594                 else if (arg & SYNC_OFF)
 595                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, off);
 596
 597                 if (arg & WORD_SIZE_8)
 598                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size8bit);
 599                 else if (arg & WORD_SIZE_12)
 600                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size12bit);
 601                 else if (arg & WORD_SIZE_16)
 602                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size16bit);
 603                 else if (arg & WORD_SIZE_24)
 604                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size24bit);
 605                 else if (arg & WORD_SIZE_32)
 606                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size32bit);
 607
 608                 if (arg & BIT_ORDER_MSB)
 609                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, msb);
 610                 else if (arg & BIT_ORDER_LSB)
 611                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, lsb);
 612
 613                 if (arg & FLOW_CONTROL_ENABLE)
 614                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled);
 615                 else if (arg & FLOW_CONTROL_DISABLE)
 616                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, disabled);
 617
 618                 if (arg & CLOCK_NOT_GATED)
 619                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_mode, normal);
 620                 else if (arg & CLOCK_GATED)
 621                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_mode, gated);
 622
 623                 break;
 624         case SSP_IPOLARITY:
 625                 /* NOTE!! negedge is considered NORMAL */
 626                 if (arg & CLOCK_NORMAL)
 627                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_polarity, neg);
 628                 else if (arg & CLOCK_INVERT)
 629                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_polarity, pos);
 630
 631                 if (arg & FRAME_NORMAL)
 632                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_polarity, normal);
 633                 else if (arg & FRAME_INVERT)
 634                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_polarity, inverted);
 635
 636                 if (arg & STATUS_NORMAL)
 637                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, status_polarity, normal);
 638                 else if (arg & STATUS_INVERT)
 639                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, status_polarity, inverted);
 640                 break;
 641         case SSP_OPOLARITY:
 642                 if (arg & CLOCK_NORMAL)
 643                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_driver, normal);
 644                 else if (arg & CLOCK_INVERT)
 645                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_driver, inverted);
 646
 647                 if (arg & FRAME_NORMAL)
 648                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_driver, normal);
 649                 else if (arg & FRAME_INVERT)
 650                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_driver, inverted);
 651
 652                 if (arg & STATUS_NORMAL)
 653                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, status_driver, normal);
 654                 else if (arg & STATUS_INVERT)
 655                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, status_driver, inverted);
 656                 break;
 657         case SSP_SPI:
 658                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, disabled);
 659                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, msb);
 660                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, size8bit);
 661                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
 662                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, word);
 663                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, normal);
 664                 if (arg & SPI_SLAVE)
 665                 {
 666                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_polarity, inverted);
 667                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_polarity, neg);
 668                         SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, SLAVE_INPUT);
 669                 }
 670                 else
 671                 {
 672                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, frame_driver, inverted);
 673                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_driver, inverted);
 674                         SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, MASTER_OUTPUT);
 675                 }
 676                 break;
 677         case SSP_INBUFCHUNK:
 678                 if (arg > port->in_buffer_size/NUM_IN_DESCR)
 679                         return -EINVAL;
 680                 port->inbufchunk = arg;
 681                 /* Make sure in_buffer_size is a multiple of inbufchunk */
 682                 port->in_buffer_size = (port->in_buffer_size/port->inbufchunk) * port->inbufchunk;
 683                 DEBUG(printk("inbufchunk %i in_buffer_size: %i\n", port->inbufchunk, port->in_buffer_size));
 684                 if (port->use_dma) {
 685                         if (port->port_nbr == 0) {
 686                                 RESET_DMA(9);
 687                                 WAIT_DMA(9);
 688                         } else {
 689                                 RESET_DMA(5);
 690                                 WAIT_DMA(5);
 691                         }
 692                         start_dma_in(port);
 693                 }
 694                 break;
 695         default:
 696                 return_val = -1;
 697         }
 698         /* Make sure we write the config without interruption */
 699         save_flags(flags);
 700         cli();
 701         /* Set config and enable port */
 702         *port->ctrl_data = port->ctrl_data_shadow;
 703         nop(); nop(); nop(); nop();
 704         *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow;
 705         nop(); nop(); nop(); nop();
 706         if (dev)
 707                 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
 708         else
 709                 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
 710
 711         *R_GEN_CONFIG_II = gen_config_ii_shadow;
 712         restore_flags(flags);
 713         return return_val;
 714 }
 715
 716
 717 static ssize_t sync_serial_write(struct file * file, const char * buf,
 718                                  size_t count, loff_t *ppos)
 719 {
 720         int dev = MINOR(file->f_dentry->d_inode->i_rdev);
 721         DECLARE_WAITQUEUE(wait, current);
 722         sync_port *port;
 723         unsigned long flags;
 724         unsigned long c, c1;
 725         unsigned long free_outp;
 726         unsigned long outp;
 727         unsigned long out_buffer;
 728
 729         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
 730         {
 731                 DEBUG(printk("Invalid minor %d\n", dev));
 732                 return -ENODEV;
 733         }
 734         port = &ports[dev];
 735
 736         DEBUGWRITE(printk("W d%d c %lu (%d/%d)\n", port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
 737         /* Space to end of buffer */
 738         /*
 739          * out_buffer <c1>012345<-   c    ->OUT_BUFFER_SIZE
 740          *            outp^    +out_count
 741                                 ^free_outp
 742          * out_buffer 45<-     c      ->0123OUT_BUFFER_SIZE
 743          *             +out_count   outp^
 744          *              free_outp
 745          *
 746          */
 747
 748         /* Read variables that may be updated by interrupts */
 749         save_flags(flags);
 750         cli();
 751         count = count > OUT_BUFFER_SIZE - port->out_count ? OUT_BUFFER_SIZE  - port->out_count : count;
 752         outp = (unsigned long)port->outp;
 753         free_outp = outp + port->out_count;
 754         restore_flags(flags);
 755         out_buffer = (unsigned long)port->out_buffer;
 756
 757         /* Find out where and how much to write */
 758         if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
 759                 free_outp -= OUT_BUFFER_SIZE;
 760         if (free_outp >= outp)
 761                 c = out_buffer + OUT_BUFFER_SIZE - free_outp;
 762         else
 763                 c = outp - free_outp;
 764         if (c > count)
 765                 c = count;
 766
 767 //      DEBUGWRITE(printk("w op %08lX fop %08lX c %lu\n", outp, free_outp, c));
 768         if (copy_from_user((void*)free_outp, buf, c))
 769                 return -EFAULT;
 770
 771         if (c != count) {
 772                 buf += c;
 773                 c1 = count - c;
 774                 DEBUGWRITE(printk("w2 fi %lu c %lu c1 %lu\n", free_outp-out_buffer, c, c1));
 775                 if (copy_from_user((void*)out_buffer, buf, c1))
 776                         return -EFAULT;
 777         }
 778         save_flags(flags);
 779         cli();
 780         port->out_count += count;
 781         restore_flags(flags);
 782
 783         /* Make sure transmitter/receiver is running */
 784         if (!port->started)
 785         {
 786                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, running);
 787                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, enable);
 788                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, enable);
 789                 port->started = 1;
 790         }
 791
 792         *port->ctrl_data = port->ctrl_data_shadow;
 793
 794         if (file->f_flags & O_NONBLOCK) {
 795                 save_flags(flags);
 796                 cli();
 797                 if (!port->tr_running) {
 798                         if (!port->use_dma) {
 799                                 /* Start sender by writing data */
 800                                 send_word(port);
 801                                 /* and enable transmitter ready IRQ */
 802                                 *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit;
 803                         } else {
 804                                 start_dma(port, (unsigned char* volatile )port->outp, c);
 805                         }
 806                 }
 807                 restore_flags(flags);
 808                 DEBUGWRITE(printk("w d%d c %lu NB\n",
 809                                   port->port_nbr, count));
 810                 return count;
 811         }
 812
 813         /* Sleep until all sent */
 814
 815         add_wait_queue(&port->out_wait_q, &wait);
 816         set_current_state(TASK_INTERRUPTIBLE);
 817         save_flags(flags);
 818         cli();
 819         if (!port->tr_running) {
 820                 if (!port->use_dma) {
 821                         /* Start sender by writing data */
 822                         send_word(port);
 823                         /* and enable transmitter ready IRQ */
 824                         *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit;
 825                 } else {
 826                         start_dma(port, port->outp, c);
 827                 }
 828         }
 829         restore_flags(flags);
 830         schedule();
 831         set_current_state(TASK_RUNNING);
 832         remove_wait_queue(&port->out_wait_q, &wait);
 833         if (signal_pending(current))
 834         {
 835                 return -EINTR;
 836         }
 837         DEBUGWRITE(printk("w d%d c %lu\n", port->port_nbr, count));
 838         return count;
 839 }
 840
 841 static ssize_t sync_serial_read(struct file * file, char * buf,
 842                                 size_t count, loff_t *ppos)
 843 {
 844         int dev = MINOR(file->f_dentry->d_inode->i_rdev);
 845         int avail;
 846         sync_port *port;
 847         unsigned char* start;
 848         unsigned char* end;
 849         unsigned long flags;
 850
 851         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
 852         {
 853                 DEBUG(printk("Invalid minor %d\n", dev));
 854                 return -ENODEV;
 855         }
 856         port = &ports[dev];
 857
 858         DEBUGREAD(printk("R%d c %d ri %lu wi %lu /%lu\n", dev, count, port->readp - port->in_buffer, port->writep - port->in_buffer, port->in_buffer_size));
 859
 860         if (!port->started)
 861         {
 862                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, running);
 863                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, enable);
 864                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, enable);
 865                 port->started = 1;
 866         }
 867         *port->ctrl_data = port->ctrl_data_shadow;
 868
 869
 870         /* Calculate number of available bytes */
 871         /* Save pointers to avoid that they are modified by interrupt */
 872         save_flags(flags);
 873         cli();
 874         start = (unsigned char*)port->readp; /* cast away volatile */
 875         end = (unsigned char*)port->writep;  /* cast away volatile */
 876         restore_flags(flags);
 877         while (start == end) /* No data */
 878         {
 879                 if (file->f_flags & O_NONBLOCK)
 880                         return -EAGAIN;
 881                 interruptible_sleep_on(&port->in_wait_q);
 882                 if (signal_pending(current))
 883                 {
 884                         return -EINTR;
 885                 }
 886                 save_flags(flags);
 887                 cli();
 888                 start = (unsigned char*)port->readp; /* cast away volatile */
 889                 end = (unsigned char*)port->writep;  /* cast away volatile */
 890                 restore_flags(flags);
 891         }
 892
 893         /* Lazy read, never return wrapped data. */
 894         if (end > start)
 895                 avail = end - start;
 896         else
 897                 avail = port->in_buffer + port->in_buffer_size - start;
 898
 899         count = count > avail ? avail : count;
 900         if (copy_to_user(buf, start, count))
 901                 return -EFAULT;
 902
 903         /* Disable interrupts while updating readp */
 904         save_flags(flags);
 905         cli();
 906         port->readp += count;
 907         if (port->readp >= port->in_buffer + port->in_buffer_size) /* Wrap? */
 908                 port->readp = port->in_buffer;
 909         restore_flags(flags);
 910         DEBUGREAD(printk("r %d\n", count));
 911         return count;
 912 }
 913
 914 static void send_word(sync_port* port)
 915 {
 916         switch(IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize, port->ctrl_data_shadow))
 917         {
 918          case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
 919                  port->out_count--;
 920                  *port->data_out = *port->outp++;
 921                  if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
 922                          port->outp = port->out_buffer;
 923                  break;
 924         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
 925         {
 926                 int data = (*port->outp++) << 8;
 927                 data |= *port->outp++;
 928                 port->out_count-=2;
 929                 *port->data_out = data;
 930                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
 931                         port->outp = port->out_buffer;
 932         }
 933         break;
 934         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
 935                 port->out_count-=2;
 936                 *port->data_out = *(unsigned short *)port->outp;
 937                 port->outp+=2;
 938                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
 939                         port->outp = port->out_buffer;
 940                 break;
 941         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
 942                 port->out_count-=3;
 943                 *port->data_out = *(unsigned int *)port->outp;
 944                 port->outp+=3;
 945                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
 946                         port->outp = port->out_buffer;
 947                 break;
 948         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
 949                 port->out_count-=4;
 950                 *port->data_out = *(unsigned int *)port->outp;
 951                 port->outp+=4;
 952                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
 953                         port->outp = port->out_buffer;
 954                 break;
 955         }
 956 }
 957
 958
 959 static void start_dma(struct sync_port* port, const char* data, int count)
 960 {
 961         port->tr_running = 1;
 962         port->out_descr.hw_len = 0;
 963         port->out_descr.next = 0;
 964         port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */
 965         port->out_descr.sw_len = count;
 966         port->out_descr.buf = virt_to_phys((char*)data);
 967         port->out_descr.status = 0;
 968
 969         *port->output_dma_first = virt_to_phys(&port->out_descr);
 970         *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
 971         DEBUGTXINT(printk("dma %08lX c %d\n", (unsigned long)data, count));
 972 }
 973
 974 static void start_dma_in(sync_port* port)
 975 {
 976         int i;
 977         unsigned long buf;
 978         port->cur_in_descr = 0;
 979         port->writep = port->in_buffer;
 980
 981         if (port->writep > port->in_buffer + port->in_buffer_size)
 982         {
 983                 panic("Offset too large in sync serial driver\n");
 984                 return;
 985         }
 986         buf = virt_to_phys(port->in_buffer);
 987         for (i = 0; i < NUM_IN_DESCR; i++) {
 988                 port->in_descr[i].sw_len = port->inbufchunk;
 989                 port->in_descr[i].ctrl = d_int;
 990                 port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]);
 991                 port->in_descr[i].buf = buf;
 992                 port->in_descr[i].hw_len = 0;
 993                 port->in_descr[i].status = 0;
 994                 port->in_descr[i].fifo_len = 0;
 995                 buf += port->inbufchunk;
 996                 prepare_rx_descriptor(&port->in_descr[i]);
 997         }
 998         /* Link the last descriptor to the first */
 999         port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]);
1000         *port->input_dma_first = virt_to_phys(&port->in_descr[(int)port->cur_in_descr]);
1001         *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1002 }
1003
1004 #ifdef SYNC_SER_DMA
1005 static void tr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1006 {
1007         unsigned long ireg = *R_IRQ_MASK2_RD;
1008         int i;
1009         struct etrax_dma_descr *descr;
1010         unsigned int sentl;
1011
1012
1013         for (i = 0; i < NUMBER_OF_PORTS; i++)
1014         {
1015                 sync_port *port = &ports[i];
1016                 if (!port->enabled  || !port->use_dma )
1017                         continue;
1018
1019                 if (ireg & (1 << port->output_dma_bit)) /* IRQ active for the port? */
1020                 {
1021                         /* Clear IRQ */
1022                         *port->output_dma_clr_irq =
1023                           IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
1024                           IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
1025
1026                         descr = &port->out_descr;
1027                         if (!(descr->status & d_stop)) {
1028                                 sentl = descr->sw_len;
1029                         } else
1030                                 /* otherwise we find the amount of data sent here */
1031                                 sentl = descr->hw_len;
1032                         port->out_count -= sentl;
1033                         port->outp += sentl;
1034                         if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1035                                 port->outp = port->out_buffer;
1036                         if (port->out_count)  {
1037                                 int c;
1038                                 c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
1039                                 if (c > port->out_count)
1040                                         c = port->out_count;
1041                                 DEBUGTXINT(printk("tx_int DMAWRITE %i %i\n", sentl, c));
1042                                 start_dma(port, port->outp, c);
1043                         } else  {
1044                                 DEBUGTXINT(printk("tx_int DMA stop %i\n", sentl));
1045                                 port->tr_running = 0;
1046                         }
1047                         wake_up_interruptible(&port->out_wait_q); /* wake up the waiting process */
1048                 }
1049         }
1050 } /* tr_interrupt */
1051
1052 static void rx_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1053 {
1054         unsigned long ireg = *R_IRQ_MASK2_RD;
1055         int i;
1056
1057         for (i = 0; i < NUMBER_OF_PORTS; i++)
1058         {
1059                 sync_port *port = &ports[i];
1060
1061                 if (!port->enabled || !port->use_dma )
1062                         continue;
1063
1064                 if (ireg & (1 << port->input_dma_descr_bit)) /* Descriptor interrupt */
1065                 {
1066                         struct etrax_dma_descr *descr;
1067                         unsigned recvl;
1068                         unsigned long oldbuf, buf;
1069
1070                         /* DMA has reached end of descriptor */
1071                         *port->input_dma_clr_irq =
1072                           IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
1073
1074                         descr = &port->in_descr[(int)port->cur_in_descr];
1075                         if (descr == phys_to_virt(*port->input_dma_descr))
1076                                 printk("sser: desc = *input_dma_descr\n");
1077
1078                         if (!(descr->status & d_eop)) {
1079                                 recvl = descr->sw_len;
1080                         } else {
1081                                 /* otherwise we find the amount of data received here */
1082                                 recvl = descr->hw_len;
1083                         }
1084                         port->writep += recvl;
1085                         if (port->writep >= port->in_buffer+ port->in_buffer_size)
1086                                 port->writep = port->in_buffer;
1087                         descr->sw_len = port->inbufchunk;
1088                         /* Reset the status information */
1089                         descr->status = 0;
1090                         /* Change the buf pointer to new position */
1091                         oldbuf = descr->buf;
1092
1093                         descr->buf += NUM_IN_DESCR * port->inbufchunk;
1094                         buf = virt_to_phys(port->in_buffer);
1095                         if (descr->buf >= buf + port->in_buffer_size)
1096                                 descr->buf -= port->in_buffer_size;
1097                         DEBUGRXINT(printk("rx_int descr %i %X recvl: %i writep %lu obuf %lu %08lX buf 0x%08lX\n", port->cur_in_descr, (unsigned long) (*port->input_dma_descr), recvl, (unsigned long)(port->writep - port->in_buffer), oldbuf, oldbuf, (unsigned long)descr->buf));
1098                         if (++port->cur_in_descr == NUM_IN_DESCR)
1099                                 port->cur_in_descr = 0;
1100
1101                         wake_up_interruptible(&port->in_wait_q); /* wake up the waiting process */
1102                 }
1103         }
1104 } /* rx_interrupt */
1105 #endif /* SYNC_SER_DMA */
1106
1107 #ifdef SYNC_SER_MANUAL
1108 static void manual_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1109 {
1110         int i;
1111
1112         for (i = 0; i < NUMBER_OF_PORTS; i++)
1113         {
1114                 sync_port* port = &ports[i];
1115
1116                 if (!port->enabled || port->use_dma)
1117                 {
1118                         continue;
1119                 }
1120
1121                 if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit))      /* Data received? */
1122                 {
1123                         /* Read data */
1124                         switch(port->ctrl_data_shadow & IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize))
1125                         {
1126                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
1127                                 *port->writep++ = *(volatile char *)port->data_in;
1128                                 break;
1129                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
1130                         {
1131                                 int data = *(unsigned short *)port->data_in;
1132                                 *port->writep = (data & 0x0ff0) >> 4;
1133                                 *(port->writep + 1) = data & 0x0f;
1134                                 port->writep+=2;
1135                         }
1136                         break;
1137                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1138                                 *(unsigned short*)port->writep = *(volatile unsigned short *)port->data_in;
1139                                 port->writep+=2;
1140                                 break;
1141                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1142                                 *(unsigned int*)port->writep = *port->data_in;
1143                                 port->writep+=3;
1144                                 break;
1145                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
1146                                 *(unsigned int*)port->writep = *port->data_in;
1147                                 port->writep+=4;
1148                                 break;
1149                         }
1150
1151                         if (port->writep >= port->in_buffer + port->in_buffer_size) /* Wrap? */
1152                                 port->writep = port->in_buffer;
1153                         if (port->writep == port->readp) {
1154                                 /* receive buffer overrun, discard oldest data
1155                                  */
1156                                 port->readp++;
1157                                 if (port->readp >= port->in_buffer + port->in_buffer_size) /* Wrap? */
1158                                         port->readp = port->in_buffer;
1159                         }
1160                         if (sync_data_avail(port) >= port->inbufchunk)
1161                                 wake_up_interruptible(&port->in_wait_q); /* Wake up application */
1162                 }
1163
1164                 if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) /* Transmitter ready? */
1165                 {
1166                         if (port->out_count > 0) /* More data to send */
1167                                 send_word(port);
1168                         else /* transmission finished */
1169                         {
1170                                 *R_IRQ_MASK1_CLR = 1 << port->transmitter_ready_bit; /* Turn off IRQ */
1171                                 wake_up_interruptible(&port->out_wait_q); /* Wake up application */
1172                         }
1173                 }
1174         }
1175 }
1176 #endif
1177
1178 module_init(etrax_sync_serial_init);