2 * Low-Level PCI Support for PC -- Routing of Interrupts
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
18 #include <asm/io_apic.h>
22 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
23 #define PIRQ_VERSION 0x0100
25 int broken_hp_bios_irq9;
26 int acer_tm360_irqrouting;
28 static struct irq_routing_table *pirq_table;
31 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
32 * Avoid using: 13, 14 and 15 (FP error and IDE).
33 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
35 unsigned int pcibios_irq_mask = 0xfff8;
37 static int pirq_penalty[16] = {
38 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
39 0, 0, 0, 0, 1000, 100000, 100000, 100000
45 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
46 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
49 struct irq_router_handler {
51 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
55 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
58 static struct irq_routing_table * __init pirq_find_routing_table(void)
61 struct irq_routing_table *rt;
65 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
66 rt = (struct irq_routing_table *) addr;
67 if (rt->signature != PIRQ_SIGNATURE ||
68 rt->version != PIRQ_VERSION ||
70 rt->size < sizeof(struct irq_routing_table))
73 for(i=0; i<rt->size; i++)
76 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
84 * If we have a IRQ routing table, use it to search for peer host
85 * bridges. It's a gross hack, but since there are no other known
86 * ways how to get a list of buses, we have to go this way.
89 static void __init pirq_peer_trick(void)
91 struct irq_routing_table *rt = pirq_table;
96 memset(busmap, 0, sizeof(busmap));
97 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
102 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
104 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
112 * It might be a secondary bus, but in this case its parent is already
113 * known (ascending bus order) and therefore pci_scan_bus returns immediately.
115 if (busmap[i] && pci_scan_bus(i, pci_root_bus->ops, NULL))
116 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
117 pcibios_last_bus = -1;
121 * Code for querying and setting of IRQ routes on various interrupt routers.
124 void eisa_set_level_irq(unsigned int irq)
126 unsigned char mask = 1 << (irq & 7);
127 unsigned int port = 0x4d0 + (irq >> 3);
128 unsigned char val = inb(port);
132 outb(val | mask, port);
137 * Common IRQ routing practice: nybbles in config space,
138 * offset by some magic constant.
140 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
143 unsigned reg = offset + (nr >> 1);
145 pci_read_config_byte(router, reg, &x);
146 return (nr & 1) ? (x >> 4) : (x & 0xf);
149 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
152 unsigned reg = offset + (nr >> 1);
154 pci_read_config_byte(router, reg, &x);
155 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
156 pci_write_config_byte(router, reg, x);
160 * ALI pirq entries are damn ugly, and completely undocumented.
161 * This has been figured out from pirq tables, and it's not a pretty
164 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
166 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
168 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
171 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
173 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
174 unsigned int val = irqmap[irq];
177 write_config_nybble(router, 0x48, pirq-1, val);
184 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
185 * just a pointer to the config space.
187 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
191 pci_read_config_byte(router, pirq, &x);
192 return (x < 16) ? x : 0;
195 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
197 pci_write_config_byte(router, pirq, irq);
202 * The VIA pirq rules are nibble-based, like ALI,
203 * but without the ugly irq number munging.
204 * However, PIRQD is in the upper instead of lower nibble.
206 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
208 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
211 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
213 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
218 * The VIA pirq rules are nibble-based, like ALI,
219 * but without the ugly irq number munging.
220 * However, for 82C586, nibble map is different .
222 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
224 static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
225 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
228 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
230 static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
231 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
236 * ITE 8330G pirq rules are nibble-based
237 * FIXME: pirqmap may be { 1, 0, 3, 2 },
238 * 2+3 are both mapped to irq 9 on my system
240 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
242 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
243 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
246 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
248 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
249 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
254 * OPTI: high four bits are nibble pointer..
255 * I wonder what the low bits do?
257 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
259 return read_config_nybble(router, 0xb8, pirq >> 4);
262 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
264 write_config_nybble(router, 0xb8, pirq >> 4, irq);
269 * OPTI Viper-M/N+: Bit field with 3 bits per entry.
270 * Due to the lack of a specification the information about this chipset
271 * was taken from the NetBSD source code.
273 static int pirq_viper_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
275 static const int viper_irq_decode[] = { 0, 5, 9, 10, 11, 12, 14, 15 };
278 pci_read_config_dword(router, 0x40, &irq);
282 return viper_irq_decode[irq];
285 static int pirq_viper_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
287 static const int viper_irq_map[] = { -1, -1, -1, -1, -1, 1, -1, -1, -1, 2, 3, 4, 5, -1, 6, 7 };
288 int newval = viper_irq_map[irq];
290 u32 mask = 7 << (3*(pirq-1));
292 mask |= 0x10000UL << (pirq-1); /* edge triggered */
298 pci_read_config_dword(router, 0x40, &val);
300 val |= newval << (3*(pirq-1));
301 pci_write_config_dword(router, 0x40, val);
307 * Cyrix: nibble offset 0x5C
309 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
311 return read_config_nybble(router, 0x5C, (pirq-1)^1);
314 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
316 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
321 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
322 * We have to deal with the following issues here:
323 * - vendors have different ideas about the meaning of link values
324 * - some onboard devices (integrated in the chipset) have special
325 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
326 * - different revision of the router have a different layout for
327 * the routing registers, particularly for the onchip devices
329 * For all routing registers the common thing is we have one byte
330 * per routeable link which is defined as:
331 * bit 7 IRQ mapping enabled (0) or disabled (1)
332 * bits [6:4] reserved (sometimes used for onchip devices)
333 * bits [3:0] IRQ to map to
334 * allowed: 3-7, 9-12, 14-15
335 * reserved: 0, 1, 2, 8, 13
337 * The config-space registers located at 0x41/0x42/0x43/0x44 are
338 * always used to route the normal PCI INT A/B/C/D respectively.
339 * Apparently there are systems implementing PCI routing table using
340 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
341 * We try our best to handle both link mappings.
343 * Currently (2003-05-21) it appears most SiS chipsets follow the
344 * definition of routing registers from the SiS-5595 southbridge.
345 * According to the SiS 5595 datasheets the revision id's of the
346 * router (ISA-bridge) should be 0x01 or 0xb0.
348 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
349 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
350 * They seem to work with the current routing code. However there is
351 * some concern because of the two USB-OHCI HCs (original SiS 5595
352 * had only one). YMMV.
354 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
357 * bits [6:5] must be written 01
358 * bit 4 channel-select primary (0), secondary (1)
361 * bit 6 OHCI function disabled (0), enabled (1)
363 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
365 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
367 * We support USBIRQ (in addition to INTA-INTD) and keep the
368 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
370 * Currently the only reported exception is the new SiS 65x chipset
371 * which includes the SiS 69x southbridge. Here we have the 85C503
372 * router revision 0x04 and there are changes in the register layout
373 * mostly related to the different USB HCs with USB 2.0 support.
375 * Onchip routing for router rev-id 0x04 (try-and-error observation)
377 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
378 * bit 6-4 are probably unused, not like 5595
381 #define PIRQ_SIS_IRQ_MASK 0x0f
382 #define PIRQ_SIS_IRQ_DISABLE 0x80
383 #define PIRQ_SIS_USB_ENABLE 0x40
384 #define PIRQ_SIS_DETECT_REGISTER 0x40
388 * 0 for PCI INTA-INTD
389 * 0 or enable bit mask to check or set for onchip functions
391 static inline int pirq_sis5595_onchip(int pirq, int *reg)
410 ret = PIRQ_SIS_USB_ENABLE; /* documented for 5595 */
416 printk(KERN_INFO "SiS pirq: IDE/ACPI/DAQ mapping not implemented: (%u)\n",
420 printk(KERN_INFO "SiS router unknown request: (%u)\n",
429 * 0 for PCI INTA-INTD
430 * 0 or enable bit mask to check or set for onchip functions
432 static inline int pirq_sis96x_onchip(int pirq, int *reg)
455 printk(KERN_INFO "SiS router unknown request: (%u)\n",
463 static int pirq_sis5595_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
468 check = pirq_sis5595_onchip(pirq, ®);
472 pci_read_config_byte(router, reg, &x);
473 if (check != 0 && !(x & check))
476 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
479 static int pirq_sis96x_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
484 check = pirq_sis96x_onchip(pirq, ®);
488 pci_read_config_byte(router, reg, &x);
489 if (check != 0 && !(x & check))
492 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
495 static int pirq_sis5595_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
500 set = pirq_sis5595_onchip(pirq, ®);
504 x = (irq & PIRQ_SIS_IRQ_MASK);
506 x = PIRQ_SIS_IRQ_DISABLE;
510 pci_write_config_byte(router, reg, x);
515 static int pirq_sis96x_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
520 set = pirq_sis96x_onchip(pirq, ®);
524 x = (irq & PIRQ_SIS_IRQ_MASK);
526 x = PIRQ_SIS_IRQ_DISABLE;
530 pci_write_config_byte(router, reg, x);
537 * VLSI: nibble offset 0x74 - educated guess due to routing table and
538 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
539 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
540 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
541 * for the busbridge to the docking station.
544 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
547 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
550 return read_config_nybble(router, 0x74, pirq-1);
553 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
556 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
559 write_config_nybble(router, 0x74, pirq-1, irq);
564 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
565 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
566 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
567 * register is a straight binary coding of desired PIC IRQ (low nibble).
569 * The 'link' value in the PIRQ table is already in the correct format
570 * for the Index register. There are some special index values:
571 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
572 * and 0x03 for SMBus.
574 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
577 return inb(0xc01) & 0xf;
580 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
587 /* Support for AMD756 PCI IRQ Routing
588 * Jhon H. Caicedo <jhcaiced@osso.org.co>
589 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
590 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
591 * The AMD756 pirq rules are nibble-based
592 * offset 0x56 0-3 PIRQA 4-7 PIRQB
593 * offset 0x57 0-3 PIRQC 4-7 PIRQD
595 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
601 irq = read_config_nybble(router, 0x56, pirq - 1);
603 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
604 dev->vendor, dev->device, pirq, irq);
608 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
610 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
611 dev->vendor, dev->device, pirq, irq);
614 write_config_nybble(router, 0x56, pirq - 1, irq);
619 #ifdef CONFIG_PCI_BIOS
621 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
623 struct pci_dev *bridge;
624 int pin = pci_get_interrupt_pin(dev, &bridge);
625 return pcibios_set_irq_routing(bridge, pin, irq);
631 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
633 /* We must not touch 440GX even if we have tables. 440GX has
634 different IRQ routing weirdness */
635 if(pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0, NULL) ||
636 pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2, NULL))
640 case PCI_DEVICE_ID_INTEL_82371FB_0:
641 case PCI_DEVICE_ID_INTEL_82371SB_0:
642 case PCI_DEVICE_ID_INTEL_82371AB_0:
643 case PCI_DEVICE_ID_INTEL_82371MX:
644 case PCI_DEVICE_ID_INTEL_82443MX_0:
645 case PCI_DEVICE_ID_INTEL_82801AA_0:
646 case PCI_DEVICE_ID_INTEL_82801AB_0:
647 case PCI_DEVICE_ID_INTEL_82801BA_0:
648 case PCI_DEVICE_ID_INTEL_82801BA_10:
649 case PCI_DEVICE_ID_INTEL_82801CA_0:
650 case PCI_DEVICE_ID_INTEL_82801CA_12:
651 case PCI_DEVICE_ID_INTEL_82801DB_0:
652 case PCI_DEVICE_ID_INTEL_82801E_0:
653 case PCI_DEVICE_ID_INTEL_82801EB_0:
654 case PCI_DEVICE_ID_INTEL_ESB_0:
655 case PCI_DEVICE_ID_INTEL_ICH6_0:
656 r->name = "PIIX/ICH";
657 r->get = pirq_piix_get;
658 r->set = pirq_piix_set;
664 static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
666 /* FIXME: We should move some of the quirk fixup stuff here */
669 * work arounds for some buggy BIOSes
671 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
672 switch(router->device)
674 case PCI_DEVICE_ID_VIA_82C686:
676 * Asus k7m bios wrongly reports 82C686A
679 device = PCI_DEVICE_ID_VIA_82C686;
681 case PCI_DEVICE_ID_VIA_8235:
683 * Asus a7v-x bios wrongly reports 8235
686 device = PCI_DEVICE_ID_VIA_8235;
693 case PCI_DEVICE_ID_VIA_82C586_0:
695 r->get = pirq_via586_get;
696 r->set = pirq_via586_set;
698 case PCI_DEVICE_ID_VIA_82C596:
699 case PCI_DEVICE_ID_VIA_82C686:
700 case PCI_DEVICE_ID_VIA_8231:
701 case PCI_DEVICE_ID_VIA_8235:
702 /* FIXME: add new ones for 8233/5 */
704 r->get = pirq_via_get;
705 r->set = pirq_via_set;
711 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
715 case PCI_DEVICE_ID_VLSI_82C534:
716 r->name = "VLSI 82C534";
717 r->get = pirq_vlsi_get;
718 r->set = pirq_vlsi_set;
725 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
729 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
730 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
731 r->name = "ServerWorks";
732 r->get = pirq_serverworks_get;
733 r->set = pirq_serverworks_set;
739 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
744 if (device != PCI_DEVICE_ID_SI_503)
748 * In case of SiS south bridge, we need to detect the two
749 * kinds of routing tables we have seen so far (5595 and 96x).
750 * Since the maintain the same device ID, we need to do poke
751 * the PCI configuration space to find the router type we are
756 * Factoid: writing bit6 of register 0x40 of the router config space
757 * will make the SB to show up 0x096x inside the device id. Note,
758 * we need to restore register 0x40 after the device id poke.
761 pci_read_config_byte(router, PIRQ_SIS_DETECT_REGISTER, ®);
762 pci_write_config_byte(router, PIRQ_SIS_DETECT_REGISTER, reg | (1 << 6));
763 pci_read_config_word(router, PCI_DEVICE_ID, &devid);
764 pci_write_config_byte(router, PIRQ_SIS_DETECT_REGISTER, reg);
766 if ((devid & 0xfff0) == 0x0960) {
768 r->get = pirq_sis96x_get;
769 r->set = pirq_sis96x_set;
770 DBG("PCI: Detecting SiS router at %02x:%02x : SiS096x detected\n",
771 rt->rtr_bus, rt->rtr_devfn);
774 r->get = pirq_sis5595_get;
775 r->set = pirq_sis5595_set;
776 DBG("PCI: Detecting SiS router at %02x:%02x : SiS5595 detected\n",
777 rt->rtr_bus, rt->rtr_devfn);
782 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
786 case PCI_DEVICE_ID_CYRIX_5520:
788 r->get = pirq_cyrix_get;
789 r->set = pirq_cyrix_set;
795 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
799 case PCI_DEVICE_ID_OPTI_82C700:
801 r->get = pirq_opti_get;
802 r->set = pirq_opti_set;
804 case PCI_DEVICE_ID_OPTI_82C558:
805 r->name = "OPTI VIPER";
806 r->get = pirq_viper_get;
807 r->set = pirq_viper_set;
815 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
819 case PCI_DEVICE_ID_ITE_IT8330G_0:
821 r->get = pirq_ite_get;
822 r->set = pirq_ite_set;
828 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
832 case PCI_DEVICE_ID_AL_M1533:
834 r->get = pirq_ali_get;
835 r->set = pirq_ali_set;
837 /* Should add 156x some day */
842 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
846 case PCI_DEVICE_ID_AMD_VIPER_740B:
849 case PCI_DEVICE_ID_AMD_VIPER_7413:
852 case PCI_DEVICE_ID_AMD_VIPER_7443:
858 r->get = pirq_amd756_get;
859 r->set = pirq_amd756_set;
863 static __initdata struct irq_router_handler pirq_routers[] = {
864 { PCI_VENDOR_ID_INTEL, intel_router_probe },
865 { PCI_VENDOR_ID_AL, ali_router_probe },
866 { PCI_VENDOR_ID_ITE, ite_router_probe },
867 { PCI_VENDOR_ID_VIA, via_router_probe },
868 { PCI_VENDOR_ID_OPTI, opti_router_probe },
869 { PCI_VENDOR_ID_SI, sis_router_probe },
870 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
871 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
872 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
873 { PCI_VENDOR_ID_AMD, amd_router_probe },
874 /* Someone with docs needs to add the ATI Radeon IGP */
877 static struct irq_router pirq_router;
878 static struct pci_dev *pirq_router_dev;
881 * FIXME: should we have an option to say "generic for
885 static void __init pirq_find_router(struct irq_router *r)
887 struct irq_routing_table *rt = pirq_table;
888 struct irq_router_handler *h;
890 #ifdef CONFIG_PCI_BIOS
891 if (!rt->signature) {
892 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
893 r->set = pirq_bios_set;
899 /* Default unless a driver reloads it */
904 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
905 rt->rtr_vendor, rt->rtr_device);
907 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
908 if (!pirq_router_dev) {
909 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
913 for( h = pirq_routers; h->vendor; h++) {
914 /* First look for a router match */
915 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
917 /* Fall back to a device match */
918 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
921 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
923 pirq_router_dev->vendor,
924 pirq_router_dev->device,
925 pirq_router_dev->slot_name);
928 static struct irq_info *pirq_get_info(struct pci_dev *dev)
930 struct irq_routing_table *rt = pirq_table;
931 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
932 struct irq_info *info;
934 for (info = rt->slots; entries--; info++)
935 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
940 static void pcibios_test_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
944 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
947 struct irq_info *info;
951 struct irq_router *r = &pirq_router;
952 struct pci_dev *dev2;
958 /* Find IRQ routing entry */
959 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
961 DBG(" -> no interrupt pin\n");
966 DBG("IRQ for %s:%d", dev->slot_name, pin);
967 info = pirq_get_info(dev);
969 DBG(" -> not found in routing table\n");
972 pirq = info->irq[pin].link;
973 mask = info->irq[pin].bitmap;
975 DBG(" -> not routed\n");
978 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
979 mask &= pcibios_irq_mask;
981 /* Work around broken HP Pavilion Notebooks which assign USB to
982 IRQ 9 even though it is actually wired to IRQ 11 */
984 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
986 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
987 r->set(pirq_router_dev, dev, pirq, 11);
990 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
991 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
994 dev->irq = r->get(pirq_router_dev, dev, pirq);
995 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
999 * Find the best IRQ to assign: use the one
1000 * reported by the device if possible.
1003 if (!newirq && assign) {
1004 for (i = 0; i < 16; i++) {
1005 if (!(mask & (1 << i)))
1007 if (pirq_penalty[i] < pirq_penalty[newirq] &&
1008 !request_irq(i, pcibios_test_irq_handler, SA_SHIRQ, "pci-test", dev)) {
1014 DBG(" -> newirq=%d", newirq);
1016 /* Check if it is hardcoded */
1017 if ((pirq & 0xf0) == 0xf0) {
1019 DBG(" -> hardcoded IRQ %d\n", irq);
1021 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq))) {
1022 DBG(" -> got IRQ %d\n", irq);
1024 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
1025 DBG(" -> assigning IRQ %d", newirq);
1026 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
1027 eisa_set_level_irq(newirq);
1035 DBG(" ... failed\n");
1036 if (newirq && mask == (1 << newirq)) {
1042 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, dev->slot_name);
1044 /* Update IRQ for all devices with the same pirq value */
1045 pci_for_each_dev(dev2) {
1046 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
1050 info = pirq_get_info(dev2);
1053 if (info->irq[pin].link == pirq) {
1054 /* We refuse to override the dev->irq information. Give a warning! */
1055 if (dev2->irq && dev2->irq != irq) {
1056 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
1057 dev2->slot_name, dev2->irq, irq);
1061 pirq_penalty[irq]++;
1063 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, dev2->slot_name);
1069 void __init pcibios_irq_init(void)
1071 DBG("PCI: IRQ init\n");
1072 pirq_table = pirq_find_routing_table();
1073 #ifdef CONFIG_PCI_BIOS
1074 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1075 pirq_table = pcibios_get_irq_routing_table();
1079 pirq_find_router(&pirq_router);
1080 if (pirq_table->exclusive_irqs) {
1082 for (i=0; i<16; i++)
1083 if (!(pirq_table->exclusive_irqs & (1 << i)))
1084 pirq_penalty[i] += 100;
1086 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
1087 if (io_apic_assign_pci_irqs)
1092 void __init pcibios_fixup_irqs(void)
1094 struct pci_dev *dev;
1097 DBG("PCI: IRQ fixup\n");
1098 pci_for_each_dev(dev) {
1100 * If the BIOS has set an out of range IRQ number, just ignore it.
1101 * Also keep track of which IRQ's are already in use.
1103 if (dev->irq >= 16) {
1104 DBG("%s: ignoring bogus IRQ %d\n", dev->slot_name, dev->irq);
1107 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
1108 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
1109 pirq_penalty[dev->irq] = 0;
1110 pirq_penalty[dev->irq]++;
1113 pci_for_each_dev(dev) {
1114 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1115 #ifdef CONFIG_X86_IO_APIC
1117 * Recalculate IRQ numbers if we use the I/O APIC.
1119 if (io_apic_assign_pci_irqs)
1124 pin--; /* interrupt pins are numbered starting from 1 */
1125 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1127 * Busses behind bridges are typically not listed in the MP-table.
1128 * In this case we have to look up the IRQ based on the parent bus,
1129 * parent slot, and pin number. The SMP code detects such bridged
1130 * busses itself so we should get into this branch reliably.
1132 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1133 struct pci_dev * bridge = dev->bus->self;
1135 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1136 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1137 PCI_SLOT(bridge->devfn), pin);
1139 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
1140 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
1143 printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
1144 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
1151 * Still no IRQ? Try to lookup one...
1153 if (pin && !dev->irq)
1154 pcibios_lookup_irq(dev, 0);
1158 void pcibios_penalize_isa_irq(int irq)
1161 * If any ISAPnP device reports an IRQ in its list of possible
1162 * IRQ's, we try to avoid assigning it to PCI devices.
1164 pirq_penalty[irq] += 100;
1167 void pcibios_enable_irq(struct pci_dev *dev)
1170 extern int via_interrupt_line_quirk;
1171 struct pci_dev *temp_dev;
1173 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1174 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1177 pin--; /* interrupt pins are numbered starting from 1 */
1179 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1180 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1183 if (io_apic_assign_pci_irqs) {
1186 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1188 * Busses behind bridges are typically not listed in the MP-table.
1189 * In this case we have to look up the IRQ based on the parent bus,
1190 * parent slot, and pin number. The SMP code detects such bridged
1191 * busses itself so we should get into this branch reliably.
1194 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1195 struct pci_dev * bridge = dev->bus->self;
1197 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1198 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1199 PCI_SLOT(bridge->devfn), pin);
1201 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
1202 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
1207 printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
1208 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
1212 msg = " Probably buggy MP table.";
1213 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1216 msg = " Please try using pci=biosirq.";
1217 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1218 'A' + pin, dev->slot_name, msg);
1220 /* VIA bridges use interrupt line for apic/pci steering across
1222 else if (via_interrupt_line_quirk)
1223 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq & 15);