2 * Low-Level PCI Support for PC
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/acpi.h>
16 #include <asm/segment.h>
19 #include <asm/smpboot.h>
23 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
25 int pcibios_last_bus = -1;
26 struct pci_bus *pci_root_bus = NULL;
27 struct pci_ops *pci_root_ops = NULL;
29 int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value) = NULL;
30 int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value) = NULL;
32 static int pci_using_acpi_prt = 0;
34 #ifdef CONFIG_MULTIQUAD
35 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
36 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
37 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
39 #define BUS2QUAD(global) (0)
40 #define BUS2LOCAL(global) (global)
41 #define QUADLOCAL2BUS(quad,local) (local)
45 * This interrupt-safe spinlock protects all accesses to PCI
46 * configuration space.
48 static spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED;
52 * Functions for accessing PCI configuration space with type 1 accesses
55 #ifdef CONFIG_PCI_DIRECT
57 #ifdef CONFIG_MULTIQUAD
58 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
59 (0x80000000 | (BUS2LOCAL(bus) << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
61 static int pci_conf1_mq_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* CONFIG_MULTIQUAD */
65 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
68 spin_lock_irqsave(&pci_config_lock, flags);
70 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
74 *value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus));
77 *value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus));
80 *value = inl_quad(0xCFC, BUS2QUAD(bus));
84 spin_unlock_irqrestore(&pci_config_lock, flags);
89 static int pci_conf1_mq_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* CONFIG_MULTIQUAD */
93 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
96 spin_lock_irqsave(&pci_config_lock, flags);
98 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
102 outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus));
105 outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus));
108 outl_quad((u32)value, 0xCFC, BUS2QUAD(bus));
112 spin_unlock_irqrestore(&pci_config_lock, flags);
117 static int pci_conf1_read_mq_config_byte(struct pci_dev *dev, int where, u8 *value)
122 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
123 PCI_FUNC(dev->devfn), where, 1, &data);
130 static int pci_conf1_read_mq_config_word(struct pci_dev *dev, int where, u16 *value)
135 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
136 PCI_FUNC(dev->devfn), where, 2, &data);
143 static int pci_conf1_read_mq_config_dword(struct pci_dev *dev, int where, u32 *value)
148 return pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
149 PCI_FUNC(dev->devfn), where, 4, value);
152 static int pci_conf1_write_mq_config_byte(struct pci_dev *dev, int where, u8 value)
154 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
155 PCI_FUNC(dev->devfn), where, 1, value);
158 static int pci_conf1_write_mq_config_word(struct pci_dev *dev, int where, u16 value)
160 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
161 PCI_FUNC(dev->devfn), where, 2, value);
164 static int pci_conf1_write_mq_config_dword(struct pci_dev *dev, int where, u32 value)
166 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
167 PCI_FUNC(dev->devfn), where, 4, value);
170 static struct pci_ops pci_direct_mq_conf1 = {
171 pci_conf1_read_mq_config_byte,
172 pci_conf1_read_mq_config_word,
173 pci_conf1_read_mq_config_dword,
174 pci_conf1_write_mq_config_byte,
175 pci_conf1_write_mq_config_word,
176 pci_conf1_write_mq_config_dword
179 #endif /* !CONFIG_MULTIQUAD */
180 #undef PCI_CONF1_ADDRESS
181 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
182 (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
184 static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* !CONFIG_MULTIQUAD */
188 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
191 spin_lock_irqsave(&pci_config_lock, flags);
193 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
197 *value = inb(0xCFC + (reg & 3));
200 *value = inw(0xCFC + (reg & 2));
207 spin_unlock_irqrestore(&pci_config_lock, flags);
212 static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* !CONFIG_MULTIQUAD */
216 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
219 spin_lock_irqsave(&pci_config_lock, flags);
221 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
225 outb((u8)value, 0xCFC + (reg & 3));
228 outw((u16)value, 0xCFC + (reg & 2));
231 outl((u32)value, 0xCFC);
235 spin_unlock_irqrestore(&pci_config_lock, flags);
240 #undef PCI_CONF1_ADDRESS
242 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
247 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
248 PCI_FUNC(dev->devfn), where, 1, &data);
255 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
260 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
261 PCI_FUNC(dev->devfn), where, 2, &data);
268 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
270 return pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
271 PCI_FUNC(dev->devfn), where, 4, value);
274 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
276 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
277 PCI_FUNC(dev->devfn), where, 1, value);
280 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
282 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
283 PCI_FUNC(dev->devfn), where, 2, value);
286 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
288 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
289 PCI_FUNC(dev->devfn), where, 4, value);
292 static struct pci_ops pci_direct_conf1 = {
293 pci_conf1_read_config_byte,
294 pci_conf1_read_config_word,
295 pci_conf1_read_config_dword,
296 pci_conf1_write_config_byte,
297 pci_conf1_write_config_word,
298 pci_conf1_write_config_dword
303 * Functions for accessing PCI configuration space with type 2 accesses
306 #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
308 static int pci_conf2_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
312 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
316 return PCIBIOS_DEVICE_NOT_FOUND;
318 spin_lock_irqsave(&pci_config_lock, flags);
320 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
321 outb((u8)bus, 0xCFA);
325 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
328 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
331 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
337 spin_unlock_irqrestore(&pci_config_lock, flags);
342 static int pci_conf2_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
346 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
350 return PCIBIOS_DEVICE_NOT_FOUND;
352 spin_lock_irqsave(&pci_config_lock, flags);
354 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
355 outb((u8)bus, 0xCFA);
359 outb ((u8)value, PCI_CONF2_ADDRESS(dev, reg));
362 outw ((u16)value, PCI_CONF2_ADDRESS(dev, reg));
365 outl ((u32)value, PCI_CONF2_ADDRESS(dev, reg));
371 spin_unlock_irqrestore(&pci_config_lock, flags);
376 #undef PCI_CONF2_ADDRESS
378 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
382 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
383 PCI_FUNC(dev->devfn), where, 1, &data);
388 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
392 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
393 PCI_FUNC(dev->devfn), where, 2, &data);
398 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
400 return pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
401 PCI_FUNC(dev->devfn), where, 4, value);
404 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
406 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
407 PCI_FUNC(dev->devfn), where, 1, value);
410 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
412 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
413 PCI_FUNC(dev->devfn), where, 2, value);
416 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
418 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
419 PCI_FUNC(dev->devfn), where, 4, value);
422 static struct pci_ops pci_direct_conf2 = {
423 pci_conf2_read_config_byte,
424 pci_conf2_read_config_word,
425 pci_conf2_read_config_dword,
426 pci_conf2_write_config_byte,
427 pci_conf2_write_config_word,
428 pci_conf2_write_config_dword
433 * Before we decide to use direct hardware access mechanisms, we try to do some
434 * trivial checks to ensure it at least _seems_ to be working -- we just test
435 * whether bus 00 contains a host bridge (this is similar to checking
436 * techniques used in XFree86, but ours should be more reliable since we
437 * attempt to make use of direct access hints provided by the PCI BIOS).
439 * This should be close to trivial, but it isn't, because there are buggy
440 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
442 static int __devinit pci_sanity_check(struct pci_ops *o)
445 struct pci_bus bus; /* Fake bus and device */
448 if (pci_probe & PCI_NO_CHECKS)
452 for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
453 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
454 (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
455 (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
456 (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
458 DBG("PCI: Sanity check failed\n");
462 static struct pci_ops * __devinit pci_check_direct(void)
467 __save_flags(flags); __cli();
470 * Check if configuration type 1 works.
472 if (pci_probe & PCI_PROBE_CONF1) {
475 outl (0x80000000, 0xCF8);
476 if (inl (0xCF8) == 0x80000000 &&
477 pci_sanity_check(&pci_direct_conf1)) {
479 __restore_flags(flags);
480 printk(KERN_INFO "PCI: Using configuration type 1\n");
481 request_region(0xCF8, 8, "PCI conf1");
483 #ifdef CONFIG_MULTIQUAD
484 /* Multi-Quad has an extended PCI Conf1 */
485 if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
486 return &pci_direct_mq_conf1;
488 return &pci_direct_conf1;
494 * Check if configuration type 2 works.
496 if (pci_probe & PCI_PROBE_CONF2) {
500 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
501 pci_sanity_check(&pci_direct_conf2)) {
502 __restore_flags(flags);
503 printk(KERN_INFO "PCI: Using configuration type 2\n");
504 request_region(0xCF8, 4, "PCI conf2");
505 return &pci_direct_conf2;
509 __restore_flags(flags);
516 * BIOS32 and PCI BIOS handling.
519 #ifdef CONFIG_PCI_BIOS
521 #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
522 #define PCIBIOS_PCI_BIOS_PRESENT 0xb101
523 #define PCIBIOS_FIND_PCI_DEVICE 0xb102
524 #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
525 #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
526 #define PCIBIOS_READ_CONFIG_BYTE 0xb108
527 #define PCIBIOS_READ_CONFIG_WORD 0xb109
528 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a
529 #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
530 #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
531 #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
532 #define PCIBIOS_GET_ROUTING_OPTIONS 0xb10e
533 #define PCIBIOS_SET_PCI_HW_INT 0xb10f
535 /* BIOS32 signature: "_32_" */
536 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
538 /* PCI signature: "PCI " */
539 #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
541 /* PCI service signature: "$PCI" */
542 #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
544 /* PCI BIOS hardware mechanism flags */
545 #define PCIBIOS_HW_TYPE1 0x01
546 #define PCIBIOS_HW_TYPE2 0x02
547 #define PCIBIOS_HW_TYPE1_SPEC 0x10
548 #define PCIBIOS_HW_TYPE2_SPEC 0x20
551 * This is the standard structure used to identify the entry point
552 * to the BIOS32 Service Directory, as documented in
553 * Standard BIOS 32-bit Service Directory Proposal
554 * Revision 0.4 May 24, 1993
555 * Phoenix Technologies Ltd.
557 * and the PCI BIOS specification.
562 unsigned long signature; /* _32_ */
563 unsigned long entry; /* 32 bit physical address */
564 unsigned char revision; /* Revision level, 0 */
565 unsigned char length; /* Length in paragraphs should be 01 */
566 unsigned char checksum; /* All bytes must add up to zero */
567 unsigned char reserved[5]; /* Must be zero */
573 * Physical address of the service directory. I don't know if we're
574 * allowed to have more than one of these or not, so just in case
575 * we'll make pcibios_present() take a memory start parameter and store
580 unsigned long address;
581 unsigned short segment;
582 } bios32_indirect = { 0, __KERNEL_CS };
585 * Returns the entry point for the given service, NULL on error
588 static unsigned long bios32_service(unsigned long service)
590 unsigned char return_code; /* %al */
591 unsigned long address; /* %ebx */
592 unsigned long length; /* %ecx */
593 unsigned long entry; /* %edx */
596 __save_flags(flags); __cli();
597 __asm__("lcall (%%edi); cld"
598 : "=a" (return_code),
604 "D" (&bios32_indirect));
605 __restore_flags(flags);
607 switch (return_code) {
609 return address + entry;
610 case 0x80: /* Not present */
611 printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
613 default: /* Shouldn't happen */
614 printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
615 service, return_code);
621 unsigned long address;
622 unsigned short segment;
623 } pci_indirect = { 0, __KERNEL_CS };
625 static int pci_bios_present;
627 static int __devinit check_pcibios(void)
629 u32 signature, eax, ebx, ecx;
630 u8 status, major_ver, minor_ver, hw_mech;
631 unsigned long flags, pcibios_entry;
633 if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
634 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
636 __save_flags(flags); __cli();
638 "lcall (%%edi); cld\n\t"
646 : "1" (PCIBIOS_PCI_BIOS_PRESENT),
649 __restore_flags(flags);
651 status = (eax >> 8) & 0xff;
652 hw_mech = eax & 0xff;
653 major_ver = (ebx >> 8) & 0xff;
654 minor_ver = ebx & 0xff;
655 if (pcibios_last_bus < 0)
656 pcibios_last_bus = ecx & 0xff;
657 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
658 status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
659 if (status || signature != PCI_SIGNATURE) {
660 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n",
664 printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
665 major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
666 #ifdef CONFIG_PCI_DIRECT
667 if (!(hw_mech & PCIBIOS_HW_TYPE1))
668 pci_probe &= ~PCI_PROBE_CONF1;
669 if (!(hw_mech & PCIBIOS_HW_TYPE2))
670 pci_probe &= ~PCI_PROBE_CONF2;
677 static int __devinit pci_bios_find_device (unsigned short vendor, unsigned short device_id,
678 unsigned short index, unsigned char *bus, unsigned char *device_fn)
683 __asm__("lcall (%%edi); cld\n\t"
689 : "1" (PCIBIOS_FIND_PCI_DEVICE),
693 "D" (&pci_indirect));
694 *bus = (bx >> 8) & 0xff;
695 *device_fn = bx & 0xff;
696 return (int) (ret & 0xff00) >> 8;
699 static int pci_bios_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
701 unsigned long result = 0;
703 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
705 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
708 spin_lock_irqsave(&pci_config_lock, flags);
712 __asm__("lcall (%%esi); cld\n\t"
718 : "1" (PCIBIOS_READ_CONFIG_BYTE),
721 "S" (&pci_indirect));
724 __asm__("lcall (%%esi); cld\n\t"
730 : "1" (PCIBIOS_READ_CONFIG_WORD),
733 "S" (&pci_indirect));
736 __asm__("lcall (%%esi); cld\n\t"
742 : "1" (PCIBIOS_READ_CONFIG_DWORD),
745 "S" (&pci_indirect));
749 spin_unlock_irqrestore(&pci_config_lock, flags);
751 return (int)((result & 0xff00) >> 8);
754 static int pci_bios_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
756 unsigned long result = 0;
758 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
760 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
763 spin_lock_irqsave(&pci_config_lock, flags);
767 __asm__("lcall (%%esi); cld\n\t"
772 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
776 "S" (&pci_indirect));
779 __asm__("lcall (%%esi); cld\n\t"
784 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
788 "S" (&pci_indirect));
791 __asm__("lcall (%%esi); cld\n\t"
796 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
800 "S" (&pci_indirect));
804 spin_unlock_irqrestore(&pci_config_lock, flags);
806 return (int)((result & 0xff00) >> 8);
809 static int pci_bios_read_config_byte(struct pci_dev *dev, int where, u8 *value)
817 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
818 PCI_FUNC(dev->devfn), where, 1, &data);
825 static int pci_bios_read_config_word(struct pci_dev *dev, int where, u16 *value)
833 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
834 PCI_FUNC(dev->devfn), where, 2, &data);
841 static int pci_bios_read_config_dword(struct pci_dev *dev, int where, u32 *value)
846 return pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
847 PCI_FUNC(dev->devfn), where, 4, value);
850 static int pci_bios_write_config_byte(struct pci_dev *dev, int where, u8 value)
852 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
853 PCI_FUNC(dev->devfn), where, 1, value);
856 static int pci_bios_write_config_word(struct pci_dev *dev, int where, u16 value)
858 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
859 PCI_FUNC(dev->devfn), where, 2, value);
862 static int pci_bios_write_config_dword(struct pci_dev *dev, int where, u32 value)
864 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
865 PCI_FUNC(dev->devfn), where, 4, value);
870 * Function table for BIOS32 access
873 static struct pci_ops pci_bios_access = {
874 pci_bios_read_config_byte,
875 pci_bios_read_config_word,
876 pci_bios_read_config_dword,
877 pci_bios_write_config_byte,
878 pci_bios_write_config_word,
879 pci_bios_write_config_dword
883 * Try to find PCI BIOS.
886 static struct pci_ops * __devinit pci_find_bios(void)
893 * Follow the standard procedure for locating the BIOS32 Service
894 * directory by scanning the permissible address range from
895 * 0xe0000 through 0xfffff for a valid BIOS32 structure.
898 for (check = (union bios32 *) __va(0xe0000);
899 check <= (union bios32 *) __va(0xffff0);
901 if (check->fields.signature != BIOS32_SIGNATURE)
903 length = check->fields.length * 16;
907 for (i = 0; i < length ; ++i)
908 sum += check->chars[i];
911 if (check->fields.revision != 0) {
912 printk("PCI: unsupported BIOS32 revision %d at 0x%p\n",
913 check->fields.revision, check);
916 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
917 if (check->fields.entry >= 0x100000) {
918 printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
921 unsigned long bios32_entry = check->fields.entry;
922 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
923 bios32_indirect.address = bios32_entry + PAGE_OFFSET;
925 return &pci_bios_access;
927 break; /* Hopefully more than one BIOS32 cannot happen... */
934 * Sort the device list according to PCI BIOS. Nasty hack, but since some
935 * fool forgot to define the `correct' device order in the PCI BIOS specs
936 * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
937 * which used BIOS ordering, we are bound to do this...
940 static void __devinit pcibios_sort(void)
942 LIST_HEAD(sorted_devices);
943 struct list_head *ln;
944 struct pci_dev *dev, *d;
946 unsigned char bus, devfn;
948 DBG("PCI: Sorting device list...\n");
949 while (!list_empty(&pci_devices)) {
950 ln = pci_devices.next;
953 while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
955 for (ln=pci_devices.next; ln != &pci_devices; ln=ln->next) {
957 if (d->bus->number == bus && d->devfn == devfn) {
958 list_del(&d->global_list);
959 list_add_tail(&d->global_list, &sorted_devices);
965 if (ln == &pci_devices) {
966 printk(KERN_WARNING "PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
968 * We must not continue scanning as several buggy BIOSes
969 * return garbage after the last device. Grr.
975 printk(KERN_WARNING "PCI: Device %02x:%02x not found by BIOS\n",
976 dev->bus->number, dev->devfn);
977 list_del(&dev->global_list);
978 list_add_tail(&dev->global_list, &sorted_devices);
981 list_splice(&sorted_devices, &pci_devices);
985 * BIOS Functions for IRQ Routing
988 struct irq_routing_options {
990 struct irq_info *table;
992 } __attribute__((packed));
994 struct irq_routing_table * __devinit pcibios_get_irq_routing_table(void)
996 struct irq_routing_options opt;
997 struct irq_routing_table *rt = NULL;
1001 if (!pci_bios_present)
1003 page = __get_free_page(GFP_KERNEL);
1006 opt.table = (struct irq_info *) page;
1007 opt.size = PAGE_SIZE;
1008 opt.segment = __KERNEL_DS;
1010 DBG("PCI: Fetching IRQ routing table... ");
1011 __asm__("push %%es\n\t"
1014 "lcall (%%esi); cld\n\t"
1022 : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
1025 "S" (&pci_indirect),
1028 DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
1030 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
1031 else if (opt.size) {
1032 rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
1034 memset(rt, 0, sizeof(struct irq_routing_table));
1035 rt->size = opt.size + sizeof(struct irq_routing_table);
1036 rt->exclusive_irqs = map;
1037 memcpy(rt->slots, (void *) page, opt.size);
1038 printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
1046 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
1050 __asm__("lcall (%%esi); cld\n\t"
1055 : "0" (PCIBIOS_SET_PCI_HW_INT),
1056 "b" ((dev->bus->number << 8) | dev->devfn),
1057 "c" ((irq << 8) | (pin + 10)),
1058 "S" (&pci_indirect));
1059 return !(ret & 0xff00);
1065 * Several buggy motherboards address only 16 devices and mirror
1066 * them to next 16 IDs. We try to detect this `feature' on all
1067 * primary buses (those containing host bridges as they are
1068 * expected to be unique) and remove the ghost devices.
1071 static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
1073 struct list_head *ln, *mn;
1074 struct pci_dev *d, *e;
1075 int mirror = PCI_DEVFN(16,0);
1076 int seen_host_bridge = 0;
1079 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
1080 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
1082 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1084 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
1086 if (e->devfn != d->devfn + mirror ||
1087 e->vendor != d->vendor ||
1088 e->device != d->device ||
1089 e->class != d->class)
1091 for(i=0; i<PCI_NUM_RESOURCES; i++)
1092 if (e->resource[i].start != d->resource[i].start ||
1093 e->resource[i].end != d->resource[i].end ||
1094 e->resource[i].flags != d->resource[i].flags)
1098 if (mn == &b->devices)
1101 if (!seen_host_bridge)
1103 printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
1106 while (ln->next != &b->devices) {
1107 d = pci_dev_b(ln->next);
1108 if (d->devfn >= mirror) {
1109 list_del(&d->global_list);
1110 list_del(&d->bus_list);
1118 * Discover remaining PCI buses in case there are peer host bridges.
1119 * We use the number of last PCI bus provided by the PCI BIOS.
1121 static void __devinit pcibios_fixup_peer_bridges(void)
1128 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
1130 DBG("PCI: Peer bridge fixup\n");
1131 for (n=0; n <= pcibios_last_bus; n++) {
1132 if (pci_bus_exists(&pci_root_buses, n))
1135 bus.ops = pci_root_ops;
1137 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
1138 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
1139 l != 0x0000 && l != 0xffff) {
1140 DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
1141 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
1142 pci_scan_bus(n, pci_root_ops, NULL);
1149 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
1152 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
1155 * i450NX -- Find and scan all secondary buses on all PXB's.
1158 u8 busno, suba, subb;
1159 #ifdef CONFIG_MULTIQUAD
1160 int quad = BUS2QUAD(d->bus->number);
1162 printk("PCI: Searching for i450NX host bridges on %s\n", d->slot_name);
1164 for(pxb=0; pxb<2; pxb++) {
1165 pci_read_config_byte(d, reg++, &busno);
1166 pci_read_config_byte(d, reg++, &suba);
1167 pci_read_config_byte(d, reg++, &subb);
1168 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
1170 pci_scan_bus(QUADLOCAL2BUS(quad,busno), pci_root_ops, NULL); /* Bus A */
1172 pci_scan_bus(QUADLOCAL2BUS(quad,suba+1), pci_root_ops, NULL); /* Bus B */
1174 pcibios_last_bus = -1;
1177 static void __devinit pci_fixup_i450gx(struct pci_dev *d)
1180 * i450GX and i450KX -- Find and scan all secondary buses.
1181 * (called separately for each PCI bridge found)
1184 pci_read_config_byte(d, 0x4a, &busno);
1185 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
1186 pci_scan_bus(busno, pci_root_ops, NULL);
1187 pcibios_last_bus = -1;
1190 static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
1193 * UM8886BF IDE controller sets region type bits incorrectly,
1194 * therefore they look like memory despite of them being I/O.
1198 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", d->slot_name);
1200 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
1203 static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
1206 * NCR 53C810 returns class code 0 (at least on some systems).
1207 * Fix class to be PCI_CLASS_STORAGE_SCSI
1210 printk("PCI: fixing NCR 53C810 class code for %s\n", d->slot_name);
1211 d->class = PCI_CLASS_STORAGE_SCSI << 8;
1215 static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
1220 * PCI IDE controllers use non-standard I/O port decoding, respect it.
1222 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
1224 DBG("PCI: IDE base address fixup for %s\n", d->slot_name);
1225 for(i=0; i<4; i++) {
1226 struct resource *r = &d->resource[i];
1227 if ((r->start & ~0x80) == 0x374) {
1234 static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
1239 * There exist PCI IDE controllers which have utter garbage
1240 * in first four base registers. Ignore that.
1242 DBG("PCI: IDE base address trash cleared for %s\n", d->slot_name);
1244 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
1247 static void __devinit pci_fixup_latency(struct pci_dev *d)
1250 * SiS 5597 and 5598 chipsets require latency timer set to
1251 * at most 32 to avoid lockups.
1253 DBG("PCI: Setting max latency to 32\n");
1254 pcibios_max_latency = 32;
1257 static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
1260 * PIIX4 ACPI device: hardwired IRQ9
1266 * Addresses issues with problems in the memory write queue timer in
1267 * certain VIA Northbridges. This bugfix is per VIA's specifications,
1268 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
1269 * to trigger a bug in its integrated ProSavage video card, which
1270 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
1271 * until VIA can provide us with definitive information on why screen
1272 * corruption occurs, and what exactly those bits do.
1274 * VIA 8363,8622,8361 Northbridges:
1275 * - bits 5, 6, 7 at offset 0x55 need to be turned off
1276 * VIA 8367 (KT266x) Northbridges:
1277 * - bits 5, 6, 7 at offset 0x95 need to be turned off
1278 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
1279 * - bits 6, 7 at offset 0x55 need to be turned off
1282 #define VIA_8363_KL133_REVISION_ID 0x81
1283 #define VIA_8363_KM133_REVISION_ID 0x84
1285 static void __init pci_fixup_via_northbridge_bug(struct pci_dev *d)
1290 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
1292 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
1294 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
1295 /* fix pci bus latency issues resulted by NB bios error
1296 it appears on bug free^Wreduced kt266x's bios forces
1297 NB latency to zero */
1298 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
1300 where = 0x95; /* the memory write queue timer register is
1301 different for the KT266x's: 0x95 not 0x55 */
1302 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
1303 (revision == VIA_8363_KL133_REVISION_ID ||
1304 revision == VIA_8363_KM133_REVISION_ID)) {
1305 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
1306 causes screen corruption on the KL133/KM133 */
1309 pci_read_config_byte(d, where, &v);
1311 printk("Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
1312 d->device, revision, where, v, mask, v & mask);
1314 pci_write_config_byte(d, where, v);
1319 * For some reasons Intel decided that certain parts of their
1320 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
1321 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
1322 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
1323 * to Intel terminology. These devices do forward all addresses from
1324 * system to PCI bus no matter what are their window settings, so they are
1325 * "transparent" (or subtractive decoding) from programmers point of view.
1327 static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
1329 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1330 (dev->device & 0xff00) == 0x2400)
1331 dev->transparent = 1;
1335 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
1337 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
1339 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
1340 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
1341 * This allows the state-machine and timer to return to a proper state within
1342 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
1343 * issue another HALT within 80 ns of the initial HALT, the failure condition
1346 static void __devinit pci_fixup_nforce2(struct pci_dev *dev)
1351 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1354 * Chip Old value New value
1355 * C17 0x1F0FFF01 0x1F01FF01
1356 * C18D 0x9F0FFF01 0x9F01FF01
1358 fixed_val = rev < 0xC1 ? 0x1F01FF01 : 0x9F01FF01;
1360 pci_read_config_dword(dev, 0x6c, &val);
1361 if (val != fixed_val) {
1362 printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
1363 pci_write_config_dword(dev, 0x6c, fixed_val);
1367 struct pci_fixup pcibios_fixups[] = {
1368 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx },
1369 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx },
1370 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide },
1371 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash },
1372 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
1373 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency },
1374 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency },
1375 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi },
1376 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug },
1377 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug },
1378 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug },
1379 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug },
1380 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810 },
1381 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge },
1382 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2},
1387 * Called after each bus is probed, but before its children
1391 void __devinit pcibios_fixup_bus(struct pci_bus *b)
1393 pcibios_fixup_ghosts(b);
1394 pci_read_bridge_bases(b);
1397 struct pci_bus * __devinit pcibios_scan_root(int busnum)
1399 struct list_head *list;
1400 struct pci_bus *bus;
1402 list_for_each(list, &pci_root_buses) {
1403 bus = pci_bus_b(list);
1404 if (bus->number == busnum) {
1405 /* Already scanned */
1410 printk("PCI: Probing PCI hardware (bus %02x)\n", busnum);
1412 return pci_scan_bus(busnum, pci_root_ops, NULL);
1415 void __devinit pcibios_config_init(void)
1418 * Try all known PCI access methods. Note that we support using
1419 * both PCI BIOS and direct access, with a preference for direct.
1422 #ifdef CONFIG_PCI_DIRECT
1423 struct pci_ops *tmp = NULL;
1427 #ifdef CONFIG_PCI_BIOS
1428 if ((pci_probe & PCI_PROBE_BIOS)
1429 && ((pci_root_ops = pci_find_bios()))) {
1430 pci_probe |= PCI_BIOS_SORT;
1431 pci_bios_present = 1;
1432 pci_config_read = pci_bios_read;
1433 pci_config_write = pci_bios_write;
1437 #ifdef CONFIG_PCI_DIRECT
1438 if ((pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
1439 && (tmp = pci_check_direct())) {
1441 if (pci_root_ops == &pci_direct_conf1) {
1442 pci_config_read = pci_conf1_read;
1443 pci_config_write = pci_conf1_write;
1446 pci_config_read = pci_conf2_read;
1447 pci_config_write = pci_conf2_write;
1455 void __init pcibios_init(void)
1460 pcibios_config_init();
1461 if (!pci_root_ops) {
1462 printk(KERN_WARNING "PCI: System does not support PCI\n");
1466 pcibios_set_cacheline_size();
1468 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1469 #ifdef CONFIG_ACPI_PCI
1470 if (!acpi_noirq && !acpi_pci_irq_init()) {
1471 pci_using_acpi_prt = 1;
1472 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
1475 if (!pci_using_acpi_prt) {
1476 pci_root_bus = pcibios_scan_root(0);
1478 pcibios_fixup_peer_bridges();
1479 pcibios_fixup_irqs();
1481 if (clustered_apic_mode && (numnodes > 1)) {
1482 for (quad = 1; quad < numnodes; ++quad) {
1483 printk("Scanning PCI bus %d for quad %d\n",
1484 QUADLOCAL2BUS(quad,0), quad);
1485 pci_scan_bus(QUADLOCAL2BUS(quad,0),
1486 pci_root_ops, NULL);
1490 pcibios_resource_survey();
1492 #ifdef CONFIG_PCI_BIOS
1493 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
1498 char * __devinit pcibios_setup(char *str)
1500 if (!strcmp(str, "off")) {
1504 #ifdef CONFIG_PCI_BIOS
1505 else if (!strcmp(str, "bios")) {
1506 pci_probe = PCI_PROBE_BIOS;
1508 } else if (!strcmp(str, "nobios")) {
1509 pci_probe &= ~PCI_PROBE_BIOS;
1511 } else if (!strcmp(str, "nosort")) {
1512 pci_probe |= PCI_NO_SORT;
1514 } else if (!strcmp(str, "biosirq")) {
1515 pci_probe |= PCI_BIOS_IRQ_SCAN;
1519 #ifdef CONFIG_PCI_DIRECT
1520 else if (!strcmp(str, "conf1")) {
1521 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
1524 else if (!strcmp(str, "conf2")) {
1525 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
1529 else if (!strcmp(str, "rom")) {
1530 pci_probe |= PCI_ASSIGN_ROMS;
1532 } else if (!strcmp(str, "assign-busses")) {
1533 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
1535 } else if (!strncmp(str, "irqmask=", 8)) {
1536 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
1538 } else if (!strncmp(str, "lastbus=", 8)) {
1539 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
1541 } else if (!strncmp(str, "noacpi", 6)) {
1548 unsigned int pcibios_assign_all_busses(void)
1550 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
1553 int pcibios_enable_device(struct pci_dev *dev, int mask)
1557 if ((err = pcibios_enable_resources(dev, mask)) < 0)
1560 #ifdef CONFIG_ACPI_PCI
1561 if (pci_using_acpi_prt) {
1562 acpi_pci_irq_enable(dev);
1567 pcibios_enable_irq(dev);