2 * hades-pci.c - Hardware specific PCI BIOS functions the Hades Atari clone.
4 * Written by Wout Klaren.
7 #include <linux/config.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
13 # define DBG_DEVS(args) printk args
15 # define DBG_DEVS(args)
18 #if defined(CONFIG_PCI) && defined(CONFIG_HADES)
20 #include <linux/slab.h>
22 #include <linux/pci.h>
24 #include <asm/atarihw.h>
25 #include <asm/atariints.h>
26 #include <asm/byteorder.h>
29 #define HADES_MEM_BASE 0x80000000
30 #define HADES_MEM_SIZE 0x20000000
31 #define HADES_CONFIG_BASE 0xA0000000
32 #define HADES_CONFIG_SIZE 0x10000000
33 #define HADES_IO_BASE 0xB0000000
34 #define HADES_IO_SIZE 0x10000000
35 #define HADES_VIRT_IO_SIZE 0x00010000 /* Only 64k is remapped and actually used. */
37 #define N_SLOTS 4 /* Number of PCI slots. */
39 static const char pci_mem_name[] = "PCI memory space";
40 static const char pci_io_name[] = "PCI I/O space";
41 static const char pci_config_name[] = "PCI config space";
43 static struct resource config_space = { pci_config_name, HADES_CONFIG_BASE,
44 HADES_CONFIG_BASE + HADES_CONFIG_SIZE - 1 };
45 static struct resource io_space = { pci_io_name, HADES_IO_BASE, HADES_IO_BASE +
48 static const unsigned long pci_conf_base_phys[] = { 0xA0080000, 0xA0040000,
49 0xA0020000, 0xA0010000 };
50 static unsigned long pci_conf_base_virt[N_SLOTS];
51 static unsigned long pci_io_base_virt;
54 * static void *mk_conf_addr(unsigned char bus, unsigned char device_fn,
55 * unsigned char where)
57 * Calculate the address of the PCI configuration area of the given
60 * BUG: boards with multiple functions are probably not correctly
64 static void *mk_conf_addr(struct pci_dev *dev, int where)
66 int device = dev->devfn >> 3, function = dev->devfn & 7;
69 DBG_DEVS(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, pci_addr=0x%p)\n",
70 dev->bus->number, dev->devfn, where, pci_addr));
74 DBG_DEVS(("mk_conf_addr: device (%d) > 3, returning NULL\n", device));
78 if (dev->bus->number != 0)
80 DBG_DEVS(("mk_conf_addr: bus (%d) > 0, returning NULL\n", device));
84 result = (void *) (pci_conf_base_virt[device] | (function << 8) | (where));
85 DBG_DEVS(("mk_conf_addr: returning pci_addr 0x%lx\n", (unsigned long) result));
89 static int hades_read_config_byte(struct pci_dev *dev, int where, u8 *value)
91 volatile unsigned char *pci_addr;
95 if ((pci_addr = (unsigned char *) mk_conf_addr(dev, where)) == NULL)
96 return PCIBIOS_DEVICE_NOT_FOUND;
100 return PCIBIOS_SUCCESSFUL;
103 static int hades_read_config_word(struct pci_dev *dev, int where, u16 *value)
105 volatile unsigned short *pci_addr;
110 return PCIBIOS_BAD_REGISTER_NUMBER;
112 if ((pci_addr = (unsigned short *) mk_conf_addr(dev, where)) == NULL)
113 return PCIBIOS_DEVICE_NOT_FOUND;
115 *value = le16_to_cpu(*pci_addr);
117 return PCIBIOS_SUCCESSFUL;
120 static int hades_read_config_dword(struct pci_dev *dev, int where, u32 *value)
122 volatile unsigned int *pci_addr;
123 unsigned char header_type;
129 return PCIBIOS_BAD_REGISTER_NUMBER;
131 if ((pci_addr = (unsigned int *) mk_conf_addr(dev, where)) == NULL)
132 return PCIBIOS_DEVICE_NOT_FOUND;
134 *value = le32_to_cpu(*pci_addr);
137 * Check if the value is an address on the bus. If true, add the
138 * base address of the PCI memory or PCI I/O area on the Hades.
141 if ((result = hades_read_config_byte(dev, PCI_HEADER_TYPE,
142 &header_type)) != PCIBIOS_SUCCESSFUL)
145 if (((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_1)) ||
146 ((header_type != PCI_HEADER_TYPE_BRIDGE) && ((where >= PCI_BASE_ADDRESS_2) &&
147 (where <= PCI_BASE_ADDRESS_5))))
149 if ((*value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
152 * Base address register that contains an I/O address. If the
153 * address is valid on the Hades (0 <= *value < HADES_VIRT_IO_SIZE),
154 * add 'pci_io_base_virt' to the value.
157 if (*value < HADES_VIRT_IO_SIZE)
158 *value += pci_io_base_virt;
163 * Base address register that contains an memory address. If the
164 * address is valid on the Hades (0 <= *value < HADES_MEM_SIZE),
165 * add HADES_MEM_BASE to the value.
171 * Base address is 0. Test if this base
172 * address register is used.
175 *pci_addr = 0xffffffff;
179 if (*value < HADES_MEM_SIZE)
180 *value += HADES_MEM_BASE;
185 if (*value < HADES_MEM_SIZE)
186 *value += HADES_MEM_BASE;
191 return PCIBIOS_SUCCESSFUL;
194 static int hades_write_config_byte(struct pci_dev *dev, int where, u8 value)
196 volatile unsigned char *pci_addr;
198 if ((pci_addr = (unsigned char *) mk_conf_addr(dev, where)) == NULL)
199 return PCIBIOS_DEVICE_NOT_FOUND;
203 return PCIBIOS_SUCCESSFUL;
206 static int hades_write_config_word(struct pci_dev *dev, int where, u16 value)
208 volatile unsigned short *pci_addr;
210 if ((pci_addr = (unsigned short *) mk_conf_addr(dev, where)) == NULL)
211 return PCIBIOS_DEVICE_NOT_FOUND;
213 *pci_addr = cpu_to_le16(value);
215 return PCIBIOS_SUCCESSFUL;
218 static int hades_write_config_dword(struct pci_dev *dev, int where, u32 value)
220 volatile unsigned int *pci_addr;
221 unsigned char header_type;
224 if ((pci_addr = (unsigned int *) mk_conf_addr(dev, where)) == NULL)
225 return PCIBIOS_DEVICE_NOT_FOUND;
228 * Check if the value is an address on the bus. If true, subtract the
229 * base address of the PCI memory or PCI I/O area on the Hades.
232 if ((result = hades_read_config_byte(dev, PCI_HEADER_TYPE,
233 &header_type)) != PCIBIOS_SUCCESSFUL)
236 if (((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_1)) ||
237 ((header_type != PCI_HEADER_TYPE_BRIDGE) && ((where >= PCI_BASE_ADDRESS_2) &&
238 (where <= PCI_BASE_ADDRESS_5))))
240 if ((value & PCI_BASE_ADDRESS_SPACE) ==
241 PCI_BASE_ADDRESS_SPACE_IO)
244 * I/O address. Check if the address is valid address on
245 * the Hades (pci_io_base_virt <= value < pci_io_base_virt +
246 * HADES_VIRT_IO_SIZE) or if the value is 0xffffffff. If not
247 * true do not write the base address register. If it is a
248 * valid base address subtract 'pci_io_base_virt' from the value.
251 if ((value >= pci_io_base_virt) && (value < (pci_io_base_virt +
252 HADES_VIRT_IO_SIZE)))
253 value -= pci_io_base_virt;
256 if (value != 0xffffffff)
257 return PCIBIOS_SET_FAILED;
263 * Memory address. Check if the address is valid address on
264 * the Hades (HADES_MEM_BASE <= value < HADES_MEM_BASE + HADES_MEM_SIZE) or
265 * if the value is 0xffffffff. If not true do not write
266 * the base address register. If it is a valid base address
267 * subtract HADES_MEM_BASE from the value.
270 if ((value >= HADES_MEM_BASE) && (value < (HADES_MEM_BASE + HADES_MEM_SIZE)))
271 value -= HADES_MEM_BASE;
274 if (value != 0xffffffff)
275 return PCIBIOS_SET_FAILED;
280 *pci_addr = cpu_to_le32(value);
282 return PCIBIOS_SUCCESSFUL;
286 * static inline void hades_fixup(void)
288 * Assign IRQ numbers as used by Linux to the interrupt pins
292 static void __init hades_fixup(int pci_modify)
295 IRQ_TT_MFP_IO0, /* Slot 0. */
296 IRQ_TT_MFP_IO1, /* Slot 1. */
297 IRQ_TT_MFP_SCC, /* Slot 2. */
298 IRQ_TT_MFP_SCSIDMA /* Slot 3. */
304 * Go through all devices, fixing up irqs as we see fit:
307 for (dev = pci_devices; dev; dev = dev->next)
309 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE)
311 slot = PCI_SLOT(dev->devfn); /* Determine slot number. */
312 dev->irq = irq_tab[slot];
314 pcibios_write_config_byte(dev->bus->number, dev->devfn,
315 PCI_INTERRUPT_LINE, dev->irq);
321 * static void hades_conf_device(unsigned char bus, unsigned char device_fn)
323 * Machine dependent Configure the given device.
327 * bus - bus number of the device.
328 * device_fn - device and function number of the device.
331 static void __init hades_conf_device(unsigned char bus, unsigned char device_fn)
333 pcibios_write_config_byte(bus, device_fn, PCI_CACHE_LINE_SIZE, 0);
336 static struct pci_ops hades_pci_ops = {
337 read_byte: hades_read_config_byte
338 read_word: hades_read_config_word
339 read_dword: hades_read_config_dword
340 write_byte: hades_write_config_byte
341 write_word: hades_write_config_word
342 write_dword: hades_write_config_dword
346 * struct pci_bus_info *init_hades_pci(void)
348 * Machine specific initialisation:
350 * - Allocate and initialise a 'pci_bus_info' structure
351 * - Initialise hardware
353 * Result: pointer to 'pci_bus_info' structure.
356 struct pci_bus_info * __init init_hades_pci(void)
358 struct pci_bus_info *bus;
362 * Remap I/O and configuration space.
365 pci_io_base_virt = (unsigned long) ioremap(HADES_IO_BASE, HADES_VIRT_IO_SIZE);
367 for (i = 0; i < N_SLOTS; i++)
368 pci_conf_base_virt[i] = (unsigned long) ioremap(pci_conf_base_phys[i], 0x10000);
371 * Allocate memory for bus info structure.
374 bus = kmalloc(sizeof(struct pci_bus_info), GFP_KERNEL);
377 memset(bus, 0, sizeof(struct pci_bus_info));
380 * Claim resources. The m68k has no seperate I/O space, both
381 * PCI memory space and PCI I/O space are in memory space. Therefore
382 * the I/O resources are requested in memory space as well.
385 if (request_resource(&iomem_resource, &config_space) != 0)
391 if (request_resource(&iomem_resource, &io_space) != 0)
393 release_resource(&config_space);
398 bus->mem_space.start = HADES_MEM_BASE;
399 bus->mem_space.end = HADES_MEM_BASE + HADES_MEM_SIZE - 1;
400 bus->mem_space.name = pci_mem_name;
402 if (request_resource(&iomem_resource, &bus->mem_space) != 0)
404 release_resource(&io_space);
405 release_resource(&config_space);
410 bus->io_space.start = pci_io_base_virt;
411 bus->io_space.end = pci_io_base_virt + HADES_VIRT_IO_SIZE - 1;
412 bus->io_space.name = pci_io_name;
414 if (request_resource(&ioport_resource, &bus->io_space) != 0)
416 release_resource(&bus->mem_space);
417 release_resource(&io_space);
418 release_resource(&config_space);
424 * Set hardware dependent functions.
427 bus->m68k_pci_ops = &hades_pci_ops;
428 bus->fixup = hades_fixup;
429 bus->conf_device = hades_conf_device;
432 * Select high to low edge for PCI interrupts.
435 tt_mfp.active_edge &= ~0x27;