3 * BRIEF MODULE DESCRIPTION
4 * IT8172 system controller specific pci support.
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/config.h>
34 #include <linux/types.h>
35 #include <linux/pci.h>
36 #include <linux/kernel.h>
37 #include <linux/init.h>
39 #include <asm/pci_channel.h>
40 #include <asm/it8172/it8172.h>
41 #include <asm/it8172/it8172_pci.h>
43 #define PCI_ACCESS_READ 0
44 #define PCI_ACCESS_WRITE 1
48 #define DBG(x...) printk(x)
53 static struct resource pci_mem_resource_1;
55 static struct resource pci_io_resource = {
62 static struct resource pci_mem_resource_0 = {
63 "ext pci memory space 0/1",
72 static struct resource pci_mem_resource_1 = {
73 "ext pci memory space 2/3",
82 extern struct pci_ops it8172_pci_ops;
84 struct pci_channel mips_pci_channels[] = {
85 { &it8172_pci_ops, &pci_io_resource, &pci_mem_resource_0, 0x10, 0xff },
86 { NULL, NULL, NULL, NULL, NULL}
90 it8172_pcibios_config_access(unsigned char access_type, struct pci_dev *dev,
91 unsigned char where, u32 *data)
94 * config cycles are on 4 byte boundary only
96 unsigned char bus = dev->bus->number;
97 unsigned char dev_fn = dev->devfn;
99 DBG("it config: type %d dev %x bus %d dev_fn %x data %x\n",
100 access_type, dev, bus, dev_fn, *data);
103 IT_WRITE(IT_CONFADDR, (bus << IT_BUSNUM_SHF) |
104 (dev_fn << IT_FUNCNUM_SHF) | (where & ~0x3));
107 if (access_type == PCI_ACCESS_WRITE) {
108 IT_WRITE(IT_CONFDATA, *data);
111 IT_READ(IT_CONFDATA, *data);
115 * Revisit: check for master or target abort.
124 * We can't address 8 and 16 bit words directly. Instead we have to
125 * read/write a 32bit word and mask/modify the data we actually want.
128 read_config_byte (struct pci_dev *dev, int where, u8 *val)
132 if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
135 *val = (data >> ((where & 3) << 3)) & 0xff;
136 DBG("cfg read byte: bus %d dev_fn %x where %x: val %x\n",
137 dev->bus->number, dev->devfn, where, *val);
139 return PCIBIOS_SUCCESSFUL;
144 read_config_word (struct pci_dev *dev, int where, u16 *val)
149 return PCIBIOS_BAD_REGISTER_NUMBER;
151 if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
154 *val = (data >> ((where & 3) << 3)) & 0xffff;
155 DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n",
156 dev->bus->number, dev->devfn, where, *val);
158 return PCIBIOS_SUCCESSFUL;
162 read_config_dword (struct pci_dev *dev, int where, u32 *val)
167 return PCIBIOS_BAD_REGISTER_NUMBER;
169 if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
173 DBG("cfg read dword: bus %d dev_fn %x where %x: val %x\n",
174 dev->bus->number, dev->devfn, where, *val);
176 return PCIBIOS_SUCCESSFUL;
181 write_config_byte (struct pci_dev *dev, int where, u8 val)
185 if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
188 data = (data & ~(0xff << ((where & 3) << 3))) |
189 (val << ((where & 3) << 3));
191 if (it8172_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data))
194 return PCIBIOS_SUCCESSFUL;
198 write_config_word (struct pci_dev *dev, int where, u16 val)
203 return PCIBIOS_BAD_REGISTER_NUMBER;
205 if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
208 data = (data & ~(0xffff << ((where & 3) << 3))) |
209 (val << ((where & 3) << 3));
211 if (it8172_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data))
215 return PCIBIOS_SUCCESSFUL;
219 write_config_dword(struct pci_dev *dev, int where, u32 val)
222 return PCIBIOS_BAD_REGISTER_NUMBER;
224 if (it8172_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &val))
227 return PCIBIOS_SUCCESSFUL;
230 struct pci_ops it8172_pci_ops = {
239 unsigned __init int pcibios_assign_all_busses(void)
243 #endif /* CONFIG_PCI */