2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 * Copyright (C) 2000-2001 Toshiba Corporation
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/config.h>
33 #include <linux/init.h>
35 #include <linux/errno.h>
36 #include <linux/irq.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/signal.h>
39 #include <linux/sched.h>
40 #include <linux/types.h>
41 #include <linux/interrupt.h>
42 #include <linux/ioport.h>
43 #include <linux/timex.h>
44 #include <linux/slab.h>
45 #include <linux/random.h>
46 #include <linux/smp.h>
47 #include <linux/smp_lock.h>
49 #include <asm/bitops.h>
51 #include <asm/mipsregs.h>
52 #include <asm/system.h>
54 #include <asm/ptrace.h>
55 #include <asm/processor.h>
56 #include <asm/jmr3927/irq.h>
57 #include <asm/debug.h>
58 #include <asm/jmr3927/jmr3927.h>
60 #if JMR3927_IRQ_END > NR_IRQS
61 #error JMR3927_IRQ_END > NR_IRQS
64 struct tb_irq_space* tb_irq_spaces;
66 unsigned int local_bh_count[NR_CPUS];
67 unsigned int local_irq_count[NR_CPUS];
69 static int jmr3927_irq_base=-1;
72 static int jmr3927_gen_iack(void)
74 /* generate ACK cycle */
76 return (tx3927_pcicptr->iiadp >> 24) & 0xff;
78 return tx3927_pcicptr->iiadp & 0xff;
83 extern asmlinkage void jmr3927_IRQ(void);
87 static unsigned char irc_level[TX3927_NUM_IR] = {
88 5, 5, 5, 5, 5, 5, /* INT[5:0] */
90 5, 5, 5, 0, 0, /* DMA, PIO, PCI */
94 static inline void mask_irq(unsigned int irq_nr)
96 struct tb_irq_space* sp;
97 for (sp = tb_irq_spaces; sp; sp = sp->next) {
98 if (sp->start_irqno <= irq_nr &&
99 irq_nr < sp->start_irqno + sp->nr_irqs) {
101 sp->mask_func(irq_nr - sp->start_irqno,
108 static inline void unmask_irq(unsigned int irq_nr)
110 struct tb_irq_space* sp;
111 for (sp = tb_irq_spaces; sp; sp = sp->next) {
112 if (sp->start_irqno <= irq_nr &&
113 irq_nr < sp->start_irqno + sp->nr_irqs) {
115 sp->unmask_func(irq_nr - sp->start_irqno,
122 static void jmr3927_irq_disable(unsigned int irq_nr);
123 static void jmr3927_irq_enable(unsigned int irq_nr);
125 static unsigned int jmr3927_irq_startup(unsigned int irq)
127 jmr3927_irq_enable(irq);
131 #define jmr3927_irq_shutdown jmr3927_irq_disable
133 static void jmr3927_irq_ack(unsigned int irq)
135 db_assert(jmr3927_irq_base != -1);
136 db_assert(irq >= jmr3927_irq_base);
137 db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
139 if (irq == JMR3927_IRQ_IRC_TMR0) {
140 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
143 jmr3927_irq_disable(irq);
146 static void jmr3927_irq_end(unsigned int irq)
148 db_assert(jmr3927_irq_base != -1);
149 db_assert(irq >= jmr3927_irq_base);
150 db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
152 jmr3927_irq_enable(irq);
155 static void jmr3927_irq_disable(unsigned int irq_nr)
159 db_assert(jmr3927_irq_base != -1);
160 db_assert(irq >= jmr3927_irq_base);
161 db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
165 restore_flags(flags);
168 static void jmr3927_irq_enable(unsigned int irq_nr)
172 db_assert(jmr3927_irq_base != -1);
173 db_assert(irq >= jmr3927_irq_base);
174 db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
178 restore_flags(flags);
182 * CP0_STATUS is a thread's resource (saved/restored on context switch).
183 * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
185 static void mask_irq_isac(int irq_nr, int space_id)
188 unsigned char imask =
189 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
190 unsigned int bit = 1 << irq_nr;
191 jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
192 /* flush write buffer */
193 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
195 static void unmask_irq_isac(int irq_nr, int space_id)
198 unsigned char imask =
199 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
200 unsigned int bit = 1 << irq_nr;
201 jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
202 /* flush write buffer */
203 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
206 static void mask_irq_ioc(int irq_nr, int space_id)
209 unsigned char imask =
210 jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
211 unsigned int bit = 1 << irq_nr;
212 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
213 /* flush write buffer */
214 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
216 static void unmask_irq_ioc(int irq_nr, int space_id)
219 unsigned char imask =
220 jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
221 unsigned int bit = 1 << irq_nr;
222 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
223 /* flush write buffer */
224 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
227 static void mask_irq_irc(int irq_nr, int space_id)
229 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
231 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
233 *ilrp = (*ilrp & 0xff00) | irc_dlevel;
235 tx3927_ircptr->imr = 0;
236 tx3927_ircptr->imr = irc_elevel;
238 static void unmask_irq_irc(int irq_nr, int space_id)
240 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
242 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
244 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
246 tx3927_ircptr->imr = 0;
247 tx3927_ircptr->imr = irc_elevel;
250 struct tb_irq_space jmr3927_isac_irqspace = {
252 .start_irqno = JMR3927_IRQ_ISAC,
253 nr_irqs : JMR3927_NR_IRQ_ISAC,
254 .mask_func = mask_irq_isac,
255 .unmask_func = unmask_irq_isac,
260 struct tb_irq_space jmr3927_ioc_irqspace = {
262 .start_irqno = JMR3927_IRQ_IOC,
263 nr_irqs : JMR3927_NR_IRQ_IOC,
264 .mask_func = mask_irq_ioc,
265 .unmask_func = unmask_irq_ioc,
270 struct tb_irq_space jmr3927_irc_irqspace = {
272 .start_irqno = JMR3927_IRQ_IRC,
273 nr_irqs : JMR3927_NR_IRQ_IRC,
274 .mask_func = mask_irq_irc,
275 .unmask_func = unmask_irq_irc,
281 void jmr3927_spurious(struct pt_regs *regs)
283 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
284 tx_branch_likely_bug_fixup(regs);
286 printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
287 regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
290 void jmr3927_irc_irqdispatch(struct pt_regs *regs)
294 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
295 tx_branch_likely_bug_fixup(regs);
297 if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
299 jmr3927_spurious(regs);
303 irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
305 do_IRQ(irq + JMR3927_IRQ_IRC, regs);
308 static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
310 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
313 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
314 if (istat & (1 << i)) {
315 irq = JMR3927_IRQ_IOC + i;
321 static struct irqaction ioc_action = {
322 jmr3927_ioc_interrupt, 0, 0, "IOC", NULL, NULL,
325 static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
327 unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
330 for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
331 if (istat & (1 << i)) {
332 irq = JMR3927_IRQ_ISAC + i;
338 static struct irqaction isac_action = {
339 jmr3927_isac_interrupt, 0, 0, "ISAC", NULL, NULL,
343 static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
345 printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
347 static struct irqaction isaerr_action = {
348 jmr3927_isaerr_interrupt, 0, 0, "ISA error", NULL, NULL,
351 static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
353 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
354 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
355 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
357 static struct irqaction pcierr_action = {
358 jmr3927_pcierr_interrupt, 0, 0, "PCI error", NULL, NULL,
361 int jmr3927_ether1_irq = 0;
363 void jmr3927_irq_init(u32 irq_base);
364 void jmr3927_irq_setup(void)
366 /* look for io board's presence */
367 int have_isac = jmr3927_have_isac();
369 /* Now, interrupt control disabled, */
370 /* all IRC interrupts are masked, */
371 /* all IRC interrupt mode are Low Active. */
375 /* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
376 /* temporary enable interrupt control */
377 tx3927_ircptr->cer = 1;
378 /* ETHER1 Int. Is High-Active. */
379 if (tx3927_ircptr->ssr & (1 << 0))
380 jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
381 #if 0 /* INT3 may be asserted by ether0 (even after reboot...) */
382 else if (tx3927_ircptr->ssr & (1 << 3))
383 jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
385 /* disable interrupt control */
386 tx3927_ircptr->cer = 0;
388 /* Ether1: High Active */
389 if (jmr3927_ether1_irq) {
390 int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
391 tx3927_ircptr->cr[ether1_irc / 8] |=
392 TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
396 /* mask all IOC interrupts */
397 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
398 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
399 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
402 /* mask all ISAC interrupts */
403 jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
404 /* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
405 jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
408 /* clear PCI Soft interrupts */
409 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
410 /* clear PCI Reset interrupts */
411 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
413 /* enable interrupt control */
414 tx3927_ircptr->cer = TX3927_IRCER_ICE;
415 tx3927_ircptr->imr = irc_elevel;
417 jmr3927_irq_init(NR_ISA_IRQS);
419 set_except_vector(0, jmr3927_IRQ);
421 /* setup irq space */
422 add_tb_irq_space(&jmr3927_isac_irqspace);
423 add_tb_irq_space(&jmr3927_ioc_irqspace);
424 add_tb_irq_space(&jmr3927_irc_irqspace);
426 /* setup IOC interrupt 1 (PCI, MODEM) */
427 setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
430 setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
431 setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
435 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
438 /* enable all CPU interrupt bits. */
439 set_c0_status(ST0_IM); /* IE bit is still 0. */
442 void (*irq_setup)(void);
443 void __init init_IRQ(void)
447 extern void breakpoint(void);
448 extern void set_debug_traps(void);
450 puts("Wait for gdb client connection ...\n");
455 /* invoke board-specific irq setup */
459 hw_irq_controller jmr3927_irq_controller = {
462 jmr3927_irq_shutdown,
467 NULL /* no affinity stuff for UP */
471 jmr3927_irq_init(u32 irq_base)
473 extern irq_desc_t irq_desc[];
476 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
477 irq_desc[i].status = IRQ_DISABLED;
478 irq_desc[i].action = NULL;
479 irq_desc[i].depth = 1;
480 irq_desc[i].handler = &jmr3927_irq_controller;
483 jmr3927_irq_base = irq_base;
486 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
487 static int tx_branch_likely_bug_count = 0;
488 static int have_tx_branch_likely_bug = 0;
489 void tx_branch_likely_bug_fixup(struct pt_regs *regs)
491 /* TX39/49-BUG: Under this condition, the insn in delay slot
492 of the branch likely insn is executed (not nullified) even
493 the branch condition is false. */
494 if (!have_tx_branch_likely_bug)
496 if ((regs->cp0_epc & 0xfff) == 0xffc &&
497 KSEGX(regs->cp0_epc) != KSEG0 &&
498 KSEGX(regs->cp0_epc) != KSEG1) {
499 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
500 /* beql,bnel,blezl,bgtzl */
501 /* bltzl,bgezl,blezall,bgezall */
503 if ((insn & 0xf0000000) == 0x50000000 ||
504 (insn & 0xfc0e0000) == 0x04020000 ||
505 (insn & 0xf3fe0000) == 0x41020000) {
507 tx_branch_likely_bug_count++;
509 "fix branch-likery bug in %s (insn %08x)\n",
510 current->comm, insn);