1 /***********************************************************************
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
6 * Copyright (C) 2000-2001 Toshiba Corporation
8 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
10 * Define the pci_ops for JMR3927.
12 * Much of the code is derived from the original DDB5074 port by
13 * Geert Uytterhoeven <geert@sonycom.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 ***********************************************************************
36 #include <linux/types.h>
37 #include <linux/pci.h>
38 #include <linux/kernel.h>
39 #include <linux/init.h>
41 #include <asm/addrspace.h>
42 #include <asm/pci_channel.h>
43 #include <asm/jmr3927/jmr3927.h>
44 #include <asm/debug.h>
46 struct resource pci_io_resource = {
48 0x1000, /* reserve regacy I/O space */
49 0x1000 + JMR3927_PCIIO_SIZE -1,
52 struct resource pci_mem_resource = {
55 JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE -1,
58 extern struct pci_ops jmr3927_pci_ops;
60 struct pci_channel mips_pci_channels[] = {
61 { &jmr3927_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 0xff },
62 { NULL, NULL, NULL, NULL, NULL}
65 unsigned int pcibios_assign_all_busses(void)
71 mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where, int *flagsp)
73 if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
76 tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) |
77 ((dev_fn & 0xff) << 0x08) |
79 /* clear M_ABORT and Disable M_ABORT Int. */
80 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
81 tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
86 check_abort(int flags)
88 int code = PCIBIOS_SUCCESSFUL;
89 if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
90 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
91 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
92 code =PCIBIOS_DEVICE_NOT_FOUND;
98 * We can't address 8 and 16 bit words directly. Instead we have to
99 * read/write a 32bit word and mask/modify the data we actually want.
101 static int jmr3927_pcibios_read_config_byte (struct pci_dev *dev,
106 unsigned char bus, func_num;
108 db_assert((where & 3) == 0);
109 db_assert(where < (1 << 8));
111 /* check if the bus is top-level */
112 if (dev->bus->parent != NULL) {
113 bus = dev->bus->number;
119 func_num = PCI_FUNC(dev->devfn);
120 if (mkaddr(bus, dev->devfn, where, &flags))
122 *val = *(volatile u8 *)((ulong)&tx3927_pcicptr->icd | (where&3));
123 return check_abort(flags);
126 static int jmr3927_pcibios_read_config_word (struct pci_dev *dev,
131 unsigned char bus, func_num;
134 return PCIBIOS_BAD_REGISTER_NUMBER;
136 db_assert((where & 3) == 0);
137 db_assert(where < (1 << 8));
139 /* check if the bus is top-level */
140 if (dev->bus->parent != NULL) {
141 bus = dev->bus->number;
147 func_num = PCI_FUNC(dev->devfn);
148 if (mkaddr(bus, dev->devfn, where, &flags))
150 *val = le16_to_cpu(*(volatile u16 *)((ulong)&tx3927_pcicptr->icd | (where&3)));
151 return check_abort(flags);
154 static int jmr3927_pcibios_read_config_dword (struct pci_dev *dev,
159 unsigned char bus, func_num;
162 return PCIBIOS_BAD_REGISTER_NUMBER;
164 db_assert((where & 3) == 0);
165 db_assert(where < (1 << 8));
167 /* check if the bus is top-level */
168 if (dev->bus->parent != NULL) {
169 bus = dev->bus->number;
175 func_num = PCI_FUNC(dev->devfn);
176 if (mkaddr(bus, dev->devfn, where, &flags))
178 *val = le32_to_cpu(tx3927_pcicptr->icd);
179 return check_abort(flags);
182 static int jmr3927_pcibios_write_config_byte (struct pci_dev *dev,
187 unsigned char bus, func_num;
189 /* check if the bus is top-level */
190 if (dev->bus->parent != NULL) {
191 bus = dev->bus->number;
197 func_num = PCI_FUNC(dev->devfn);
198 if (mkaddr(bus, dev->devfn, where, &flags))
200 *(volatile u8 *)((ulong)&tx3927_pcicptr->icd | (where&3)) = val;
201 return check_abort(flags);
204 static int jmr3927_pcibios_write_config_word (struct pci_dev *dev,
209 unsigned char bus, func_num;
212 return PCIBIOS_BAD_REGISTER_NUMBER;
214 /* check if the bus is top-level */
215 if (dev->bus->parent != NULL) {
216 bus = dev->bus->number;
222 func_num = PCI_FUNC(dev->devfn);
223 if (mkaddr(bus, dev->devfn, where, &flags))
225 *(volatile u16 *)((ulong)&tx3927_pcicptr->icd | (where&3)) = cpu_to_le16(val);
226 return check_abort(flags);
229 static int jmr3927_pcibios_write_config_dword (struct pci_dev *dev,
234 unsigned char bus, func_num;
237 return PCIBIOS_BAD_REGISTER_NUMBER;
239 /* check if the bus is top-level */
240 if (dev->bus->parent != NULL) {
241 bus = dev->bus->number;
247 func_num = PCI_FUNC(dev->devfn);
248 if (mkaddr(bus, dev->devfn, where, &flags))
250 tx3927_pcicptr->icd = cpu_to_le32(val);
251 return check_abort(flags);
253 struct pci_ops jmr3927_pci_ops = {
254 jmr3927_pcibios_read_config_byte,
255 jmr3927_pcibios_read_config_word,
256 jmr3927_pcibios_read_config_dword,
257 jmr3927_pcibios_write_config_byte,
258 jmr3927_pcibios_write_config_word,
259 jmr3927_pcibios_write_config_dword
262 #ifndef JMR3927_INIT_INDIRECT_PCI
263 inline unsigned long tc_readl(volatile __u32 *addr)
267 inline void tc_writel(unsigned long data, volatile __u32 *addr)
272 unsigned long tc_readl(volatile __u32 *addr)
276 addr = PHYSADDR(addr);
277 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)addr;
278 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =
279 (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG;
280 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
281 val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
282 /* clear by setting */
283 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
286 void tc_writel(unsigned long data, volatile __u32 *addr)
288 addr = PHYSADDR(addr);
289 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = cpu_to_le32(data);
290 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)addr;
291 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =
292 (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG;
293 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
294 /* clear by setting */
295 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
297 unsigned char tx_ioinb(unsigned char *addr)
304 ioaddr = (unsigned long)addr;
305 offset = ioaddr & 0x3;
308 else if (offset == 1)
310 else if (offset == 2)
312 else if (offset == 3)
314 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr;
315 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =
316 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
317 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
318 val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
320 /* clear by setting */
321 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
324 void tx_iooutb(unsigned long data, unsigned char *addr)
330 data = data | (data << 8) | (data << 16) | (data << 24);
331 ioaddr = (unsigned long)addr;
332 offset = ioaddr & 0x3;
335 else if (offset == 1)
337 else if (offset == 2)
339 else if (offset == 3)
341 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = data;
342 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr;
343 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =
344 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
345 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
346 /* clear by setting */
347 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
349 unsigned short tx_ioinw(unsigned short *addr)
356 ioaddr = (unsigned long)addr;
357 offset = ioaddr & 0x3;
360 else if (offset == 2)
362 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr;
363 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =
364 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
365 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
366 val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
368 /* clear by setting */
369 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
373 void tx_iooutw(unsigned long data, unsigned short *addr)
379 data = data | (data << 16);
380 ioaddr = (unsigned long)addr;
381 offset = ioaddr & 0x3;
384 else if (offset == 2)
386 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = data;
387 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr;
388 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =
389 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
390 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
391 /* clear by setting */
392 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
394 unsigned long tx_ioinl(unsigned int *addr)
399 ioaddr = (unsigned long)addr;
400 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr;
401 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =
402 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG;
403 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
404 val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
405 /* clear by setting */
406 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
409 void tx_iooutl(unsigned long data, unsigned int *addr)
413 ioaddr = (unsigned long)addr;
414 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = cpu_to_le32(data);
415 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr;
416 *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =
417 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG;
418 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
419 /* clear by setting */
420 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
422 void tx_insbyte(unsigned char *addr,void *buffer,unsigned int count)
424 unsigned char *ptr = (unsigned char *) buffer;
427 *ptr++ = tx_ioinb(addr);
430 void tx_insword(unsigned short *addr,void *buffer,unsigned int count)
432 unsigned short *ptr = (unsigned short *) buffer;
435 *ptr++ = tx_ioinw(addr);
438 void tx_inslong(unsigned int *addr,void *buffer,unsigned int count)
440 unsigned long *ptr = (unsigned long *) buffer;
443 *ptr++ = tx_ioinl(addr);
446 void tx_outsbyte(unsigned char *addr,void *buffer,unsigned int count)
448 unsigned char *ptr = (unsigned char *) buffer;
451 tx_iooutb(*ptr++,addr);
454 void tx_outsword(unsigned short *addr,void *buffer,unsigned int count)
456 unsigned short *ptr = (unsigned short *) buffer;
459 tx_iooutw(*ptr++,addr);
462 void tx_outslong(unsigned int *addr,void *buffer,unsigned int count)
464 unsigned long *ptr = (unsigned long *) buffer;
467 tx_iooutl(*ptr++,addr);