arch/mips/kernel/r4k_fpu.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996, 1998, 2000 by Ralf Baechle
   7  *
   8  * Multi-arch abstraction and asm macros for easier reading:
   9  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  10  *
  11  *  Carsten Langgaard, carstenl@mips.com
  12  *  Copyright (C) 2000 MIPS Technologies, Inc.
  13  */
  14 #include <asm/asm.h>
  15 #include <asm/errno.h>
  16 #include <asm/fpregdef.h>
  17 #include <asm/mipsregs.h>
  18 #include <asm/offset.h>
  19 #include <asm/regdef.h>
  20
  21 #define EX(a,b)                                                 \
  22 9:      a,b;                                                    \
  23         .section __ex_table,"a";                                \
  24         PTR     9b, fault;                                      \
  25         .previous
  26
  27         .set    noreorder
  28         .set    mips3
  29         /* Save floating point context */
  30 LEAF(_save_fp_context)
  31         li      v0, 0                                   # assume success
  32         cfc1    t1,fcr31
  33
  34         /* Store the 16 even double precision registers */
  35         EX(sdc1 $f0,(SC_FPREGS+0)(a0))
  36         EX(sdc1 $f2,(SC_FPREGS+16)(a0))
  37         EX(sdc1 $f4,(SC_FPREGS+32)(a0))
  38         EX(sdc1 $f6,(SC_FPREGS+48)(a0))
  39         EX(sdc1 $f8,(SC_FPREGS+64)(a0))
  40         EX(sdc1 $f10,(SC_FPREGS+80)(a0))
  41         EX(sdc1 $f12,(SC_FPREGS+96)(a0))
  42         EX(sdc1 $f14,(SC_FPREGS+112)(a0))
  43         EX(sdc1 $f16,(SC_FPREGS+128)(a0))
  44         EX(sdc1 $f18,(SC_FPREGS+144)(a0))
  45         EX(sdc1 $f20,(SC_FPREGS+160)(a0))
  46         EX(sdc1 $f22,(SC_FPREGS+176)(a0))
  47         EX(sdc1 $f24,(SC_FPREGS+192)(a0))
  48         EX(sdc1 $f26,(SC_FPREGS+208)(a0))
  49         EX(sdc1 $f28,(SC_FPREGS+224)(a0))
  50         EX(sdc1 $f30,(SC_FPREGS+240)(a0))
  51         EX(sw   t1,SC_FPC_CSR(a0))
  52         cfc1    t0,$0                           # implementation/version
  53
  54         jr      ra
  55         .set    nomacro
  56          EX(sw  t0,SC_FPC_EIR(a0))
  57         .set    macro
  58         END(_save_fp_context)
  59
  60 /*
  61  * Restore FPU state:
  62  *  - fp gp registers
  63  *  - cp1 status/control register
  64  *
  65  * We base the decision which registers to restore from the signal stack
  66  * frame on the current content of c0_status, not on the content of the
  67  * stack frame which might have been changed by the user.
  68  */
  69 LEAF(_restore_fp_context)
  70         li      v0, 0                                   # assume success
  71         EX(lw   t0,SC_FPC_CSR(a0))
  72
  73         /*
  74          * Restore the 16 even double precision registers
  75          * when cp1 was enabled in the cp0 status register.
  76          */
  77         EX(ldc1 $f0,(SC_FPREGS+0)(a0))
  78         EX(ldc1 $f2,(SC_FPREGS+16)(a0))
  79         EX(ldc1 $f4,(SC_FPREGS+32)(a0))
  80         EX(ldc1 $f6,(SC_FPREGS+48)(a0))
  81         EX(ldc1 $f8,(SC_FPREGS+64)(a0))
  82         EX(ldc1 $f10,(SC_FPREGS+80)(a0))
  83         EX(ldc1 $f12,(SC_FPREGS+96)(a0))
  84         EX(ldc1 $f14,(SC_FPREGS+112)(a0))
  85         EX(ldc1 $f16,(SC_FPREGS+128)(a0))
  86         EX(ldc1 $f18,(SC_FPREGS+144)(a0))
  87         EX(ldc1 $f20,(SC_FPREGS+160)(a0))
  88         EX(ldc1 $f22,(SC_FPREGS+176)(a0))
  89         EX(ldc1 $f24,(SC_FPREGS+192)(a0))
  90         EX(ldc1 $f26,(SC_FPREGS+208)(a0))
  91         EX(ldc1 $f28,(SC_FPREGS+224)(a0))
  92         EX(ldc1 $f30,(SC_FPREGS+240)(a0))
  93         jr      ra
  94          ctc1   t0,fcr31
  95         END(_restore_fp_context)
  96         .set    reorder
  97
  98         .type   fault@function
  99         .ent    fault
 100 fault:  li      v0, -EFAULT
 101         jr      ra
 102         .end    fault