arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/bootinfo.h>
  19 #include <asm/cacheops.h>
  20 #include <asm/cpu.h>
  21 #include <asm/io.h>
  22 #include <asm/page.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/r4kcache.h>
  25 #include <asm/system.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/war.h>
  28
  29 static unsigned long icache_size, dcache_size, scache_size;
  30
  31 /*
  32  * Dummy cache handling routines for machines without boardcaches
  33  */
  34 static void no_sc_noop(void) {}
  35
  36 static struct bcache_ops no_sc_ops = {
  37         .bc_enable = (void *)no_sc_noop,
  38         .bc_disable = (void *)no_sc_noop,
  39         .bc_wback_inv = (void *)no_sc_noop,
  40         .bc_inv = (void *)no_sc_noop
  41 };
  42
  43 struct bcache_ops *bcops = &no_sc_ops;
  44
  45 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x2010)
  46 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x2020)
  47
  48 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  49 do {                                                                    \
  50         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  51                 *(volatile unsigned long *)KSEG1;                       \
  52         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  53                 __asm__ __volatile__("nop;nop;nop;nop");                \
  54 } while (0)
  55
  56 static void (* r4k_blast_dcache_page)(unsigned long addr);
  57
  58 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
  59 {
  60         R4600_HIT_CACHEOP_WAR_IMPL;
  61         blast_dcache32_page(addr);
  62 }
  63
  64 static inline void r4k_blast_dcache_page_setup(void)
  65 {
  66         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
  67
  68         if (dc_lsize == 16)
  69                 r4k_blast_dcache_page = blast_dcache16_page;
  70         else if (dc_lsize == 32)
  71                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  72 }
  73
  74 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
  75
  76 static void r4k_blast_dcache_page_indexed_setup(void)
  77 {
  78         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
  79
  80         if (dc_lsize == 16)
  81                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  82         else if (dc_lsize == 32)
  83                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  84 }
  85
  86 static void (* r4k_blast_dcache)(void);
  87
  88 static inline void r4k_blast_dcache_setup(void)
  89 {
  90         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
  91
  92         if (dc_lsize == 16)
  93                 r4k_blast_dcache = blast_dcache16;
  94         else if (dc_lsize == 32)
  95                 r4k_blast_dcache = blast_dcache32;
  96 }
  97
  98 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
  99 #define JUMP_TO_ALIGN(order) \
 100         __asm__ __volatile__( \
 101                 "b\t1f\n\t" \
 102                 ".align\t" #order "\n\t" \
 103                 "1:\n\t" \
 104                 )
 105 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 106 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 107
 108 static inline void blast_r4600_v1_icache32(void)
 109 {
 110         unsigned long flags;
 111
 112         local_irq_save(flags);
 113         blast_icache32();
 114         local_irq_restore(flags);
 115 }
 116
 117 static inline void tx49_blast_icache32(void)
 118 {
 119         unsigned long start = KSEG0;
 120         unsigned long end = start + current_cpu_data.icache.waysize;
 121         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 122         unsigned long ws_end = current_cpu_data.icache.ways <<
 123                                current_cpu_data.icache.waybit;
 124         unsigned long ws, addr;
 125
 126         CACHE32_UNROLL32_ALIGN2;
 127         /* I'm in even chunk.  blast odd chunks */
 128         for (ws = 0; ws < ws_end; ws += ws_inc)
 129                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 130                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 131         CACHE32_UNROLL32_ALIGN;
 132         /* I'm in odd chunk.  blast even chunks */
 133         for (ws = 0; ws < ws_end; ws += ws_inc)
 134                 for (addr = start; addr < end; addr += 0x400 * 2)
 135                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 136 }
 137
 138 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 139 {
 140         unsigned long flags;
 141
 142         local_irq_save(flags);
 143         blast_icache32_page_indexed(page);
 144         local_irq_restore(flags);
 145 }
 146
 147 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 148 {
 149         unsigned long start = page;
 150         unsigned long end = start + PAGE_SIZE;
 151         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 152         unsigned long ws_end = current_cpu_data.icache.ways <<
 153                                current_cpu_data.icache.waybit;
 154         unsigned long ws, addr;
 155
 156         CACHE32_UNROLL32_ALIGN2;
 157         /* I'm in even chunk.  blast odd chunks */
 158         for (ws = 0; ws < ws_end; ws += ws_inc)
 159                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 160                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 161         CACHE32_UNROLL32_ALIGN;
 162         /* I'm in odd chunk.  blast even chunks */
 163         for (ws = 0; ws < ws_end; ws += ws_inc)
 164                 for (addr = start; addr < end; addr += 0x400 * 2)
 165                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 166 }
 167
 168 static void (* r4k_blast_icache_page)(unsigned long addr);
 169
 170 static inline void r4k_blast_icache_page_setup(void)
 171 {
 172         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 173
 174         if (ic_lsize == 16)
 175                 r4k_blast_icache_page = blast_icache16_page;
 176         else if (ic_lsize == 32)
 177                 r4k_blast_icache_page = blast_icache32_page;
 178         else if (ic_lsize == 64)
 179                 r4k_blast_icache_page = blast_icache64_page;
 180 }
 181
 182 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 183
 184 static inline void r4k_blast_icache_page_indexed_setup(void)
 185 {
 186         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 187
 188         if (ic_lsize == 16)
 189                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 190         else if (ic_lsize == 32) {
 191                 if (TX49XX_ICACHE_INDEX_INV_WAR)
 192                         r4k_blast_icache_page_indexed =
 193                                 tx49_blast_icache32_page_indexed;
 194                 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 195                         r4k_blast_icache_page_indexed =
 196                                 blast_icache32_r4600_v1_page_indexed;
 197                 else
 198                         r4k_blast_icache_page_indexed =
 199                                 blast_icache32_page_indexed;
 200         } else if (ic_lsize == 64)
 201                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 202 }
 203
 204 static void (* r4k_blast_icache)(void);
 205
 206 static inline void r4k_blast_icache_setup(void)
 207 {
 208         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 209
 210         if (ic_lsize == 16)
 211                 r4k_blast_icache = blast_icache16;
 212         else if (ic_lsize == 32) {
 213                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 214                         r4k_blast_icache = blast_r4600_v1_icache32;
 215                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 216                         r4k_blast_icache = tx49_blast_icache32;
 217                 else if (ic_lsize == 32)
 218                         r4k_blast_icache = blast_icache32;
 219         } else if (ic_lsize == 64)
 220                 r4k_blast_icache = blast_icache64;
 221 }
 222
 223 static void (* r4k_blast_scache_page)(unsigned long addr);
 224
 225 static inline void r4k_blast_scache_page_setup(void)
 226 {
 227         unsigned long sc_lsize = current_cpu_data.scache.linesz;
 228
 229         if (sc_lsize == 16)
 230                 r4k_blast_scache_page = blast_scache16_page;
 231         else if (sc_lsize == 32)
 232                 r4k_blast_scache_page = blast_scache32_page;
 233         else if (sc_lsize == 64)
 234                 r4k_blast_scache_page = blast_scache64_page;
 235         else if (sc_lsize == 128)
 236                 r4k_blast_scache_page = blast_scache128_page;
 237 }
 238
 239 static void (* r4k_blast_scache)(void);
 240
 241 static inline void r4k_blast_scache_setup(void)
 242 {
 243         unsigned long sc_lsize = current_cpu_data.scache.linesz;
 244
 245         if (sc_lsize == 16)
 246                 r4k_blast_scache = blast_scache16;
 247         else if (sc_lsize == 32)
 248                 r4k_blast_scache = blast_scache32;
 249         else if (sc_lsize == 64)
 250                 r4k_blast_scache = blast_scache64;
 251         else if (sc_lsize == 128)
 252                 r4k_blast_scache = blast_scache128;
 253 }
 254
 255 static void r4k_flush_cache_all(void)
 256 {
 257         if (!cpu_has_dc_aliases)
 258                 return;
 259
 260         r4k_blast_dcache();
 261         r4k_blast_icache();
 262 }
 263
 264 static void r4k___flush_cache_all(void)
 265 {
 266         r4k_blast_dcache();
 267         r4k_blast_icache();
 268
 269         switch (current_cpu_data.cputype) {
 270         case CPU_R4000SC:
 271         case CPU_R4000MC:
 272         case CPU_R4400SC:
 273         case CPU_R4400MC:
 274         case CPU_R10000:
 275         case CPU_R12000:
 276                 r4k_blast_scache();
 277         }
 278 }
 279
 280 static void r4k_flush_cache_range(struct mm_struct *mm,
 281         unsigned long start, unsigned long end)
 282 {
 283         if (!cpu_has_dc_aliases)
 284                 return;
 285
 286         if (cpu_context(smp_processor_id(), mm) != 0) {
 287                 r4k_blast_dcache();
 288                 r4k_blast_icache();
 289         }
 290 }
 291
 292 static void r4k_flush_cache_mm(struct mm_struct *mm)
 293 {
 294         if (!cpu_has_dc_aliases)
 295                 return;
 296
 297         if (!cpu_context(smp_processor_id(), mm))
 298                 return;
 299
 300         r4k_blast_dcache();
 301         r4k_blast_icache();
 302
 303         /*
 304          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 305          * only flush the primary caches but R10000 and R12000 behave sane ...
 306          */
 307         if (current_cpu_data.cputype == CPU_R4000SC ||
 308             current_cpu_data.cputype == CPU_R4000MC ||
 309             current_cpu_data.cputype == CPU_R4400SC ||
 310             current_cpu_data.cputype == CPU_R4400MC)
 311                 r4k_blast_scache();
 312 }
 313
 314 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 315                                         unsigned long page)
 316 {
 317         int exec = vma->vm_flags & VM_EXEC;
 318         struct mm_struct *mm = vma->vm_mm;
 319         pgd_t *pgdp;
 320         pmd_t *pmdp;
 321         pte_t *ptep;
 322
 323         /*
 324          * If ownes no valid ASID yet, cannot possibly have gotten
 325          * this page into the cache.
 326          */
 327         if (cpu_context(smp_processor_id(), mm) == 0)
 328                 return;
 329
 330         page &= PAGE_MASK;
 331         pgdp = pgd_offset(mm, page);
 332         pmdp = pmd_offset(pgdp, page);
 333         ptep = pte_offset(pmdp, page);
 334
 335         /*
 336          * If the page isn't marked valid, the page cannot possibly be
 337          * in the cache.
 338          */
 339         if (!(pte_val(*ptep) & _PAGE_PRESENT))
 340                 return;
 341
 342         /*
 343          * Doing flushes for another ASID than the current one is
 344          * too difficult since stupid R4k caches do a TLB translation
 345          * for every cache flush operation.  So we do indexed flushes
 346          * in that case, which doesn't overly flush the cache too much.
 347          */
 348         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 349                 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 350                         r4k_blast_dcache_page(page);
 351                 if (exec)
 352                         r4k_blast_icache_page(page);
 353
 354                 return;
 355         }
 356
 357         /*
 358          * Do indexed flush, too much work to get the (possible) TLB refills
 359          * to work correctly.
 360          */
 361         page = (KSEG0 + (page & (dcache_size - 1)));
 362         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 363                 r4k_blast_dcache_page_indexed(page);
 364         if (exec) {
 365                 if (cpu_has_vtag_icache) {
 366                         int cpu = smp_processor_id();
 367
 368                         if (cpu_context(cpu, vma->vm_mm) != 0)
 369                                 drop_mmu_context(vma->vm_mm, cpu);
 370                 } else
 371                         r4k_blast_icache_page_indexed(page);
 372         }
 373 }
 374
 375 static void r4k_flush_data_cache_page(unsigned long addr)
 376 {
 377         r4k_blast_dcache_page(addr);
 378 }
 379
 380 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 381 {
 382         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 383         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 384         unsigned long addr, aend;
 385
 386         if (!cpu_has_ic_fills_f_dc) {
 387                 if (end - start > dcache_size)
 388                         r4k_blast_dcache();
 389                 else {
 390                         addr = start & ~(dc_lsize - 1);
 391                         aend = (end - 1) & ~(dc_lsize - 1);
 392
 393                         while (1) {
 394                                 /* Hit_Writeback_Inv_D */
 395                                 protected_writeback_dcache_line(addr);
 396                                 if (addr == aend)
 397                                         break;
 398                                 addr += dc_lsize;
 399                         }
 400                 }
 401         }
 402
 403         if (end - start > icache_size)
 404                 r4k_blast_icache();
 405         else {
 406                 addr = start & ~(ic_lsize - 1);
 407                 aend = (end - 1) & ~(ic_lsize - 1);
 408                 while (1) {
 409                         /* Hit_Invalidate_I */
 410                         protected_flush_icache_line(addr);
 411                         if (addr == aend)
 412                                 break;
 413                         addr += ic_lsize;
 414                 }
 415         }
 416 }
 417
 418 /*
 419  * Ok, this seriously sucks.  We use them to flush a user page but don't
 420  * know the virtual address, so we have to blast away the whole icache
 421  * which is significantly more expensive than the real thing.  Otoh we at
 422  * least know the kernel address of the page so we can flush it
 423  * selectivly.
 424  */
 425 static void r4k_flush_icache_page(struct vm_area_struct *vma,
 426         struct page *page)
 427 {
 428         /*
 429          * If there's no context yet, or the page isn't executable, no icache
 430          * flush is needed.
 431          */
 432         if (!(vma->vm_flags & VM_EXEC))
 433                 return;
 434
 435         /*
 436          * Tricky ...  Because we don't know the virtual address we've got the
 437          * choice of either invalidating the entire primary and secondary
 438          * caches or invalidating the secondary caches also.  With the subset
 439          * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
 440          * secondary cache will result in any entries in the primary caches
 441          * also getting invalidated which hopefully is a bit more economical.
 442          */
 443         if (cpu_has_subset_pcaches) {
 444                 unsigned long addr = (unsigned long) page_address(page);
 445
 446                 r4k_blast_scache_page(addr);
 447                 ClearPageDcacheDirty(page);
 448
 449                 return;
 450         }
 451
 452         if (!cpu_has_ic_fills_f_dc) {
 453                 unsigned long addr = (unsigned long) page_address(page);
 454                 r4k_blast_dcache_page(addr);
 455                 ClearPageDcacheDirty(page);
 456         }
 457
 458         /*
 459          * We're not sure of the virtual address(es) involved here, so
 460          * we have to flush the entire I-cache.
 461          */
 462         if (cpu_has_vtag_icache) {
 463                 int cpu = smp_processor_id();
 464
 465                 if (cpu_context(cpu, vma->vm_mm) != 0)
 466                         drop_mmu_context(vma->vm_mm, cpu);
 467         } else
 468                 r4k_blast_icache();
 469 }
 470
 471 #ifdef CONFIG_NONCOHERENT_IO
 472
 473 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 474 {
 475         unsigned long end, a;
 476
 477         /* Catch bad driver code */
 478         BUG_ON(size == 0);
 479
 480         if (cpu_has_subset_pcaches) {
 481                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 482
 483                 if (size >= scache_size) {
 484                         r4k_blast_scache();
 485                         return;
 486                 }
 487
 488                 a = addr & ~(sc_lsize - 1);
 489                 end = (addr + size - 1) & ~(sc_lsize - 1);
 490                 while (1) {
 491                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 492                         if (a == end)
 493                                 break;
 494                         a += sc_lsize;
 495                 }
 496                 return;
 497         }
 498
 499         /*
 500          * Either no secondary cache or the available caches don't have the
 501          * subset property so we have to flush the primary caches
 502          * explicitly
 503          */
 504         if (size >= dcache_size) {
 505                 r4k_blast_dcache();
 506         } else {
 507                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 508
 509                 R4600_HIT_CACHEOP_WAR_IMPL;
 510                 a = addr & ~(dc_lsize - 1);
 511                 end = (addr + size - 1) & ~(dc_lsize - 1);
 512                 while (1) {
 513                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 514                         if (a == end)
 515                                 break;
 516                         a += dc_lsize;
 517                 }
 518         }
 519
 520         bc_wback_inv(addr, size);
 521 }
 522
 523 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 524 {
 525         unsigned long end, a;
 526
 527         /* Catch bad driver code */
 528         BUG_ON(size == 0);
 529
 530         if (cpu_has_subset_pcaches) {
 531                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 532
 533                 if (size >= scache_size) {
 534                         r4k_blast_scache();
 535                         return;
 536                 }
 537
 538                 a = addr & ~(sc_lsize - 1);
 539                 end = (addr + size - 1) & ~(sc_lsize - 1);
 540                 while (1) {
 541                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 542                         if (a == end)
 543                                 break;
 544                         a += sc_lsize;
 545                 }
 546                 return;
 547         }
 548
 549         if (size >= dcache_size) {
 550                 r4k_blast_dcache();
 551         } else {
 552                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 553
 554                 R4600_HIT_CACHEOP_WAR_IMPL;
 555                 a = addr & ~(dc_lsize - 1);
 556                 end = (addr + size - 1) & ~(dc_lsize - 1);
 557                 while (1) {
 558                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 559                         if (a == end)
 560                                 break;
 561                         a += dc_lsize;
 562                 }
 563         }
 564
 565         bc_inv(addr, size);
 566 }
 567 #endif /* CONFIG_NONCOHERENT_IO */
 568
 569 /*
 570  * While we're protected against bad userland addresses we don't care
 571  * very much about what happens in that case.  Usually a segmentation
 572  * fault will dump the process later on anyway ...
 573  */
 574 static void r4k_flush_cache_sigtramp(unsigned long addr)
 575 {
 576         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 577         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 578
 579         R4600_HIT_CACHEOP_WAR_IMPL;
 580         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 581         protected_flush_icache_line(addr & ~(ic_lsize - 1));
 582         if (MIPS4K_ICACHE_REFILL_WAR) {
 583                 __asm__ __volatile__ (
 584                         ".set push\n\t"
 585                         ".set noat\n\t"
 586                         ".set mips3\n\t"
 587 #if CONFIG_MIPS32
 588                         "la     $at,1f\n\t"
 589 #endif
 590 #if CONFIG_MIPS64
 591                         "dla    $at,1f\n\t"
 592 #endif
 593                         "cache  %0,($at)\n\t"
 594                         "nop; nop; nop\n"
 595                         "1:\n\t"
 596                         ".set pop"
 597                         :
 598                         : "i" (Hit_Invalidate_I));
 599         }
 600         if (MIPS_CACHE_SYNC_WAR)
 601                 __asm__ __volatile__ ("sync");
 602 }
 603
 604 static void r4k_flush_icache_all(void)
 605 {
 606         if (cpu_has_vtag_icache)
 607                 r4k_blast_icache();
 608 }
 609
 610 static inline void rm7k_erratum31(void)
 611 {
 612         const unsigned long ic_lsize = 32;
 613         unsigned long addr;
 614
 615         /* RM7000 erratum #31. The icache is screwed at startup. */
 616         write_c0_taglo(0);
 617         write_c0_taghi(0);
 618
 619         for (addr = KSEG0; addr <= KSEG0 + 4096; addr += ic_lsize) {
 620                 __asm__ __volatile__ (
 621                         ".set noreorder\n\t"
 622                         ".set mips3\n\t"
 623                         "cache\t%1, 0(%0)\n\t"
 624                         "cache\t%1, 0x1000(%0)\n\t"
 625                         "cache\t%1, 0x2000(%0)\n\t"
 626                         "cache\t%1, 0x3000(%0)\n\t"
 627                         "cache\t%2, 0(%0)\n\t"
 628                         "cache\t%2, 0x1000(%0)\n\t"
 629                         "cache\t%2, 0x2000(%0)\n\t"
 630                         "cache\t%2, 0x3000(%0)\n\t"
 631                         "cache\t%1, 0(%0)\n\t"
 632                         "cache\t%1, 0x1000(%0)\n\t"
 633                         "cache\t%1, 0x2000(%0)\n\t"
 634                         "cache\t%1, 0x3000(%0)\n\t"
 635                         ".set\tmips0\n\t"
 636                         ".set\treorder\n\t"
 637                         :
 638                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 639         }
 640 }
 641
 642 static char *way_string[] = { NULL, "direct mapped", "2-way", "3-way", "4-way",
 643         "5-way", "6-way", "7-way", "8-way"
 644 };
 645
 646 static void __init probe_pcache(void)
 647 {
 648         struct cpuinfo_mips *c = &current_cpu_data;
 649         unsigned int config = read_c0_config();
 650         unsigned int prid = read_c0_prid();
 651         unsigned long config1;
 652         unsigned int lsize;
 653
 654         switch (c->cputype) {
 655         case CPU_R4600:                 /* QED style two way caches? */
 656         case CPU_R4700:
 657         case CPU_R5000:
 658         case CPU_NEVADA:
 659                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 660                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 661                 c->icache.ways = 2;
 662                 c->icache.waybit = ffs(icache_size/2) - 1;
 663
 664                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 665                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 666                 c->dcache.ways = 2;
 667                 c->dcache.waybit= ffs(dcache_size/2) - 1;
 668
 669                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 670                 break;
 671
 672         case CPU_R5432:
 673         case CPU_R5500:
 674                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 675                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 676                 c->icache.ways = 2;
 677                 c->icache.waybit= 0;
 678
 679                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 680                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 681                 c->dcache.ways = 2;
 682                 c->dcache.waybit = 0;
 683
 684                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 685                 break;
 686
 687         case CPU_TX49XX:
 688                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 689                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 690                 c->icache.ways = 4;
 691                 c->icache.waybit= 0;
 692
 693                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 694                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 695                 c->dcache.ways = 4;
 696                 c->dcache.waybit = 0;
 697
 698                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 699                 break;
 700
 701         case CPU_R4000PC:
 702         case CPU_R4000SC:
 703         case CPU_R4000MC:
 704         case CPU_R4400PC:
 705         case CPU_R4400SC:
 706         case CPU_R4400MC:
 707         case CPU_R4300:
 708                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 709                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 710                 c->icache.ways = 1;
 711                 c->icache.waybit = 0;   /* doesn't matter */
 712
 713                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 714                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 715                 c->dcache.ways = 1;
 716                 c->dcache.waybit = 0;   /* does not matter */
 717
 718                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 719                 break;
 720
 721         case CPU_R10000:
 722         case CPU_R12000:
 723                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 724                 c->icache.linesz = 64;
 725                 c->icache.ways = 2;
 726                 c->icache.waybit = 0;
 727
 728                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 729                 c->dcache.linesz = 32;
 730                 c->dcache.ways = 2;
 731                 c->dcache.waybit = 0;
 732
 733                 c->options |= MIPS_CPU_PREFETCH;
 734                 break;
 735
 736         case CPU_VR4133:
 737                 write_c0_config(config & ~CONF_EB);
 738         case CPU_VR4131:
 739                 /* Workaround for cache instruction bug of VR4131 */
 740                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 741                     c->processor_id == 0x0c82U) {
 742                         config &= ~0x00000030U;
 743                         config |= 0x00410000U;
 744                         write_c0_config(config);
 745                 }
 746                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 747                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 748                 c->icache.ways = 2;
 749                 c->icache.waybit = ffs(icache_size/2) - 1;
 750
 751                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 752                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 753                 c->dcache.ways = 2;
 754                 c->dcache.waybit = ffs(dcache_size/2) - 1;
 755
 756                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 757                 break;
 758
 759         case CPU_VR41XX:
 760         case CPU_VR4111:
 761         case CPU_VR4121:
 762         case CPU_VR4122:
 763         case CPU_VR4181:
 764         case CPU_VR4181A:
 765                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 766                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 767                 c->icache.ways = 1;
 768                 c->icache.waybit = 0;   /* doesn't matter */
 769
 770                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 771                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 772                 c->dcache.ways = 1;
 773                 c->dcache.waybit = 0;   /* does not matter */
 774
 775                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 776                 break;
 777
 778         case CPU_RM7000:
 779                 rm7k_erratum31();
 780
 781         case CPU_RM9000:
 782                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 783                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 784                 c->icache.ways = 4;
 785                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
 786
 787                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 788                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 789                 c->dcache.ways = 4;
 790                 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
 791
 792 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
 793                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 794 #endif
 795                 c->options |= MIPS_CPU_PREFETCH;
 796                 break;
 797
 798         default:
 799                 if (!(config & MIPS_CONF_M))
 800                         panic("Don't know how to probe P-caches on this cpu.");
 801
 802                 /*
 803                  * So we seem to be a MIPS32 or MIPS64 CPU
 804                  * So let's probe the I-cache ...
 805                  */
 806                 config1 = read_c0_config1();
 807
 808                 if ((lsize = ((config1 >> 19) & 7)))
 809                         c->icache.linesz = 2 << lsize;
 810                 else
 811                         c->icache.linesz = lsize;
 812                 c->icache.sets = 64 << ((config1 >> 22) & 7);
 813                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 814
 815                 icache_size = c->icache.sets *
 816                               c->icache.ways *
 817                               c->icache.linesz;
 818                 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
 819
 820                 if (config & 0x8)               /* VI bit */
 821                         c->icache.flags |= MIPS_CACHE_VTAG;
 822
 823                 /*
 824                  * Now probe the MIPS32 / MIPS64 data cache.
 825                  */
 826                 c->dcache.flags = 0;
 827
 828                 if ((lsize = ((config1 >> 10) & 7)))
 829                         c->dcache.linesz = 2 << lsize;
 830                 else
 831                         c->dcache.linesz= lsize;
 832                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
 833                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 834
 835                 dcache_size = c->dcache.sets *
 836                               c->dcache.ways *
 837                               c->dcache.linesz;
 838                 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
 839
 840                 c->options |= MIPS_CPU_PREFETCH;
 841                 break;
 842         }
 843
 844         /*
 845          * Processor configuration sanity check for the R4000SC erratum
 846          * #5.  With page sizes larger than 32kB there is no possibility
 847          * to get a VCE exception anymore so we don't care about this
 848          * misconfiguration.  The case is rather theoretical anyway;
 849          * presumably no vendor is shipping his hardware in the "bad"
 850          * configuration.
 851          */
 852         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
 853             !(config & CONF_SC) && c->icache.linesz != 16 &&
 854             PAGE_SIZE <= 0x8000)
 855                 panic("Improper R4000SC processor configuration detected");
 856
 857         /* compute a couple of other cache variables */
 858         c->icache.waysize = icache_size / c->icache.ways;
 859         c->dcache.waysize = dcache_size / c->dcache.ways;
 860
 861         c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
 862         c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
 863
 864         /*
 865          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
 866          * 2-way virtually indexed so normally would suffer from aliases.  So
 867          * normally they'd suffer from aliases but magic in the hardware deals
 868          * with that for us so we don't need to take care ourselves.
 869          */
 870         if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000)
 871                 if (c->dcache.waysize > PAGE_SIZE)
 872                         c->dcache.flags |= MIPS_CACHE_ALIASES;
 873
 874         switch (c->cputype) {
 875         case CPU_20KC:
 876                 /*
 877                  * Some older 20Kc chips doesn't have the 'VI' bit in
 878                  * the config register.
 879                  */
 880                 c->icache.flags |= MIPS_CACHE_VTAG;
 881                 break;
 882
 883         case CPU_AU1500:
 884                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
 885                 break;
 886         }
 887
 888         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
 889                icache_size >> 10,
 890                cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
 891                way_string[c->icache.ways], c->icache.linesz);
 892
 893         printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
 894                dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
 895 }
 896
 897 /*
 898  * If you even _breathe_ on this function, look at the gcc output and make sure
 899  * it does not pop things on and off the stack for the cache sizing loop that
 900  * executes in KSEG1 space or else you will crash and burn badly.  You have
 901  * been warned.
 902  */
 903 static int __init probe_scache(void)
 904 {
 905         extern unsigned long stext;
 906         unsigned long flags, addr, begin, end, pow2;
 907         unsigned int config = read_c0_config();
 908         struct cpuinfo_mips *c = &current_cpu_data;
 909         int tmp;
 910
 911         if (config & CONF_SC)
 912                 return 0;
 913
 914         begin = (unsigned long) &stext;
 915         begin &= ~((4 * 1024 * 1024) - 1);
 916         end = begin + (4 * 1024 * 1024);
 917
 918         /*
 919          * This is such a bitch, you'd think they would make it easy to do
 920          * this.  Away you daemons of stupidity!
 921          */
 922         local_irq_save(flags);
 923
 924         /* Fill each size-multiple cache line with a valid tag. */
 925         pow2 = (64 * 1024);
 926         for (addr = begin; addr < end; addr = (begin + pow2)) {
 927                 unsigned long *p = (unsigned long *) addr;
 928                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
 929                 pow2 <<= 1;
 930         }
 931
 932         /* Load first line with zero (therefore invalid) tag. */
 933         write_c0_taglo(0);
 934         write_c0_taghi(0);
 935         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
 936         cache_op(Index_Store_Tag_I, begin);
 937         cache_op(Index_Store_Tag_D, begin);
 938         cache_op(Index_Store_Tag_SD, begin);
 939
 940         /* Now search for the wrap around point. */
 941         pow2 = (128 * 1024);
 942         tmp = 0;
 943         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
 944                 cache_op(Index_Load_Tag_SD, addr);
 945                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
 946                 if (!read_c0_taglo())
 947                         break;
 948                 pow2 <<= 1;
 949         }
 950         local_irq_restore(flags);
 951         addr -= begin;
 952
 953         scache_size = addr;
 954         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
 955         c->scache.ways = 1;
 956         c->dcache.waybit = 0;           /* does not matter */
 957
 958         return 1;
 959 }
 960
 961 typedef int (*probe_func_t)(unsigned long);
 962 extern int r5k_sc_init(void);
 963 extern int rm7k_sc_init(void);
 964
 965 static void __init setup_scache(void)
 966 {
 967         struct cpuinfo_mips *c = &current_cpu_data;
 968         unsigned int config = read_c0_config();
 969         probe_func_t probe_scache_kseg1;
 970         int sc_present = 0;
 971
 972         /*
 973          * Do the probing thing on R4000SC and R4400SC processors.  Other
 974          * processors don't have a S-cache that would be relevant to the
 975          * Linux memory managment.
 976          */
 977         switch (c->cputype) {
 978         case CPU_R4000SC:
 979         case CPU_R4000MC:
 980         case CPU_R4400SC:
 981         case CPU_R4400MC:
 982                 probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
 983                 sc_present = probe_scache_kseg1(config);
 984                 if (sc_present)
 985                         c->options |= MIPS_CPU_CACHE_CDEX_S;
 986                 break;
 987
 988         case CPU_R10000:
 989         case CPU_R12000:
 990                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
 991                 c->scache.linesz = 64 << ((config >> 13) & 1);
 992                 c->scache.ways = 2;
 993                 c->scache.waybit= 0;
 994                 sc_present = 1;
 995                 break;
 996
 997         case CPU_R5000:
 998         case CPU_NEVADA:
 999 #ifdef CONFIG_R5000_CPU_SCACHE
1000                 r5k_sc_init();
1001 #endif
1002                 return;
1003
1004         case CPU_RM7000:
1005         case CPU_RM9000:
1006 #ifdef CONFIG_RM7000_CPU_SCACHE
1007                 rm7k_sc_init();
1008 #endif
1009                 return;
1010
1011         default:
1012                 sc_present = 0;
1013         }
1014
1015         if (!sc_present)
1016                 return;
1017
1018         if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1019              c->isa_level == MIPS_CPU_ISA_M64) &&
1020             !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1021                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1022
1023         /* compute a couple of other cache variables */
1024         c->scache.waysize = scache_size / c->scache.ways;
1025
1026         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1027
1028         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1029                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1030
1031         c->options |= MIPS_CPU_SUBSET_CACHES;
1032 }
1033
1034 static inline void coherency_setup(void)
1035 {
1036         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1037
1038         /*
1039          * c0_status.cu=0 specifies that updates by the sc instruction use
1040          * the coherency mode specified by the TLB; 1 means cachable
1041          * coherent update on write will be used.  Not all processors have
1042          * this bit and; some wire it to zero, others like Toshiba had the
1043          * silly idea of putting something else there ...
1044          */
1045         switch (current_cpu_data.cputype) {
1046         case CPU_R4000PC:
1047         case CPU_R4000SC:
1048         case CPU_R4000MC:
1049         case CPU_R4400PC:
1050         case CPU_R4400SC:
1051         case CPU_R4400MC:
1052                 clear_c0_config(CONF_CU);
1053                 break;
1054         }
1055
1056 }
1057
1058 void __init ld_mmu_r4xx0(void)
1059 {
1060         extern void build_clear_page(void);
1061         extern void build_copy_page(void);
1062         extern char except_vec2_generic;
1063         struct cpuinfo_mips *c = &current_cpu_data;
1064
1065         /* Default cache error handler for R4000 and R5000 family */
1066         memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
1067         memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
1068
1069         probe_pcache();
1070         setup_scache();
1071
1072         if (c->dcache.sets * c->dcache.ways > PAGE_SIZE)
1073                 c->dcache.flags |= MIPS_CACHE_ALIASES;
1074
1075         r4k_blast_dcache_page_setup();
1076         r4k_blast_dcache_page_indexed_setup();
1077         r4k_blast_dcache_setup();
1078         r4k_blast_icache_page_setup();
1079         r4k_blast_icache_page_indexed_setup();
1080         r4k_blast_icache_setup();
1081         r4k_blast_scache_page_setup();
1082         r4k_blast_scache_setup();
1083
1084         /*
1085          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1086          * This code supports virtually indexed processors and will be
1087          * unnecessarily inefficient on physically indexed processors.
1088          */
1089         shm_align_mask = max_t( unsigned long,
1090                                 c->dcache.sets * c->dcache.linesz - 1,
1091                                 PAGE_SIZE - 1);
1092
1093         _flush_cache_all        = r4k_flush_cache_all;
1094         ___flush_cache_all      = r4k___flush_cache_all;
1095         _flush_cache_mm         = r4k_flush_cache_mm;
1096         _flush_cache_page       = r4k_flush_cache_page;
1097         _flush_icache_page      = r4k_flush_icache_page;
1098         _flush_cache_range      = r4k_flush_cache_range;
1099
1100         _flush_cache_sigtramp   = r4k_flush_cache_sigtramp;
1101         _flush_icache_all       = r4k_flush_icache_all;
1102         _flush_data_cache_page  = r4k_flush_data_cache_page;
1103         _flush_icache_range     = r4k_flush_icache_range;
1104
1105 #ifdef CONFIG_NONCOHERENT_IO
1106         _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1107         _dma_cache_wback        = r4k_dma_cache_wback_inv;
1108         _dma_cache_inv          = r4k_dma_cache_inv;
1109 #endif
1110
1111         __flush_cache_all();
1112         coherency_setup();
1113
1114         build_clear_page();
1115         build_copy_page();
1116 }