2 * Copyright 2002 Momentum Computer
3 * Author: Matthew Dharm <mdharm@momenco.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/config.h>
26 #include <linux/types.h>
27 #include <linux/pci.h>
28 #include <linux/kernel.h>
29 #include <linux/slab.h>
30 #include <linux/version.h>
33 #include <asm/mv64340.h>
35 #include <linux/init.h>
42 * These functions and structures provide the BIOS scan and mapping of the PCI
46 #define MAX_PCI_DEVS 10
48 void mv64340_board_pcibios_fixup_bus(struct pci_bus* c);
50 /* Functions to implement "pci ops" */
51 static int galileo_pcibios_read_config_word(struct pci_dev *dev,
52 int offset, u16 * val);
53 static int galileo_pcibios_read_config_byte(struct pci_dev *dev,
54 int offset, u8 * val);
55 static int galileo_pcibios_read_config_dword(struct pci_dev *dev,
56 int offset, u32 * val);
57 static int galileo_pcibios_write_config_byte(struct pci_dev *dev,
59 static int galileo_pcibios_write_config_word(struct pci_dev *dev,
61 static int galileo_pcibios_write_config_dword(struct pci_dev *dev,
63 static void galileo_pcibios_set_master(struct pci_dev *dev);
66 * General-purpose PCI functions.
73 * Check if the pci device that are trying to access does really exists
74 * on the evaluation board.
77 * bus - bus number (0 for PCI 0 ; 1 for PCI 1)
78 * dev - number of device on the specific pci bus
81 * 0 - if OK , 1 - if failure
83 static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev)
85 /* Accessing device 31 crashes the MV-64340. */
92 * galileo_pcibios_(read/write)_config_(dword/word/byte) -
94 * reads/write a dword/word/byte register from the configuration space
97 * Note that bus 0 and bus 1 are local, and we assume all other busses are
98 * bridged from bus 1. This is a safe assumption, since any other
99 * configuration will require major modifications to the CP7000G
103 * dev - device number
104 * offset - register offset in the configuration space
105 * val - value to be written / read
108 * PCIBIOS_SUCCESSFUL when operation was succesfull
109 * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous
110 * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned
113 static int galileo_pcibios_read_config_dword(struct pci_dev *device,
114 int offset, u32* val)
117 uint32_t address_reg, data_reg;
120 bus = device->bus->number;
121 dev = PCI_SLOT(device->devfn);
122 func = PCI_FUNC(device->devfn);
124 /* verify the range */
125 if (pci_range_ck(bus, dev))
126 return PCIBIOS_DEVICE_NOT_FOUND;
128 /* select the MV-64340 registers to communicate with the PCI bus */
130 address_reg = MV64340_PCI_0_CONFIG_ADDR;
131 data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG;
133 address_reg = MV64340_PCI_1_CONFIG_ADDR;
134 data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG;
137 address = (bus << 16) | (dev << 11) | (func << 8) |
138 (offset & 0xfc) | 0x80000000;
140 /* start the configuration cycle */
141 MV_WRITE(address_reg, address);
144 MV_READ(data_reg, val);
146 return PCIBIOS_SUCCESSFUL;
150 static int galileo_pcibios_read_config_word(struct pci_dev *device,
151 int offset, u16* val)
154 uint32_t address_reg, data_reg;
157 bus = device->bus->number;
158 dev = PCI_SLOT(device->devfn);
159 func = PCI_FUNC(device->devfn);
161 /* verify the range */
162 if (pci_range_ck(bus, dev))
163 return PCIBIOS_DEVICE_NOT_FOUND;
165 /* select the MV-64340 registers to communicate with the PCI bus */
167 address_reg = MV64340_PCI_0_CONFIG_ADDR;
168 data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG;
170 address_reg = MV64340_PCI_1_CONFIG_ADDR;
171 data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG;
174 address = (bus << 16) | (dev << 11) | (func << 8) |
175 (offset & 0xfc) | 0x80000000;
177 /* start the configuration cycle */
178 MV_WRITE(address_reg, address);
181 MV_READ_16(data_reg + (offset & 0x3), val);
183 return PCIBIOS_SUCCESSFUL;
186 static int galileo_pcibios_read_config_byte(struct pci_dev *device,
190 uint32_t address_reg, data_reg;
193 bus = device->bus->number;
194 dev = PCI_SLOT(device->devfn);
195 func = PCI_FUNC(device->devfn);
197 /* verify the range */
198 if (pci_range_ck(bus, dev))
199 return PCIBIOS_DEVICE_NOT_FOUND;
201 /* select the MV-64340 registers to communicate with the PCI bus */
203 address_reg = MV64340_PCI_0_CONFIG_ADDR;
204 data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG;
206 address_reg = MV64340_PCI_1_CONFIG_ADDR;
207 data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG;
210 address = (bus << 16) | (dev << 11) | (func << 8) |
211 (offset & 0xfc) | 0x80000000;
213 /* start the configuration cycle */
214 MV_WRITE(address_reg, address);
217 MV_READ_8(data_reg + (offset & 0x3), val);
219 return PCIBIOS_SUCCESSFUL;
222 static int galileo_pcibios_write_config_dword(struct pci_dev *device,
226 uint32_t address_reg, data_reg;
229 bus = device->bus->number;
230 dev = PCI_SLOT(device->devfn);
231 func = PCI_FUNC(device->devfn);
233 /* verify the range */
234 if (pci_range_ck(bus, dev))
235 return PCIBIOS_DEVICE_NOT_FOUND;
237 /* select the MV-64340 registers to communicate with the PCI bus */
239 address_reg = MV64340_PCI_0_CONFIG_ADDR;
240 data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG;
242 address_reg = MV64340_PCI_1_CONFIG_ADDR;
243 data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG;
246 address = (bus << 16) | (dev << 11) | (func << 8) |
247 (offset & 0xfc) | 0x80000000;
249 /* start the configuration cycle */
250 MV_WRITE(address_reg, address);
253 MV_WRITE(data_reg, val);
255 return PCIBIOS_SUCCESSFUL;
259 static int galileo_pcibios_write_config_word(struct pci_dev *device,
263 uint32_t address_reg, data_reg;
266 bus = device->bus->number;
267 dev = PCI_SLOT(device->devfn);
268 func = PCI_FUNC(device->devfn);
270 /* verify the range */
271 if (pci_range_ck(bus, dev))
272 return PCIBIOS_DEVICE_NOT_FOUND;
274 /* select the MV-64340 registers to communicate with the PCI bus */
276 address_reg = MV64340_PCI_0_CONFIG_ADDR;
277 data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG;
279 address_reg = MV64340_PCI_1_CONFIG_ADDR;
280 data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG;
283 address = (bus << 16) | (dev << 11) | (func << 8) |
284 (offset & 0xfc) | 0x80000000;
286 /* start the configuration cycle */
287 MV_WRITE(address_reg, address);
290 MV_WRITE_16(data_reg + (offset & 0x3), val);
292 return PCIBIOS_SUCCESSFUL;
295 static int galileo_pcibios_write_config_byte(struct pci_dev *device,
299 uint32_t address_reg, data_reg;
302 bus = device->bus->number;
303 dev = PCI_SLOT(device->devfn);
304 func = PCI_FUNC(device->devfn);
306 /* verify the range */
307 if (pci_range_ck(bus, dev))
308 return PCIBIOS_DEVICE_NOT_FOUND;
310 /* select the MV-64340 registers to communicate with the PCI bus */
312 address_reg = MV64340_PCI_0_CONFIG_ADDR;
313 data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG;
315 address_reg = MV64340_PCI_1_CONFIG_ADDR;
316 data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG;
319 address = (bus << 16) | (dev << 11) | (func << 8) |
320 (offset & 0xfc) | 0x80000000;
322 /* start the configuration cycle */
323 MV_WRITE(address_reg, address);
326 MV_WRITE_8(data_reg + (offset & 0x3), val);
328 return PCIBIOS_SUCCESSFUL;
331 static void galileo_pcibios_set_master(struct pci_dev *dev)
335 galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd);
336 cmd |= PCI_COMMAND_MASTER;
337 galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd);
340 /* Externally-expected functions. Do not change function names */
342 int pcibios_enable_resources(struct pci_dev *dev)
349 galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd);
351 for (idx = 0; idx < 6; idx++) {
352 r = &dev->resource[idx];
353 if (!r->start && r->end) {
355 "PCI: Device %s not available because of "
356 "resource collisions\n", dev->slot_name);
359 if (r->flags & IORESOURCE_IO)
360 cmd |= PCI_COMMAND_IO;
361 if (r->flags & IORESOURCE_MEM)
362 cmd |= PCI_COMMAND_MEMORY;
364 if (cmd != old_cmd) {
365 galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd);
369 * Let's fix up the latency timer and cache line size here. Cache
370 * line size = 32 bytes / sizeof dword (4) = 8.
371 * Latency timer must be > 8. 32 is random but appears to work.
373 galileo_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
375 printk(KERN_WARNING "PCI setting cache line size to 8 from "
377 galileo_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
380 galileo_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp1);
382 printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n",
384 galileo_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER,
392 int pcibios_enable_device(struct pci_dev *dev, int mask)
394 return pcibios_enable_resources(dev);
397 void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
398 struct resource *res, int resource)
405 new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
407 reg = PCI_BASE_ADDRESS_0 + 4 * resource;
408 } else if (resource == PCI_ROM_RESOURCE) {
409 res->flags |= PCI_ROM_ADDRESS_ENABLE;
410 reg = dev->rom_base_reg;
413 * Somebody might have asked allocation of a non-standard
419 pci_write_config_dword(dev, reg, new);
420 pci_read_config_dword(dev, reg, &check);
422 ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK :
423 PCI_BASE_ADDRESS_MEM_MASK)) {
424 printk(KERN_ERR "PCI: Error while updating region "
425 "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
431 void pcibios_align_resource(void *data, struct resource *res,
432 unsigned long size, unsigned long align)
434 struct pci_dev *dev = data;
436 if (res->flags & IORESOURCE_IO) {
437 unsigned long start = res->start;
439 /* We need to avoid collisions with `mirrored' VGA ports
440 and other strange ISA hardware, so we always want the
441 addresses kilobyte aligned. */
443 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
444 " (%ld bytes)\n", dev->slot_name,
445 dev->resource - res, size);
448 start = (start + 1024 - 1) & ~(1024 - 1);
454 struct pci_ops galileo_pci_ops = {
455 galileo_pcibios_read_config_byte,
456 galileo_pcibios_read_config_word,
457 galileo_pcibios_read_config_dword,
458 galileo_pcibios_write_config_byte,
459 galileo_pcibios_write_config_word,
460 galileo_pcibios_write_config_dword
463 struct pci_fixup pcibios_fixups[] = {
467 void __init pcibios_fixup_bus(struct pci_bus *c)
469 mv64340_board_pcibios_fixup_bus(c);
472 void __init pcibios_init(void)
474 /* Reset PCI I/O and PCI MEM values */
475 ioport_resource.start = 0xe0000000;
476 ioport_resource.end = 0xe0000000 + 0x20000000 - 1;
477 iomem_resource.start = 0xc0000000;
478 iomem_resource.end = 0xc0000000 + 0x20000000 - 1;
480 pci_scan_bus(0, &galileo_pci_ops, NULL);
481 pci_scan_bus(1, &galileo_pci_ops, NULL);
484 unsigned __init int pcibios_assign_all_busses(void)
489 #endif /* CONFIG_PCI */