arch/mips/momentum/jaguar_atx/setup.c

   1 /*
   2  * setup.c
   3  *
   4  * BRIEF MODULE DESCRIPTION
   5  * Momentum Computer Jaguar-ATX board dependent boot routines
   6  *
   7  * Copyright (C) 1996, 1997, 2001  Ralf Baechle
   8  * Copyright (C) 2000 RidgeRun, Inc.
   9  * Copyright (C) 2001 Red Hat, Inc.
  10  * Copyright (C) 2002 Momentum Computer
  11  *
  12  * Author: Matthew Dharm, Momentum Computer
  13  *   mdharm@momenco.com
  14  *
  15  * Louis Hamilton, Red Hat, Inc.
  16  *   hamilton@redhat.com  [MIPS64 modifications]
  17  *
  18  * Author: RidgeRun, Inc.
  19  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  20  *
  21  * Copyright 2001 MontaVista Software Inc.
  22  * Author: jsun@mvista.com or jsun@junsun.net
  23  *
  24  *  This program is free software; you can redistribute  it and/or modify it
  25  *  under  the terms of  the GNU General  Public License as published by the
  26  *  Free Software Foundation;  either version 2 of the  License, or (at your
  27  *  option) any later version.
  28  *
  29  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  30  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  31  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  32  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  33  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  34  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  35  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  36  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  37  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  38  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  *  You should have received a copy of the  GNU General Public License along
  41  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  42  *  675 Mass Ave, Cambridge, MA 02139, USA.
  43  *
  44  */
  45 #include <linux/init.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/mc146818rtc.h>
  49 #include <linux/mm.h>
  50 #include <linux/swap.h>
  51 #include <linux/ioport.h>
  52 #include <linux/sched.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/pci.h>
  55 #include <linux/timex.h>
  56 #include <linux/vmalloc.h>
  57 #include <asm/time.h>
  58 #include <asm/bootinfo.h>
  59 #include <asm/page.h>
  60 #include <asm/bootinfo.h>
  61 #include <asm/io.h>
  62 #include <asm/irq.h>
  63 #include <asm/pci.h>
  64 #include <asm/processor.h>
  65 #include <asm/ptrace.h>
  66 #include <asm/reboot.h>
  67 #include <asm/mc146818rtc.h>
  68 #include <linux/version.h>
  69 #include <linux/bootmem.h>
  70 #include <linux/blk.h>
  71 #include <asm/mv64340.h>
  72 #include "jaguar_atx_fpga.h"
  73
  74
  75 unsigned long mv64340_base;
  76 extern unsigned long mv64340_sram_base;
  77 unsigned long cpu_clock;
  78
  79 /* These functions are used for rebooting or halting the machine*/
  80 extern void momenco_jaguar_restart(char *command);
  81 extern void momenco_jaguar_halt(void);
  82 extern void momenco_jaguar_power_off(void);
  83
  84 void momenco_time_init(void);
  85
  86 static char reset_reason;
  87
  88 #define ENTRYLO(x) ((pte_val(mk_pte_phys((x), PAGE_KERNEL_UNCACHED)) >> 6)|1)
  89
  90 void __init bus_error_init(void) { /* nothing */ }
  91
  92 /* setup code for a handoff from a version 2 PMON 2000 PROM */
  93 void PMON_v2_setup(void)
  94 {
  95         /* Some wired TLB entries for the MV64340 and perhiperals. The
  96            MV64340 is going to be hit on every IRQ anyway - there's
  97            absolutely no point in letting it be a random TLB entry, as
  98            it'll just cause needless churning of the TLB. And we use
  99            the other half for the serial port, which is just a PITA
 100            otherwise :)
 101
 102                 Device                  Physical        Virtual
 103                 MV64340 Internal Regs   0xf4000000      0xf4000000
 104                 Ocelot-C[S] PLD (CS0)   0xfc000000      0xfc000000
 105                 NVRAM (CS1)             0xfc800000      0xfc800000
 106                 UARTs (CS2)             0xfd000000      0xfd000000
 107                 Internal SRAM           0xfe000000      0xfe000000
 108                 M-Systems DOC (CS3)     0xff000000      0xff000000
 109         */
 110   printk("PMON_v2_setup\n");
 111
 112 #ifdef CONFIG_MIPS64
 113         /* marvell and extra space */
 114         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
 115         /* fpga, rtc, and uart */
 116         add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
 117         /* m-sys and internal SRAM */
 118         add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
 119
 120         mv64340_base = 0xfffffffff4000000;
 121         mv64340_sram_base = 0xfffffffffe000000;
 122 #else
 123         /* marvell and extra space */
 124         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
 125         /* fpga, rtc, and uart */
 126         add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
 127         /* m-sys and internal SRAM */
 128         add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
 129
 130         mv64340_base = 0xf4000000;
 131         mv64340_sram_base = 0xfe000000;
 132 #endif
 133 }
 134
 135 #define CONV_BCD_TO_BIN(val)    (((val) & 0xf) + (((val) >> 4) * 10))
 136 #define CONV_BIN_TO_BCD(val)    (((val) % 10) + (((val) / 10) << 4))
 137
 138 unsigned long m48t37y_get_time(void)
 139 {
 140 #ifdef CONFIG_MIPS64
 141         unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
 142 #else
 143         unsigned char *rtc_base = (unsigned char*)0xfc800000;
 144 #endif
 145         unsigned int year, month, day, hour, min, sec;
 146
 147         /* stop the update */
 148         rtc_base[0x7ff8] = 0x40;
 149
 150         year = CONV_BCD_TO_BIN(rtc_base[0x7fff]);
 151         year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100;
 152
 153         month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]);
 154
 155         day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]);
 156
 157         hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]);
 158         min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]);
 159         sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]);
 160
 161         /* start the update */
 162         rtc_base[0x7ff8] = 0x00;
 163
 164         return mktime(year, month, day, hour, min, sec);
 165 }
 166
 167 int m48t37y_set_time(unsigned long sec)
 168 {
 169 #ifdef CONFIG_MIPS64
 170         unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
 171 #else
 172         unsigned char *rtc_base = (unsigned char*)0xfc800000;
 173 #endif
 174         struct rtc_time tm;
 175
 176         /* convert to a more useful format -- note months count from 0 */
 177         to_tm(sec, &tm);
 178         tm.tm_mon += 1;
 179
 180         /* enable writing */
 181         rtc_base[0x7ff8] = 0x80;
 182
 183         /* year */
 184         rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100);
 185         rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100);
 186
 187         /* month */
 188         rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon);
 189
 190         /* day */
 191         rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday);
 192
 193         /* hour/min/sec */
 194         rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour);
 195         rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min);
 196         rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec);
 197
 198         /* day of week -- not really used, but let's keep it up-to-date */
 199         rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1);
 200
 201         /* disable writing */
 202         rtc_base[0x7ff8] = 0x00;
 203
 204         return 0;
 205 }
 206
 207 void momenco_timer_setup(struct irqaction *irq)
 208 {
 209         setup_irq(8, irq);
 210 }
 211
 212 void momenco_time_init(void)
 213 {
 214         mips_hpt_frequency = cpu_clock / 2;
 215         board_timer_setup = momenco_timer_setup;
 216
 217         rtc_get_time = m48t37y_get_time;
 218         rtc_set_time = m48t37y_set_time;
 219 }
 220
 221 void __init momenco_jaguar_atx_setup(void)
 222 {
 223         unsigned int tmpword;
 224
 225         board_time_init = momenco_time_init;
 226
 227         _machine_restart = momenco_jaguar_restart;
 228         _machine_halt = momenco_jaguar_halt;
 229         _machine_power_off = momenco_jaguar_power_off;
 230
 231         /*
 232          * initrd_start = (ulong)jaguar_initrd_start;
 233          * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
 234          * initrd_below_start_ok = 1;
 235          */
 236
 237         /* do handoff reconfiguration */
 238         PMON_v2_setup();
 239
 240         /* shut down ethernet ports, just to be sure our memory doesn't get
 241          * corrupted by random ethernet traffic.
 242          */
 243         MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
 244         MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
 245         MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
 246         MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
 247         MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
 248         MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
 249         do {}
 250           while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
 251         do {}
 252           while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
 253         do {}
 254           while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
 255         do {}
 256           while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
 257         do {}
 258           while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
 259         do {}
 260           while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
 261         MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
 262         MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
 263         MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
 264
 265         /* Turn off the Bit-Error LED */
 266         JAGUAR_FPGA_WRITE(0x80, CLR);
 267
 268         tmpword = JAGUAR_FPGA_READ(BOARDREV);
 269         if (tmpword < 26)
 270                 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
 271                         'A'+tmpword);
 272         else
 273                 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
 274                         tmpword);
 275
 276         tmpword = JAGUAR_FPGA_READ(FPGA_REV);
 277         printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
 278         tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
 279         printk("Reset reason: 0x%x\n", tmpword);
 280         switch (tmpword) {
 281                 case 0x1:
 282                         printk("  - Power-up reset\n");
 283                         break;
 284                 case 0x2:
 285                         printk("  - Push-button reset\n");
 286                         break;
 287                 case 0x8:
 288                         printk("  - Watchdog reset\n");
 289                         break;
 290                 case 0x10:
 291                         printk("  - JTAG reset\n");
 292                         break;
 293                 default:
 294                         printk("  - Unknown reset cause\n");
 295         }
 296         reset_reason = tmpword;
 297         JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
 298
 299         tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
 300         printk("Board Status register: 0x%02x\n", tmpword);
 301         printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
 302         printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
 303
 304         /* 256MiB of RM9000x2 DDR */
 305 //      add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
 306
 307         /* 128MiB of MV-64340 DDR */
 308 //      add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
 309
 310         /* XXX Memory configuration should be picked up from PMON2k */
 311 #ifdef CONFIG_JAGUAR_DMALOW
 312         printk("Jaguar ATX DMA-low mode set\n");
 313         add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
 314         add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
 315 #else
 316         /* 128MiB of MV-64340 DDR RAM */
 317         printk("Jaguar ATX DMA-low mode is not set\n");
 318         add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
 319 #endif
 320
 321 #ifdef GEMDEBUG_TRACEBUFFER
 322         {
 323           unsigned int tbControl;
 324           tbControl =
 325             0 << 26 |  /* post trigger delay 0 */
 326                     0x2 << 16 |         /* sequential trace mode */
 327             //      0x0 << 16 |         /* non-sequential trace mode */
 328             //      0xf << 4 |          /* watchpoints disabled */
 329             2 << 2 |            /* armed */
 330             2 ;                 /* interrupt disabled  */
 331           printk ("setting     tbControl = %08lx\n", tbControl);
 332           write_32bit_cp0_set1_register($22, tbControl);
 333           __asm__ __volatile__(".set noreorder\n\t" \
 334                                "nop; nop; nop; nop; nop; nop;\n\t" \
 335                                "nop; nop; nop; nop; nop; nop;\n\t" \
 336                                ".set reorder\n\t");
 337
 338         }
 339 #endif
 340 }
 341
 342
 343 #ifndef CONFIG_MIPS64
 344 /* This needs to be one of the first initcalls, because no I/O port access
 345    can work before this */
 346 static int io_base_ioremap(void)
 347 {
 348         /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
 349         void *io_remap_range = ioremap(0xc0000000, 0x30000000);
 350
 351         printk("*** io_base_ioremap\n");
 352         if (!io_remap_range) {
 353                 panic("Could not ioremap I/O port range");
 354         }
 355         printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
 356         set_io_port_base(io_remap_range - 0xc0000000);
 357
 358         return 0;
 359 }
 360
 361 module_init(io_base_ioremap);
 362 #endif