4 * This was derived from the ppc4xx.h and contains
7 * Armin Kuster akuster@pacbell.net
11 * Copyright 2002 MontaVista Softare Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 * Version 1.0 (02/01/17) - A. Kuster
34 * Initial version - moved 405 specific out of the other core.h's
36 * Version 1.0 (02/08/02) - A. Kuster
37 * removed DCRN_UIC1_BASE to NP405L & H
39 * Version 1.2 (05/29/02) - Akuster
40 * removed DCRN_MALRXCTP2R etc, alread in ibmnp405.h
44 #ifndef __ASM_IBM405_H__
45 #define __ASM_IBM405_H__
48 #define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
49 #define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
52 #define BESR_DSES 0x80000000 /* Data-Side Error Status */
53 #define BESR_DMES 0x40000000 /* DMA Error Status */
54 #define BESR_RWS 0x20000000 /* Read/Write Status */
55 #define BESR_ETMASK 0x1C000000 /* Error Type */
62 /* Clock and power management shifts for emacs */
63 #define IBM_CPM_EMMII 0 /* Shift value for MII */
64 #define IBM_CPM_EMRX 1 /* Shift value for recv */
65 #define IBM_CPM_EMTX 2 /* Shift value for MAC */
68 #define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */
69 #define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */
71 #define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
73 #ifdef DCRN_CHPSR_BASE
74 #define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
77 #ifdef DCRN_CPMFR_BASE
78 #define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
81 #ifdef DCRN_CPMSR_BASE
82 #define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
83 #define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
87 /* Decompression Controller Address */
88 #define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0)
89 /* Decompression Controller Data */
90 #define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1)
92 #define DCRN_DCP0_CFGADDR 0x0
93 #define DCRN_DCP0_CFGDATA 0x0
97 /* DMA Channel Control Register 0 */
98 #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0)
99 #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */
100 /* DMA Destination Address Register 0 */
101 #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2)
102 /* DMA Source Address Register 0 */
103 #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3)
104 #ifdef DCRNCAP_DMA_CC
105 /* DMA Chained Count Register 0 */
106 #define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4)
108 #ifdef DCRNCAP_DMA_SG
109 /* DMA Scatter/Gather Descriptor Addr 0 */
110 #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4)
114 #ifdef DCRN_DMA1_BASE
115 /* DMA Channel Control Register 1 */
116 #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0)
117 #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */
118 /* DMA Destination Address Register 1 */
119 #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2)
120 /* DMA Source Address Register 1 */
121 #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */
122 #ifdef DCRNCAP_DMA_CC
123 /* DMA Chained Count Register 1 */
124 #define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4)
126 #ifdef DCRNCAP_DMA_SG
127 /* DMA Scatter/Gather Descriptor Addr 1 */
128 #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4)
132 #ifdef DCRN_DMA2_BASE
133 #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */
134 #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */
135 #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */
136 #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */
137 #ifdef DCRNCAP_DMA_CC
138 #define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */
140 #ifdef DCRNCAP_DMA_SG
141 #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */
145 #ifdef DCRN_DMA3_BASE
146 #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */
147 #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */
148 #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */
149 #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */
150 #ifdef DCRNCAP_DMA_CC
151 #define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */
153 #ifdef DCRNCAP_DMA_SG
154 #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */
158 #ifdef DCRN_DMASR_BASE
159 #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
160 #ifdef DCRNCAP_DMA_SG
161 #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
162 /* don't know if these two registers always exist if scatter/gather exists */
163 #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
164 #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
169 #define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */
170 #define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */
173 #ifdef DCRN_EXIER_BASE
174 #define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
177 #ifdef DCRN_EXISR_BASE
178 #define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
181 #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
182 #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
183 #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
184 #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
185 #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
186 #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
187 #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
188 #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
189 #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
190 #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
191 #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
192 #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
193 #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
194 #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
196 #ifdef DCRN_IOCR_BASE
197 #define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */
199 #define IOCR_E0TE 0x80000000
200 #define IOCR_E0LP 0x40000000
201 #define IOCR_E1TE 0x20000000
202 #define IOCR_E1LP 0x10000000
203 #define IOCR_E2TE 0x08000000
204 #define IOCR_E2LP 0x04000000
205 #define IOCR_E3TE 0x02000000
206 #define IOCR_E3LP 0x01000000
207 #define IOCR_E4TE 0x00800000
208 #define IOCR_E4LP 0x00400000
209 #define IOCR_EDT 0x00080000
210 #define IOCR_SOR 0x00040000
211 #define IOCR_EDO 0x00008000
212 #define IOCR_2XC 0x00004000
213 #define IOCR_ATC 0x00002000
214 #define IOCR_SPD 0x00001000
215 #define IOCR_BEM 0x00000800
216 #define IOCR_PTD 0x00000400
217 #define IOCR_ARE 0x00000080
218 #define IOCR_DRC 0x00000020
219 #define IOCR_RDM(x) (((x) & 0x3) << 3)
220 #define IOCR_TCS 0x00000004
221 #define IOCR_SCS 0x00000002
222 #define IOCR_SPC 0x00000001
224 #define DCRN_MALCR(base) (base + 0x0) /* MAL Configuration */
225 #define DCRN_MALDBR(base) ((base) + 0x3) /* Debug Register */
226 #define DCRN_MALESR(base) ((base) + 0x1) /* Error Status */
227 #define DCRN_MALIER(base) ((base) + 0x2) /* Interrupt Enable */
228 #define DCRN_MALTXCARR(base) ((base) + 0x5) /* TX Channed Active Reset Register */
229 #define DCRN_MALTXCASR(base) ((base) + 0x4) /* TX Channel Active Set Register */
230 #define DCRN_MALTXDEIR(base) ((base) + 0x7) /* Tx Descriptor Error Interrupt */
231 #define DCRN_MALTXEOBISR(base) ((base) + 0x6) /* Tx End of Buffer Interrupt Status */
232 #define DCRN_MALRXCARR(base) ((base) + 0x11) /* RX Channed Active Reset Register */
233 #define DCRN_MALRXCASR(base) ((base) + 0x10) /* RX Channel Active Set Register */
234 #define DCRN_MALRXDEIR(base) ((base) + 0x13) /* Rx Descriptor Error Interrupt */
235 #define DCRN_MALRXEOBISR(base) ((base) + 0x12) /* Rx End of Buffer Interrupt Status */
236 #define DCRN_MALRXCTP0R(base) ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */
237 #define DCRN_MALRXCTP1R(base) ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */
238 #define DCRN_MALTXCTP0R(base) ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */
239 #define DCRN_MALTXCTP1R(base) ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */
240 #define DCRN_MALTXCTP2R(base) ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */
241 #define DCRN_MALTXCTP3R(base) ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */
242 #define DCRN_MALRCBS0(base) ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */
243 #define DCRN_MALRCBS1(base) ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */
246 #define MALCR_MMSR 0x80000000 /* MAL Software reset */
247 #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
248 #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
249 #define MALCR_PLBP_3 0x00C00000 /* highest */
250 #define MALCR_GA 0x00200000 /* Guarded Active Bit */
251 #define MALCR_OA 0x00100000 /* Ordered Active Bit */
252 #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
253 #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
254 #define MALCR_PLBLT_2 0x00020000
255 #define MALCR_PLBLT_3 0x00010000
256 #define MALCR_PLBLT_4 0x00008000
257 #define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */
258 #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
259 #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
260 #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
261 #define MALCR_LEA 0x00000002 /* Locked Error Active */
262 #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
264 #define MALESR_EVB 0x80000000 /* Error Valid Bit */
265 #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
266 #define MALESR_DE 0x00100000 /* Descriptor Error */
267 #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
268 #define MALESR_OTE 0x00040000 /* OPB Timeout Error */
269 #define MALESR_OSE 0x00020000 /* OPB Slave Error */
270 #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
271 #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
272 #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
273 #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
274 #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
275 #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
277 #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
278 #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
279 #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
280 #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
281 #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
282 /* DCRN_MALTXEOBISR */
283 #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
284 #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
286 #ifdef DCRN_PLB0_BASE
287 #define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0)
288 #define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2)
289 /* doesn't exist on stb03xxx? */
290 #define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3)
293 #ifdef DCRN_PLB1_BASE
294 #define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0)
295 #define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1)
296 /* doesn't exist on stb03xxx? */
297 #define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2)
300 #ifdef DCRN_PLLMR_BASE
301 #define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
304 #ifdef DCRN_POB0_BASE
305 #define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
306 #define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2)
307 #define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
310 #define DCRN_UIC_SR(base) (base + 0x0)
311 #define DCRN_UIC_ER(base) (base + 0x2)
312 #define DCRN_UIC_CR(base) (base + 0x3)
313 #define DCRN_UIC_PR(base) (base + 0x4)
314 #define DCRN_UIC_TR(base) (base + 0x5)
315 #define DCRN_UIC_MSR(base) (base + 0x6)
316 #define DCRN_UIC_VR(base) (base + 0x7)
317 #define DCRN_UIC_VCR(base) (base + 0x8)
319 #ifdef DCRN_SDRAM0_BASE
320 #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
321 #define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
324 #ifdef DCRN_OCM0_BASE
325 #define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
326 #define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
327 #define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
328 #define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
331 #endif /* __ASM_IBM405_H__ */
332 #endif /* __KERNEL__ */