2 * arch/ppc/platforms/ibm_ocp.h
4 * Definitions for the on-chip peripherals on the IBM
5 * PPC405GP embedded processor.
7 * Copyright 2001 MontaVista Softare Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 #ifndef __ASM_IBM_OCP_H__
33 #define __ASM_IBM_OCP_H__
36 #include <linux/types.h>
39 // TODO: DEPRECATE THIS FILE !
51 typedef struct pcil0_regs {
52 struct pmm_regs pmm[3];
66 typedef struct NS16550 {
78 typedef struct iic_regs {
102 /* General purpose i/o */
104 typedef struct gpio_regs {
112 /* Structure of the memory mapped IDE control.
114 typedef struct ide_regs {
115 unsigned int si_stat; /* IDE status */
116 unsigned int si_intenable; /* IDE interrupt enable */
117 unsigned int si_control; /* IDE control */
118 unsigned int pad0[0x3d];
119 unsigned int si_c0rt; /* Chan 0 Register transfer timing */
120 unsigned int si_c0fpt; /* Chan 0 Fast PIO transfer timing */
121 unsigned int si_c0timo; /* Chan 0 timeout */
122 unsigned int pad1[2];
123 unsigned int si_c0d0u; /* Chan 0 UDMA transfer timing */
124 #define si_c0d0m si_c0d0u /* Chan 0 Multiword DMA timing */
126 unsigned int si_c0d1u; /* Chan 0 dev 1 UDMA timing */
127 #define si_c0d1m si_c0d1u /* Chan 0 dev 1 Multiword DMA timing */
128 unsigned int si_c0c; /* Chan 0 Control */
129 unsigned int si_c0s0; /* Chan 0 Status 0 */
130 unsigned int si_c0ie; /* Chan 0 Interrupt Enable */
131 unsigned int si_c0s1; /* Chan 0 Status 0 */
132 unsigned int pad4[4];
133 unsigned int si_c0dcm; /* Chan 0 DMA Command */
134 unsigned int si_c0tb; /* Chan 0 PRD Table base address */
135 unsigned int si_c0dct; /* Chan 0 DMA Count */
136 unsigned int si_c0da; /* Chan 0 DMA Address */
137 unsigned int si_c0sr; /* Chan 0 Slew Rate Output Control */
138 unsigned char pad5[0xa2];
139 unsigned short si_c0adc; /* Chan 0 Alt status/control */
140 unsigned char si_c0d; /* Chan 0 data */
141 unsigned char si_c0ef; /* Chan 0 error/features */
142 unsigned char si_c0sct; /* Chan 0 sector count */
143 unsigned char si_c0sn; /* Chan 0 sector number */
144 unsigned char si_c0cl; /* Chan 0 cylinder low */
145 unsigned char si_c0ch; /* Chan 0 cylinder high */
146 unsigned char si_c0dh; /* Chan 0 device/head */
147 unsigned char si_c0scm; /* Chan 0 status/command */
150 #endif /* __ASSEMBLY__ */
151 #endif /* __ASM_IBM_OCP_H__ */
152 #endif /* __KERNEL__ */