2 * arch/ppc/platforms/ocotea.c
4 * Ocotea board specific routines
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2003 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/types.h>
25 #include <linux/major.h>
26 #include <linux/blk.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/irq.h>
31 #include <linux/seq_file.h>
32 #include <linux/tty.h>
33 #include <linux/serial.h>
35 #include <asm/system.h>
36 #include <asm/pgtable.h>
40 #include <asm/machdep.h>
41 #include <asm/pci-bridge.h>
44 #include <asm/bootinfo.h>
45 #include <asm/ppc4xx_pic.h>
47 #include <kernel/ibm440gx_common.h>
49 extern void abort(void);
50 extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
51 extern int pckbd_getkeycode(unsigned int scancode);
52 extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
54 extern void gen550_progress(char *, unsigned short);
55 extern void gen550_init(int, struct serial_struct *);
57 /* Global Variables */
58 unsigned char __res[sizeof (bd_t)];
61 ocotea_calibrate_decr(void)
67 tb_ticks_per_jiffy = freq / HZ;
68 tb_to_us = mulhwu_scale_factor(freq, 1000000);
70 /* Set the time base to zero */
74 /* Clear any pending timer interrupts */
75 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
77 /* Enable decrementer interrupt */
78 mtspr(SPRN_TCR, TCR_DIE);
82 ocotea_show_cpuinfo(struct seq_file *m)
84 ibm440gx_show_cpuinfo(m);
85 seq_printf(m, "vendor\t\t: IBM\n");
86 seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
92 ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
94 static char pci_irq_table[][4] =
96 * PCI IDSEL/INTPIN->INTLINE
100 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
101 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
102 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
103 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
106 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
107 return PCI_IRQ_TABLE_LOOKUP;
110 #define PCIX_READW(offset) \
111 (readw((u32)pcix_reg_base+offset))
113 #define PCIX_WRITEW(value, offset) \
114 (writew(value, (u32)pcix_reg_base+offset))
116 #define PCIX_WRITEL(value, offset) \
117 (writel(value, (u32)pcix_reg_base+offset))
120 * FIXME: This is only here to "make it work". This will move
121 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
122 * configuration library. -Matt
125 ocotea_setup_pcix(void)
129 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
131 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
132 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
134 /* Disable all windows */
135 PCIX_WRITEL(0, PCIX0_POM0SA);
136 PCIX_WRITEL(0, PCIX0_POM1SA);
137 PCIX_WRITEL(0, PCIX0_POM2SA);
138 PCIX_WRITEL(0, PCIX0_PIM0SA);
139 PCIX_WRITEL(0, PCIX0_PIM0SAH);
140 PCIX_WRITEL(0, PCIX0_PIM1SA);
141 PCIX_WRITEL(0, PCIX0_PIM2SA);
142 PCIX_WRITEL(0, PCIX0_PIM2SAH);
144 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
145 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
146 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
147 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
148 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
149 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
151 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
152 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
153 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
154 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
160 ocotea_setup_hose(void)
162 struct pci_controller *hose;
164 /* Configure windows on the PCI-X host bridge */
167 hose = pcibios_alloc_controller();
172 hose->first_busno = 0;
173 hose->last_busno = 0xff;
175 hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
177 pci_init_resource(&hose->io_resource,
183 pci_init_resource(&hose->mem_resources[0],
184 OCOTEA_PCI_LOWER_MEM,
185 OCOTEA_PCI_UPPER_MEM,
189 hose->io_space.start = OCOTEA_PCI_LOWER_IO;
190 hose->io_space.end = OCOTEA_PCI_UPPER_IO;
191 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
192 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
194 (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
195 hose->io_base_virt = (void *)isa_io_base;
197 setup_indirect_pci(hose,
198 OCOTEA_PCI_CFGA_PLB32,
199 OCOTEA_PCI_CFGD_PLB32);
200 hose->set_cfg_type = 1;
202 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
204 ppc_md.pci_swizzle = common_swizzle;
205 ppc_md.pci_map_irq = ocotea_map_irq;
212 ocotea_early_serial_map(const struct ibm44x_clocks* clks)
214 struct serial_struct serial_req;
216 /* Setup ioremapped serial port access */
217 memset(&serial_req, 0, sizeof(serial_req));
219 serial_req.baud_base = clks->uart0 / 16;
222 serial_req.flags = ASYNC_BOOT_AUTOCONF;
223 serial_req.io_type = SERIAL_IO_MEM;
224 serial_req.iomem_base = ioremap64(PPC440GX_UART0_ADDR, 8);
225 serial_req.iomem_reg_shift = 0;
227 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
228 /* Configure debug serial access */
229 gen550_init(0, &serial_req);
232 if (early_serial_setup(&serial_req) != 0) {
233 printk("Early serial init of port 0 failed\n");
236 /* Assume early_serial_setup() doesn't modify serial_req */
238 serial_req.baud_base = clks->uart1 / 16;
241 serial_req.iomem_base = ioremap64(PPC440GX_UART1_ADDR, 8);
243 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
244 /* Configure debug serial access */
245 gen550_init(1, &serial_req);
248 if (early_serial_setup(&serial_req) != 0) {
249 printk("Early serial init of port 1 failed\n");
254 ocotea_setup_arch(void)
257 unsigned long long mac64;
258 bd_t *bip = (bd_t *) __res;
259 struct ibm44x_clocks clocks;
261 /* Retrieve MAC addresses from flash */
262 addr = ioremap64(OCOTEA_MAC_BASE, OCOTEA_MAC_SIZE);
263 mac64 = simple_strtoull(addr, 0, 16);
264 memcpy(bip->bi_enetaddr[0], (char *)&mac64+2, 6);
265 mac64 = simple_strtoull(addr+OCOTEA_MAC1_OFFSET, 0, 16);
266 memcpy(bip->bi_enetaddr[1], (char *)&mac64+2, 6);
269 /* Set EMAC PHY map to not probe address 0x00 */
270 emac_phy_map[0] = 0x00000001;
271 emac_phy_map[1] = 0x00000001;
273 #if !defined(CONFIG_BDI_SWITCH)
275 * The Abatron BDI JTAG debugger does not tolerate others
276 * mucking with the debug registers.
278 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
281 * Determine various clocks.
282 * To be completely correct we should get SysClk
283 * from FPGA, because it can be changed by on-board switches
286 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
287 bip->bi_opb_busfreq = clocks.opb;
289 /* Use IIC in standard (100 kHz) mode */
290 bip->bi_iic_fast[0] = bip->bi_iic_fast[1] = 0;
292 /* Setup TODC access */
293 TODC_INIT(TODC_TYPE_DS1743,
296 ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
299 /* init to some ~sane value until calibrate_delay() runs */
300 loops_per_jiffy = 50000000/HZ;
302 /* Setup PCI host bridge */
305 #ifdef CONFIG_BLK_DEV_INITRD
307 ROOT_DEV = to_kdev_t(0x0100); /* /dev/ram */
310 #ifdef CONFIG_ROOT_NFS
311 ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs */
313 ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 */
317 conswitchp = &dummy_con;
320 ocotea_early_serial_map(&clocks);
322 /* Identify the system */
323 printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
327 ocotea_restart(char *cmd)
334 ocotea_power_off(void)
348 * Read the 440GX memory controller to get size of system memory.
350 static unsigned long __init
351 ocotea_find_end_of_memory(void)
361 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
364 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
367 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
370 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
374 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
376 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
378 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
380 case SDRAM_CONFIG_SIZE_8M:
381 mem_size += PPC44x_MEM_SIZE_8M;
383 case SDRAM_CONFIG_SIZE_16M:
384 mem_size += PPC44x_MEM_SIZE_16M;
386 case SDRAM_CONFIG_SIZE_32M:
387 mem_size += PPC44x_MEM_SIZE_32M;
389 case SDRAM_CONFIG_SIZE_64M:
390 mem_size += PPC44x_MEM_SIZE_64M;
392 case SDRAM_CONFIG_SIZE_128M:
393 mem_size += PPC44x_MEM_SIZE_128M;
395 case SDRAM_CONFIG_SIZE_256M:
396 mem_size += PPC44x_MEM_SIZE_256M;
398 case SDRAM_CONFIG_SIZE_512M:
399 mem_size += PPC44x_MEM_SIZE_512M;
407 ocotea_init_irq(void)
411 /* Enable PPC440GP interrupt compatibility mode */
412 SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) | DCRN_SDR_MFR_PCM);
416 for (i = 0; i < NR_IRQS; i++)
417 irq_desc[i].handler = ppc4xx_pic;
420 void __init platform_init(unsigned long r3, unsigned long r4,
421 unsigned long r5, unsigned long r6, unsigned long r7)
423 parse_bootinfo(find_bootinfo());
425 /* Disable L2-Cache due to hardware issues */
426 ibm440gx_l2c_disable();
428 ppc_md.setup_arch = ocotea_setup_arch;
429 ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
430 ppc_md.init_IRQ = ocotea_init_irq;
431 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
433 ppc_md.find_end_of_memory = ocotea_find_end_of_memory;
435 ppc_md.restart = ocotea_restart;
436 ppc_md.power_off = ocotea_power_off;
437 ppc_md.halt = ocotea_halt;
439 ppc_md.calibrate_decr = ocotea_calibrate_decr;
440 ppc_md.time_init = todc_time_init;
441 ppc_md.set_rtc_time = todc_set_rtc_time;
442 ppc_md.get_rtc_time = todc_get_rtc_time;
444 ppc_md.nvram_read_val = todc_direct_read_val;
445 ppc_md.nvram_write_val = todc_direct_write_val;
446 #if defined(CONFIG_VT)
447 ppc_md.kbd_setkeycode = pckbd_setkeycode;
448 ppc_md.kbd_getkeycode = pckbd_getkeycode;
449 ppc_md.kbd_translate = pckbd_translate;
450 ppc_md.kbd_unexpected_up = pckbd_unexpected_up;
451 ppc_md.kbd_leds = pckbd_leds;
452 ppc_md.kbd_init_hw = 0;
455 #ifdef CONFIG_SERIAL_TEXT_DEBUG
456 ppc_md.progress = gen550_progress;
457 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
459 ppc_md.early_serial_map = ocotea_early_serial_map;