arch/ppc/platforms/pmac_smp.c

   1 /*
   2  * SMP support for power macintosh.
   3  *
   4  * We support both the old "powersurge" SMP architecture
   5  * and the current Core99 (G4 PowerMac) machines.
   6  *
   7  * Note that we don't support the very first rev. of
   8  * Apple/DayStar 2 CPUs board, the one with the funky
   9  * watchdog. Hopefully, none of these should be there except
  10  * maybe internally to Apple. I should probably still add some
  11  * code to detect this card though and disable SMP. --BenH.
  12  *
  13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
  14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
  15  *
  16  * Support for DayStar quad CPU cards
  17  * Copyright (C) XLR8, Inc. 1994-2000
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  */
  24 #include <linux/config.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/smp.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/kernel_stat.h>
  31 #include <linux/delay.h>
  32 #define __KERNEL_SYSCALLS__
  33 #include <linux/unistd.h>
  34 #include <linux/init.h>
  35 #include <linux/spinlock.h>
  36 #include <linux/stringify.h>
  37
  38 #include <asm/ptrace.h>
  39 #include <asm/atomic.h>
  40 #include <asm/irq.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/hardirq.h>
  44 #include <asm/softirq.h>
  45 #include <asm/sections.h>
  46 #include <asm/io.h>
  47 #include <asm/prom.h>
  48 #include <asm/smp.h>
  49 #include <asm/residual.h>
  50 #include <asm/machdep.h>
  51 #include <asm/pmac_feature.h>
  52 #include <asm/time.h>
  53 #include <asm/open_pic.h>
  54 #include <asm/processor.h>
  55
  56 /*
  57  * Powersurge (old powermac SMP) support.
  58  */
  59
  60 extern void __secondary_start_psurge(void);
  61 extern void __secondary_start_psurge2(void);    /* Temporary horrible hack */
  62 extern void __secondary_start_psurge3(void);    /* Temporary horrible hack */
  63
  64 /* Addresses for powersurge registers */
  65 #define HAMMERHEAD_BASE         0xf8000000
  66 #define HHEAD_CONFIG            0x90
  67 #define HHEAD_SEC_INTR          0xc0
  68
  69 /* register for interrupting the primary processor on the powersurge */
  70 /* N.B. this is actually the ethernet ROM! */
  71 #define PSURGE_PRI_INTR         0xf3019000
  72
  73 /* register for storing the start address for the secondary processor */
  74 /* N.B. this is the PCI config space address register for the 1st bridge */
  75 #define PSURGE_START            0xf2800000
  76
  77 /* Daystar/XLR8 4-CPU card */
  78 #define PSURGE_QUAD_REG_ADDR    0xf8800000
  79
  80 #define PSURGE_QUAD_IRQ_SET     0
  81 #define PSURGE_QUAD_IRQ_CLR     1
  82 #define PSURGE_QUAD_IRQ_PRIMARY 2
  83 #define PSURGE_QUAD_CKSTOP_CTL  3
  84 #define PSURGE_QUAD_PRIMARY_ARB 4
  85 #define PSURGE_QUAD_BOARD_ID    6
  86 #define PSURGE_QUAD_WHICH_CPU   7
  87 #define PSURGE_QUAD_CKSTOP_RDBK 8
  88 #define PSURGE_QUAD_RESET_CTL   11
  89
  90 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
  91 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
  92 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
  93 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
  94
  95 /* virtual addresses for the above */
  96 static volatile u8 *hhead_base;
  97 static volatile u8 *quad_base;
  98 static volatile u32 *psurge_pri_intr;
  99 static volatile u8 *psurge_sec_intr;
 100 static volatile u32 *psurge_start;
 101
 102 /* values for psurge_type */
 103 #define PSURGE_NONE             -1
 104 #define PSURGE_DUAL             0
 105 #define PSURGE_QUAD_OKEE        1
 106 #define PSURGE_QUAD_COTTON      2
 107 #define PSURGE_QUAD_ICEGRASS    3
 108
 109 /* what sort of powersurge board we have */
 110 static int psurge_type = PSURGE_NONE;
 111
 112 volatile static long int core99_l2_cache;
 113 volatile static long int core99_l3_cache;
 114
 115 static void __init
 116 core99_init_caches(void)
 117 {
 118         int cpu = smp_processor_id();
 119
 120         if (!(cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR))
 121                 return;
 122
 123         if (cpu == 0){
 124                 core99_l2_cache = _get_L2CR();
 125                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
 126         } else {
 127                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
 128                 _set_L2CR(0);
 129                 _set_L2CR(core99_l2_cache);
 130                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
 131         }
 132
 133         if (!(cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR))
 134                 return;
 135
 136         if (cpu == 0){
 137                 core99_l3_cache = _get_L3CR();
 138                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
 139         } else {
 140                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
 141                 _set_L3CR(0);
 142                 _set_L3CR(core99_l3_cache);
 143                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
 144         }
 145 }
 146
 147 /*
 148  * Set and clear IPIs for powersurge.
 149  */
 150 static inline void psurge_set_ipi(int cpu)
 151 {
 152         if (psurge_type == PSURGE_NONE)
 153                 return;
 154         if (cpu == 0)
 155                 in_be32(psurge_pri_intr);
 156         else if (psurge_type == PSURGE_DUAL)
 157                 out_8(psurge_sec_intr, 0);
 158         else
 159                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
 160 }
 161
 162 static inline void psurge_clr_ipi(int cpu)
 163 {
 164         if (cpu > 0) {
 165                 switch(psurge_type) {
 166                 case PSURGE_DUAL:
 167                         out_8(psurge_sec_intr, ~0);
 168                 case PSURGE_NONE:
 169                         break;
 170                 default:
 171                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
 172                 }
 173         }
 174 }
 175
 176 /*
 177  * On powersurge (old SMP powermac architecture) we don't have
 178  * separate IPIs for separate messages like openpic does.  Instead
 179  * we have a bitmap for each processor, where a 1 bit means that
 180  * the corresponding message is pending for that processor.
 181  * Ideally each cpu's entry would be in a different cache line.
 182  *  -- paulus.
 183  */
 184 static unsigned long psurge_smp_message[NR_CPUS];
 185
 186 void __pmac
 187 psurge_smp_message_recv(struct pt_regs *regs)
 188 {
 189         int cpu = smp_processor_id();
 190         int msg;
 191
 192         /* clear interrupt */
 193         psurge_clr_ipi(cpu);
 194
 195         if (smp_num_cpus < 2)
 196                 return;
 197
 198         /* make sure there is a message there */
 199         for (msg = 0; msg < 4; msg++)
 200                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
 201                         smp_message_recv(msg, regs);
 202 }
 203
 204 void __pmac
 205 psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
 206 {
 207         psurge_smp_message_recv(regs);
 208 }
 209
 210 static void __pmac
 211 smp_psurge_message_pass(int target, int msg, unsigned long data, int wait)
 212 {
 213         int i;
 214
 215         if (smp_num_cpus < 2)
 216                 return;
 217
 218         for (i = 0; i < smp_num_cpus; i++) {
 219                 if (target == MSG_ALL
 220                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
 221                     || target == i) {
 222                         set_bit(msg, &psurge_smp_message[i]);
 223                         psurge_set_ipi(i);
 224                 }
 225         }
 226 }
 227
 228 /*
 229  * Determine a quad card presence. We read the board ID register, we
 230  * force the data bus to change to something else, and we read it again.
 231  * It it's stable, then the register probably exist (ugh !)
 232  */
 233 static int __init psurge_quad_probe(void)
 234 {
 235         int type;
 236         unsigned int i;
 237
 238         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
 239         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
 240             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 241                 return PSURGE_DUAL;
 242
 243         /* looks OK, try a slightly more rigorous test */
 244         /* bogus is not necessarily cacheline-aligned,
 245            though I don't suppose that really matters.  -- paulus */
 246         for (i = 0; i < 100; i++) {
 247                 volatile u32 bogus[8];
 248                 bogus[(0+i)%8] = 0x00000000;
 249                 bogus[(1+i)%8] = 0x55555555;
 250                 bogus[(2+i)%8] = 0xFFFFFFFF;
 251                 bogus[(3+i)%8] = 0xAAAAAAAA;
 252                 bogus[(4+i)%8] = 0x33333333;
 253                 bogus[(5+i)%8] = 0xCCCCCCCC;
 254                 bogus[(6+i)%8] = 0xCCCCCCCC;
 255                 bogus[(7+i)%8] = 0x33333333;
 256                 wmb();
 257                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
 258                 mb();
 259                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 260                         return PSURGE_DUAL;
 261         }
 262         return type;
 263 }
 264
 265 static void __init psurge_quad_init(void)
 266 {
 267         int procbits;
 268
 269         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
 270         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
 271         if (psurge_type == PSURGE_QUAD_ICEGRASS)
 272                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 273         else
 274                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
 275         mdelay(33);
 276         out_8(psurge_sec_intr, ~0);
 277         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
 278         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 279         if (psurge_type != PSURGE_QUAD_ICEGRASS)
 280                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
 281         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
 282         mdelay(33);
 283         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
 284         mdelay(33);
 285         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
 286         mdelay(33);
 287 }
 288
 289 static int __init smp_psurge_probe(void)
 290 {
 291         int i, ncpus;
 292
 293         /* We don't do SMP on the PPC601 -- paulus */
 294         if (PVR_VER(mfspr(PVR)) == 1)
 295                 return 1;
 296
 297         /*
 298          * The powersurge cpu board can be used in the generation
 299          * of powermacs that have a socket for an upgradeable cpu card,
 300          * including the 7500, 8500, 9500, 9600.
 301          * The device tree doesn't tell you if you have 2 cpus because
 302          * OF doesn't know anything about the 2nd processor.
 303          * Instead we look for magic bits in magic registers,
 304          * in the hammerhead memory controller in the case of the
 305          * dual-cpu powersurge board.  -- paulus.
 306          */
 307         if (find_devices("hammerhead") == NULL)
 308                 return 1;
 309
 310         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
 311         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
 312         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
 313
 314         psurge_type = psurge_quad_probe();
 315         if (psurge_type != PSURGE_DUAL) {
 316                 psurge_quad_init();
 317                 /* All released cards using this HW design have 4 CPUs */
 318                 ncpus = 4;
 319         } else {
 320                 iounmap((void *) quad_base);
 321                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
 322                         /* not a dual-cpu card */
 323                         iounmap((void *) hhead_base);
 324                         psurge_type = PSURGE_NONE;
 325                         return 1;
 326                 }
 327                 ncpus = 2;
 328         }
 329
 330         psurge_start = ioremap(PSURGE_START, 4);
 331         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
 332
 333         /* this is not actually strictly necessary -- paulus. */
 334         for (i = 1; i < ncpus; ++i)
 335                 smp_hw_index[i] = i;
 336
 337         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
 338
 339         return ncpus;
 340 }
 341
 342 static void __init smp_psurge_kick_cpu(int nr)
 343 {
 344         void (*start)(void) = __secondary_start_psurge;
 345         unsigned long a;
 346
 347         /* may need to flush here if secondary bats aren't setup */
 348         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
 349                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
 350         asm volatile("sync");
 351
 352         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
 353
 354         /* setup entry point of secondary processor */
 355         switch (nr) {
 356         case 2:
 357                 start = __secondary_start_psurge2;
 358                 break;
 359         case 3:
 360                 start = __secondary_start_psurge3;
 361                 break;
 362         }
 363
 364         out_be32(psurge_start, __pa(start));
 365         mb();
 366
 367         psurge_set_ipi(nr);
 368         udelay(10);
 369         psurge_clr_ipi(nr);
 370
 371         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
 372 }
 373
 374 /*
 375  * With the dual-cpu powersurge board, the decrementers and timebases
 376  * of both cpus are frozen after the secondary cpu is started up,
 377  * until we give the secondary cpu another interrupt.  This routine
 378  * uses this to get the timebases synchronized.
 379  *  -- paulus.
 380  */
 381 static void __init psurge_dual_sync_tb(int cpu_nr)
 382 {
 383         static volatile int sec_tb_reset = 0;
 384         int t;
 385
 386         set_dec(tb_ticks_per_jiffy);
 387         set_tb(0, 0);
 388         last_jiffy_stamp(cpu_nr) = 0;
 389
 390         if (cpu_nr > 0) {
 391                 mb();
 392                 sec_tb_reset = 1;
 393                 return;
 394         }
 395
 396         /* wait for the secondary to have reset its TB before proceeding */
 397         for (t = 10000000; t > 0 && !sec_tb_reset; --t)
 398                 ;
 399
 400         /* now interrupt the secondary, starting both TBs */
 401         psurge_set_ipi(1);
 402
 403         smp_tb_synchronized = 1;
 404 }
 405
 406 static void __init
 407 smp_psurge_setup_cpu(int cpu_nr)
 408 {
 409
 410         if (cpu_nr == 0) {
 411                 /* If we failed to start the second CPU, we should still
 412                  * send it an IPI to start the timebase & DEC or we might
 413                  * have them stuck.
 414                  */
 415                 if (smp_num_cpus < 2)
 416                         goto sync_tb;
 417                 /* reset the entry point so if we get another intr we won't
 418                  * try to startup again */
 419                 out_be32(psurge_start, 0x100);
 420                 if (request_irq(30, psurge_primary_intr, SA_INTERRUPT, "primary IPI", 0))
 421                         printk(KERN_ERR "Couldn't get primary IPI interrupt");
 422         }
 423 sync_tb:
 424         if (psurge_type == PSURGE_DUAL)
 425                 psurge_dual_sync_tb(cpu_nr);
 426 }
 427
 428 static int __init
 429 smp_core99_probe(void)
 430 {
 431         struct device_node *cpus;
 432         int i, ncpus = 1;
 433         extern int powersave_nap;
 434
 435         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
 436         cpus = find_type_devices("cpu");
 437         if (cpus)
 438                 while ((cpus = cpus->next) != NULL)
 439                         ++ncpus;
 440         printk("smp_core99_probe: found %d cpus\n", ncpus);
 441         if (ncpus > 1) {
 442                 openpic_request_IPIs();
 443                 for (i = 1; i < ncpus; ++i)
 444                         smp_hw_index[i] = i;
 445 #ifdef CONFIG_6xx       /* XXX */
 446                 powersave_nap = 0;
 447 #endif
 448                 /* Read cache setting of CPU 0 */
 449                 core99_init_caches();
 450         }
 451
 452         return ncpus;
 453 }
 454
 455 static void __init
 456 smp_core99_kick_cpu(int nr)
 457 {
 458         unsigned long save_vector, new_vector;
 459         unsigned long flags;
 460
 461         volatile unsigned long *vector
 462                  = ((volatile unsigned long *)(KERNELBASE+0x100));
 463         if (nr < 1 || nr > 3)
 464                 return;
 465         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
 466
 467         local_irq_save(flags);
 468         local_irq_disable();
 469
 470         /* Save reset vector */
 471         save_vector = *vector;
 472
 473         /* Setup fake reset vector that does
 474          *   b __secondary_start_psurge - KERNELBASE
 475          */
 476         switch(nr) {
 477                 case 1:
 478                         new_vector = (unsigned long)__secondary_start_psurge;
 479                         break;
 480                 case 2:
 481                         new_vector = (unsigned long)__secondary_start_psurge2;
 482                         break;
 483                 case 3:
 484                         new_vector = (unsigned long)__secondary_start_psurge3;
 485                         break;
 486         }
 487         *vector = 0x48000002 + new_vector - KERNELBASE;
 488
 489         /* flush data cache and inval instruction cache */
 490         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 491
 492         /* Put some life in our friend */
 493         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
 494
 495         /* FIXME: We wait a bit for the CPU to take the exception, I should
 496          * instead wait for the entry code to set something for me. Well,
 497          * ideally, all that crap will be done in prom.c and the CPU left
 498          * in a RAM-based wait loop like CHRP.
 499          */
 500         mdelay(1);
 501
 502         /* Restore our exception vector */
 503         *vector = save_vector;
 504         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 505
 506         local_irq_restore(flags);
 507         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
 508 }
 509
 510 static void __init
 511 smp_core99_setup_cpu(int cpu_nr)
 512 {
 513
 514         /* Setup some critical registers
 515          * and apply cache setting from CPU 0
 516          */
 517         if (cpu_nr != 0)
 518                 core99_init_caches();
 519
 520         /* Setup openpic */
 521         do_openpic_setup_cpu();
 522
 523         /* Setup L2/L3 */
 524         if (cpu_nr == 0)
 525                 if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
 526 }
 527
 528 /* PowerSurge-style Macs */
 529 struct smp_ops_t psurge_smp_ops __pmacdata = {
 530         .message_pass   = smp_psurge_message_pass,
 531         .probe          = smp_psurge_probe,
 532         .kick_cpu       = smp_psurge_kick_cpu,
 533         .setup_cpu      = smp_psurge_setup_cpu,
 534 };
 535
 536 /* Core99 Macs (dual G4s) */
 537 struct smp_ops_t core99_smp_ops __pmacdata = {
 538         .message_pass   = smp_openpic_message_pass,
 539         .probe          = smp_core99_probe,
 540         .kick_cpu       = smp_core99_kick_cpu,
 541         .setup_cpu      = smp_core99_setup_cpu,
 542 };