2 * Speech Design SPD8xxTS board specific definitions
4 * Copyright (c) 2000,2001 Wolfgang Denk (wd@denx.de)
8 #ifndef __ASM_SPD8XX_H__
9 #define __ASM_SPD8XX_H__
11 #include <linux/config.h>
13 #include <asm/ppcboot.h>
15 #define SPD_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */
16 #define SPD_IMAP_SIZE (64 * 1024) /* size of mapped area */
18 #define IMAP_ADDR SPD_IMMR_BASE /* physical base address of IMMR area */
19 #define IMAP_SIZE SPD_IMAP_SIZE /* mapped size of IMMR area */
21 #define PCMCIA_MEM_ADDR ((uint)0xFE100000)
22 #define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
24 #define IDE0_INTERRUPT 10 /* = IRQ5 */
25 #define IDE1_INTERRUPT 12 /* = IRQ6 */
26 #define CPM_INTERRUPT 13 /* = SIU_LEVEL6 (was: SIU_LEVEL2) */
28 /* override the default number of IDE hardware interfaces */
32 * Definitions for IDE0 Interface
34 #define IDE0_BASE_OFFSET 0x0000 /* Offset in PCMCIA memory */
35 #define IDE0_DATA_REG_OFFSET 0x0000
36 #define IDE0_ERROR_REG_OFFSET 0x0081
37 #define IDE0_NSECTOR_REG_OFFSET 0x0082
38 #define IDE0_SECTOR_REG_OFFSET 0x0083
39 #define IDE0_LCYL_REG_OFFSET 0x0084
40 #define IDE0_HCYL_REG_OFFSET 0x0085
41 #define IDE0_SELECT_REG_OFFSET 0x0086
42 #define IDE0_STATUS_REG_OFFSET 0x0087
43 #define IDE0_CONTROL_REG_OFFSET 0x0106
44 #define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
47 * Definitions for IDE1 Interface
49 #define IDE1_BASE_OFFSET 0x0C00 /* Offset in PCMCIA memory */
50 #define IDE1_DATA_REG_OFFSET 0x0000
51 #define IDE1_ERROR_REG_OFFSET 0x0081
52 #define IDE1_NSECTOR_REG_OFFSET 0x0082
53 #define IDE1_SECTOR_REG_OFFSET 0x0083
54 #define IDE1_LCYL_REG_OFFSET 0x0084
55 #define IDE1_HCYL_REG_OFFSET 0x0085
56 #define IDE1_SELECT_REG_OFFSET 0x0086
57 #define IDE1_STATUS_REG_OFFSET 0x0087
58 #define IDE1_CONTROL_REG_OFFSET 0x0106
59 #define IDE1_IRQ_REG_OFFSET 0x000A /* not used */
61 /* We don't use the 8259.
63 #define NR_8259_INTS 0
65 #endif /* __ASM_SPD8XX_H__ */
66 #endif /* __KERNEL__ */