2 * arch/sparc/kernel/sun4m_irq.c:
4 * djhr: Hacked out of irq.c into a CPU dependent version.
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
12 #include <linux/config.h>
13 #include <linux/ptrace.h>
14 #include <linux/errno.h>
15 #include <linux/linkage.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/signal.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
25 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/system.h>
29 #include <asm/vaddrs.h>
30 #include <asm/timer.h>
31 #include <asm/openprom.h>
32 #include <asm/oplib.h>
33 #include <asm/traps.h>
34 #include <asm/pgalloc.h>
35 #include <asm/pgtable.h>
41 static unsigned long dummy;
43 struct sun4m_intregs *sun4m_interrupts;
44 unsigned long *irq_rcvreg = &dummy;
46 /* These tables only apply for interrupts greater than 15..
48 * any intr value below 0x10 is considered to be a soft-int
49 * this may be useful or it may not.. but that's how I've done it.
50 * and it won't clash with what OBP is telling us about devices.
52 * take an encoded intr value and lookup if it's valid
53 * then get the mask bits that match from irq_mask
55 * P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
57 static unsigned char irq_xlate[32] = {
58 /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f */
59 0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 5, 6, 14, 0, 7,
60 0, 0, 8, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 0
63 static unsigned long irq_mask[] = {
64 0, /* illegal index */
65 SUN4M_INT_SCSI, /* 1 irq 4 */
66 SUN4M_INT_ETHERNET, /* 2 irq 6 */
67 SUN4M_INT_VIDEO, /* 3 irq 8 */
68 SUN4M_INT_REALTIME, /* 4 irq 10 */
69 SUN4M_INT_FLOPPY, /* 5 irq 11 */
70 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), /* 6 irq 12 */
71 SUN4M_INT_MODULE_ERR, /* 7 irq 15 */
72 SUN4M_INT_SBUS(0), /* 8 irq 2 */
73 SUN4M_INT_SBUS(1), /* 9 irq 3 */
74 SUN4M_INT_SBUS(2), /* 10 irq 5 */
75 SUN4M_INT_SBUS(3), /* 11 irq 7 */
76 SUN4M_INT_SBUS(4), /* 12 irq 9 */
77 SUN4M_INT_SBUS(5), /* 13 irq 11 */
78 SUN4M_INT_SBUS(6) /* 14 irq 13 */
81 static int sun4m_pil_map[] = { 0, 2, 3, 5, 7, 9, 11, 13 };
83 unsigned int sun4m_sbint_to_irq(struct sbus_dev *sdev, unsigned int sbint)
85 if (sbint >= sizeof(sun4m_pil_map)) {
86 printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
89 return sun4m_pil_map[sbint] | 0x30;
92 inline unsigned long sun4m_get_irqmask(unsigned int irq)
97 /* OBIO/SBUS interrupts */
99 mask = irq_mask[irq_xlate[irq]];
101 printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
103 /* Soft Interrupts will come here.
104 * Currently there is no way to trigger them but I'm sure
105 * something could be cooked up.
108 mask = SUN4M_SOFT_INT(irq);
113 static void sun4m_disable_irq(unsigned int irq_nr)
115 unsigned long mask, flags;
116 int cpu = smp_processor_id();
118 mask = sun4m_get_irqmask(irq_nr);
121 sun4m_interrupts->set = mask;
123 sun4m_interrupts->cpu_intregs[cpu].set = mask;
124 restore_flags(flags);
127 static void sun4m_enable_irq(unsigned int irq_nr)
129 unsigned long mask, flags;
130 int cpu = smp_processor_id();
132 /* Dreadful floppy hack. When we use 0x2b instead of
133 * 0x0b the system blows (it starts to whistle!).
134 * So we continue to use 0x0b. Fixme ASAP. --P3
136 if (irq_nr != 0x0b) {
137 mask = sun4m_get_irqmask(irq_nr);
140 sun4m_interrupts->clear = mask;
142 sun4m_interrupts->cpu_intregs[cpu].clear = mask;
143 restore_flags(flags);
146 sun4m_interrupts->clear = SUN4M_INT_FLOPPY;
147 restore_flags(flags);
151 static unsigned long cpu_pil_to_imask[16] = {
154 /*2*/ SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
155 /*3*/ SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
156 /*4*/ SUN4M_INT_SCSI,
157 /*5*/ SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
158 /*6*/ SUN4M_INT_ETHERNET,
159 /*7*/ SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
160 /*8*/ SUN4M_INT_VIDEO,
161 /*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
162 /*10*/ SUN4M_INT_REALTIME,
163 /*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
164 /*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
165 /*13*/ SUN4M_INT_AUDIO,
166 /*14*/ SUN4M_INT_E14,
170 /* We assume the caller is local cli()'d when these are called, or else
171 * very bizarre behavior will result.
173 static void sun4m_disable_pil_irq(unsigned int pil)
175 sun4m_interrupts->set = cpu_pil_to_imask[pil];
178 static void sun4m_enable_pil_irq(unsigned int pil)
180 sun4m_interrupts->clear = cpu_pil_to_imask[pil];
184 static void sun4m_send_ipi(int cpu, int level)
188 mask = sun4m_get_irqmask(level);
189 sun4m_interrupts->cpu_intregs[cpu].set = mask;
192 static void sun4m_clear_ipi(int cpu, int level)
196 mask = sun4m_get_irqmask(level);
197 sun4m_interrupts->cpu_intregs[cpu].clear = mask;
200 static void sun4m_set_udt(int cpu)
202 sun4m_interrupts->undirected_target = cpu;
206 #define OBIO_INTR 0x20
207 #define TIMER_IRQ (OBIO_INTR | 10)
208 #define PROFILE_IRQ (OBIO_INTR | 14)
210 struct sun4m_timer_regs *sun4m_timers;
211 unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
213 static void sun4m_clear_clock_irq(void)
215 volatile unsigned int clear_intr;
216 clear_intr = sun4m_timers->l10_timer_limit;
219 static void sun4m_clear_profile_irq(int cpu)
221 volatile unsigned int clear;
223 clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit;
226 static void sun4m_load_profile_irq(int cpu, unsigned int limit)
228 sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
231 char *sun4m_irq_itoa(unsigned int irq)
233 static char buff[16];
234 sprintf(buff, "%d", irq);
238 static void __init sun4m_init_timers(void (*counter_fn)(int, void *, struct pt_regs *))
240 int reg_count, irq, cpu;
241 struct linux_prom_registers cnt_regs[PROMREG_MAX];
242 int obio_node, cnt_node;
247 prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 ||
248 (obio_node = prom_getchild (obio_node)) == 0 ||
249 (cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
250 prom_printf("Cannot find /obio/counter node\n");
253 reg_count = prom_getproperty(cnt_node, "reg",
254 (void *) cnt_regs, sizeof(cnt_regs));
255 reg_count = (reg_count/sizeof(struct linux_prom_registers));
257 /* Apply the obio ranges to the timer registers. */
258 prom_apply_obio_ranges(cnt_regs, reg_count);
260 cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
261 cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
262 cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
263 for(obio_node = 1; obio_node < 4; obio_node++) {
264 cnt_regs[obio_node].phys_addr =
265 cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
266 cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
267 cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
270 memset((char*)&r, 0, sizeof(struct resource));
271 /* Map the per-cpu Counter registers. */
272 r.flags = cnt_regs[0].which_io;
273 r.start = cnt_regs[0].phys_addr;
274 sun4m_timers = (struct sun4m_timer_regs *) sbus_ioremap(&r, 0,
275 PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
276 /* Map the system Counter register. */
277 /* XXX Here we expect consequent calls to yeld adjusent maps. */
278 r.flags = cnt_regs[4].which_io;
279 r.start = cnt_regs[4].phys_addr;
280 sbus_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");
282 sun4m_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
283 master_l10_counter = &sun4m_timers->l10_cur_count;
284 master_l10_limit = &sun4m_timers->l10_timer_limit;
286 irq = request_irq(TIMER_IRQ,
288 (SA_INTERRUPT | SA_STATIC_ALLOC),
291 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
295 if(linux_num_cpus > 1) {
296 for(cpu = 0; cpu < 4; cpu++)
297 sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0;
298 sun4m_interrupts->set = SUN4M_INT_E14;
300 sun4m_timers->cpu_timers[0].l14_timer_limit = 0;
305 extern unsigned long lvl14_save[4];
306 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
308 /* For SMP we use the level 14 ticker, however the bootup code
309 * has copied the firmwares level 14 vector into boot cpu's
310 * trap table, we must fix this now or we get squashed.
312 __save_and_cli(flags);
313 trap_table->inst_one = lvl14_save[0];
314 trap_table->inst_two = lvl14_save[1];
315 trap_table->inst_three = lvl14_save[2];
316 trap_table->inst_four = lvl14_save[3];
317 local_flush_cache_all();
318 __restore_flags(flags);
323 void __init sun4m_init_IRQ(void)
326 struct linux_prom_registers int_regs[PROMREG_MAX];
331 if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 ||
332 (ie_node = prom_getchild (ie_node)) == 0 ||
333 (ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
334 prom_printf("Cannot find /obio/interrupt node\n");
337 num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs,
339 num_regs = (num_regs/sizeof(struct linux_prom_registers));
341 /* Apply the obio ranges to these registers. */
342 prom_apply_obio_ranges(int_regs, num_regs);
344 int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
345 int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
346 int_regs[4].which_io = int_regs[num_regs-1].which_io;
347 for(ie_node = 1; ie_node < 4; ie_node++) {
348 int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
349 int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
350 int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
353 memset((char *)&r, 0, sizeof(struct resource));
354 /* Map the interrupt registers for all possible cpus. */
355 r.flags = int_regs[0].which_io;
356 r.start = int_regs[0].phys_addr;
357 sun4m_interrupts = (struct sun4m_intregs *) sbus_ioremap(&r, 0,
358 PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu");
360 /* Map the system interrupt control registers. */
361 r.flags = int_regs[4].which_io;
362 r.start = int_regs[4].phys_addr;
363 sbus_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");
365 sun4m_interrupts->set = ~SUN4M_INT_MASKALL;
366 for (i=0; i<linux_num_cpus; i++)
367 sun4m_interrupts->cpu_intregs[i].clear = ~0x17fff;
369 if (linux_num_cpus > 1) {
370 /* system wide interrupts go to cpu 0, this should always
371 * be safe because it is guaranteed to be fitted or OBP doesn't
374 * Not sure, but writing here on SLAVIO systems may puke
375 * so I don't do it unless there is more than 1 cpu.
377 irq_rcvreg = (unsigned long *)
378 &sun4m_interrupts->undirected_target;
379 sun4m_interrupts->undirected_target = 0;
381 BTFIXUPSET_CALL(sbint_to_irq, sun4m_sbint_to_irq, BTFIXUPCALL_NORM);
382 BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
383 BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
384 BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
385 BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
386 BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
387 BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
388 BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
389 BTFIXUPSET_CALL(__irq_itoa, sun4m_irq_itoa, BTFIXUPCALL_NORM);
390 sparc_init_timers = sun4m_init_timers;
392 BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
393 BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
394 BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
396 /* Cannot enable interrupts until OBP ticker is disabled. */