arch/sparc/mm/srmmu.c

   1 /* $Id: srmmu.c,v 1.233 2001/11/13 00:49:27 davem Exp $
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995 Pete Zaitcev
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mm.h>
  14 #include <linux/slab.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/pagemap.h>
  17 #include <linux/init.h>
  18 #include <linux/blk.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/fs.h>
  22 #include <linux/seq_file.h>
  23
  24 #include <asm/page.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/io.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/sbus.h>
  36 #include <asm/asi.h>
  37 #include <asm/msi.h>
  38 #include <asm/a.out.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/io-unit.h>
  41
  42 /* Now the cpu specific definitions. */
  43 #include <asm/viking.h>
  44 #include <asm/mxcc.h>
  45 #include <asm/ross.h>
  46 #include <asm/tsunami.h>
  47 #include <asm/swift.h>
  48 #include <asm/turbosparc.h>
  49
  50 #include <asm/btfixup.h>
  51
  52 enum mbus_module srmmu_modtype;
  53 unsigned int hwbug_bitmask;
  54 int vac_cache_size;
  55 int vac_line_size;
  56
  57 extern struct resource sparc_iomap;
  58
  59 extern unsigned long last_valid_pfn;
  60
  61 extern unsigned long page_kernel;
  62
  63 pgd_t *srmmu_swapper_pg_dir;
  64
  65 #ifdef CONFIG_SMP
  66 #define FLUSH_BEGIN(mm)
  67 #define FLUSH_END
  68 #else
  69 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  70 #define FLUSH_END       }
  71 #endif
  72
  73 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  74 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  75
  76 int flush_page_for_dma_global = 1;
  77
  78 #ifdef CONFIG_SMP
  79 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  80 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  81 #endif
  82
  83 char *srmmu_name;
  84
  85 ctxd_t *srmmu_ctx_table_phys;
  86 ctxd_t *srmmu_context_table;
  87
  88 int viking_mxcc_present;
  89 static spinlock_t srmmu_context_spinlock = SPIN_LOCK_UNLOCKED;
  90
  91 int is_hypersparc;
  92
  93 /*
  94  * In general all page table modifications should use the V8 atomic
  95  * swap instruction.  This insures the mmu and the cpu are in sync
  96  * with respect to ref/mod bits in the page tables.
  97  */
  98 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
  99 {
 100         __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
 101         return value;
 102 }
 103
 104 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
 105 {
 106         srmmu_swap((unsigned long *)ptep, pte_val(pteval));
 107 }
 108
 109 /* The very generic SRMMU page table operations. */
 110 static inline int srmmu_device_memory(unsigned long x)
 111 {
 112         return ((x & 0xF0000000) != 0);
 113 }
 114
 115 int srmmu_cache_pagetables;
 116
 117 /* these will be initialized in srmmu_nocache_calcsize() */
 118 int srmmu_nocache_npages;
 119 unsigned long srmmu_nocache_size;
 120 unsigned long srmmu_nocache_end;
 121 unsigned long pkmap_base;
 122 unsigned long pkmap_base_end;
 123 unsigned long srmmu_nocache_bitmap_size;
 124 extern unsigned long fix_kmap_begin;
 125 extern unsigned long fix_kmap_end;
 126
 127 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 128
 129 /* The context table is a nocache user with the biggest alignment needs. */
 130 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 131
 132 void *srmmu_nocache_pool;
 133 void *srmmu_nocache_bitmap;
 134 int srmmu_nocache_low;
 135 int srmmu_nocache_used;
 136 static spinlock_t srmmu_nocache_spinlock = SPIN_LOCK_UNLOCKED;
 137
 138 /* This makes sense. Honest it does - Anton */
 139 #define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
 140 #define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
 141 #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
 142
 143 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 144 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 145
 146 static inline unsigned long srmmu_pmd_page(pmd_t pmd)
 147 { return srmmu_device_memory(pmd_val(pmd))?~0:(unsigned long)__nocache_va((pmd_val(pmd) & SRMMU_PTD_PMASK) << 4); }
 148
 149 static inline struct page *srmmu_pte_page(pte_t pte)
 150 { return (mem_map + (unsigned long)(srmmu_device_memory(pte_val(pte))?~0:(((pte_val(pte) & SRMMU_PTE_PMASK) << 4) >> PAGE_SHIFT))); }
 151
 152 static inline int srmmu_pte_none(pte_t pte)
 153 { return !(pte_val(pte) & 0xFFFFFFF); }
 154
 155 static inline int srmmu_pte_present(pte_t pte)
 156 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 157
 158 static inline void srmmu_pte_clear(pte_t *ptep)
 159 { srmmu_set_pte(ptep, __pte(0)); }
 160
 161 static inline int srmmu_pmd_none(pmd_t pmd)
 162 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 163
 164 static inline int srmmu_pmd_bad(pmd_t pmd)
 165 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 166
 167 static inline int srmmu_pmd_present(pmd_t pmd)
 168 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 169
 170 static inline void srmmu_pmd_clear(pmd_t *pmdp)
 171 { srmmu_set_pte((pte_t *)pmdp, __pte(0)); }
 172
 173 static inline int srmmu_pgd_none(pgd_t pgd)
 174 { return !(pgd_val(pgd) & 0xFFFFFFF); }
 175
 176 static inline int srmmu_pgd_bad(pgd_t pgd)
 177 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 178
 179 static inline int srmmu_pgd_present(pgd_t pgd)
 180 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 181
 182 static inline void srmmu_pgd_clear(pgd_t * pgdp)
 183 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
 184
 185 static inline int srmmu_pte_write(pte_t pte)
 186 { return pte_val(pte) & SRMMU_WRITE; }
 187
 188 static inline int srmmu_pte_dirty(pte_t pte)
 189 { return pte_val(pte) & SRMMU_DIRTY; }
 190
 191 static inline int srmmu_pte_young(pte_t pte)
 192 { return pte_val(pte) & SRMMU_REF; }
 193
 194 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 195 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 196
 197 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 198 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 199
 200 static inline pte_t srmmu_pte_mkold(pte_t pte)
 201 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 202
 203 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 204 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 205
 206 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 207 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 208
 209 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 210 { return __pte(pte_val(pte) | SRMMU_REF);}
 211
 212 /*
 213  * Conversion functions: convert a page and protection to a page entry,
 214  * and a page entry and page directory to the page they refer to.
 215  */
 216 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 217 { return __pte((((page - mem_map) << PAGE_SHIFT) >> 4) | pgprot_val(pgprot)); }
 218
 219 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 220 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 221
 222 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 223 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 224
 225 /* XXX should we hyper_flush_whole_icache here - Anton */
 226 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 227 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 228
 229 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 230 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 231
 232 static inline void srmmu_pmd_set(pmd_t * pmdp, pte_t * ptep)
 233 { srmmu_set_pte((pte_t *)pmdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) ptep) >> 4))); }
 234
 235 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 236 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 237
 238 /* to find an entry in a top-level page table... */
 239 extern inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 240 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 241
 242 /* Find an entry in the second-level page table.. */
 243 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 244 { return (pmd_t *) srmmu_pgd_page(*dir) + ((address >> SRMMU_PMD_SHIFT) & (SRMMU_PTRS_PER_PMD - 1)); }
 245
 246 /* Find an entry in the third-level page table.. */
 247 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 248 { return (pte_t *) srmmu_pmd_page(*dir) + ((address >> PAGE_SHIFT) & (SRMMU_PTRS_PER_PTE - 1)); }
 249
 250 unsigned long __srmmu_get_nocache(int size, int align)
 251 {
 252         int offset = srmmu_nocache_low;
 253         int i;
 254         unsigned long va_tmp, phys_tmp;
 255         int lowest_failed = 0;
 256
 257         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 258
 259         spin_lock(&srmmu_nocache_spinlock);
 260
 261 repeat:
 262         offset = find_next_zero_bit(srmmu_nocache_bitmap, srmmu_nocache_bitmap_size, offset);
 263
 264         /* we align on physical address */
 265         if (align) {
 266                 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 267                 va_tmp = (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 268                 phys_tmp = (__nocache_pa(va_tmp) + align - 1) & ~(align - 1);
 269                 va_tmp = (unsigned long)__nocache_va(phys_tmp);
 270                 offset = (va_tmp - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 271         }
 272
 273         if ((srmmu_nocache_bitmap_size - offset) < size) {
 274                 printk("Run out of nocached RAM!\n");
 275                 spin_unlock(&srmmu_nocache_spinlock);
 276                 return 0;
 277         }
 278
 279         i = 0;
 280         while(i < size) {
 281                 if (test_bit(offset + i, srmmu_nocache_bitmap)) {
 282                         lowest_failed = 1;
 283                         offset = offset + i + 1;
 284                         goto repeat;
 285                 }
 286                 i++;
 287         }
 288
 289         i = 0;
 290         while(i < size) {
 291                 set_bit(offset + i, srmmu_nocache_bitmap);
 292                 i++;
 293                 srmmu_nocache_used++;
 294         }
 295
 296         if (!lowest_failed && ((align >> SRMMU_NOCACHE_BITMAP_SHIFT) <= 1) && (offset > srmmu_nocache_low))
 297                 srmmu_nocache_low = offset;
 298
 299         spin_unlock(&srmmu_nocache_spinlock);
 300
 301         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 302 }
 303
 304 unsigned inline long srmmu_get_nocache(int size, int align)
 305 {
 306         unsigned long tmp;
 307
 308         tmp = __srmmu_get_nocache(size, align);
 309
 310         if (tmp)
 311                 memset((void *)tmp, 0, size);
 312
 313         return tmp;
 314 }
 315
 316 void srmmu_free_nocache(unsigned long vaddr, int size)
 317 {
 318         int offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 319
 320         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 321
 322         spin_lock(&srmmu_nocache_spinlock);
 323
 324         while(size--) {
 325                 clear_bit(offset + size, srmmu_nocache_bitmap);
 326                 srmmu_nocache_used--;
 327         }
 328
 329         if (offset < srmmu_nocache_low)
 330                 srmmu_nocache_low = offset;
 331
 332         spin_unlock(&srmmu_nocache_spinlock);
 333 }
 334
 335 void srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end);
 336
 337 extern unsigned long probe_memory(void);        /* in fault.c */
 338
 339 /* Reserve nocache dynamically proportionally to the amount of
 340  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 341  */
 342 void srmmu_nocache_calcsize(void)
 343 {
 344         unsigned long sysmemavail = probe_memory() / 1024;
 345
 346         srmmu_nocache_npages =
 347                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 348         if (sysmemavail % (SRMMU_NOCACHE_ALCRATIO * 1024))
 349                 srmmu_nocache_npages += 256;
 350
 351         /* anything above 1280 blows up */
 352         if (srmmu_nocache_npages > 1280) srmmu_nocache_npages = 1280;
 353
 354         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 355         srmmu_nocache_bitmap_size = srmmu_nocache_npages * 16;
 356         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 357         fix_kmap_begin = srmmu_nocache_end;
 358         fix_kmap_end = fix_kmap_begin + (KM_TYPE_NR * NR_CPUS - 1) * PAGE_SIZE;
 359         pkmap_base = SRMMU_NOCACHE_VADDR + srmmu_nocache_size + 0x40000;
 360         pkmap_base_end = pkmap_base + LAST_PKMAP * PAGE_SIZE;
 361
 362         /* printk("system memory available = %luk\nnocache ram size = %luk\n",
 363                 sysmemavail, srmmu_nocache_size / 1024); */
 364 }
 365
 366 void srmmu_nocache_init(void)
 367 {
 368         pgd_t *pgd;
 369         pmd_t *pmd;
 370         pte_t *pte;
 371         unsigned long paddr, vaddr;
 372         unsigned long pteval;
 373
 374         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 375                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 376         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 377
 378         srmmu_nocache_bitmap = __alloc_bootmem(srmmu_nocache_bitmap_size, SMP_CACHE_BYTES, 0UL);
 379         memset(srmmu_nocache_bitmap, 0, srmmu_nocache_bitmap_size);
 380
 381         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 382         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 383         init_mm.pgd = srmmu_swapper_pg_dir;
 384
 385         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 386
 387         spin_lock_init(&srmmu_nocache_spinlock);
 388
 389         paddr = __pa((unsigned long)srmmu_nocache_pool);
 390         vaddr = SRMMU_NOCACHE_VADDR;
 391
 392         while (vaddr < srmmu_nocache_end) {
 393                 pgd = pgd_offset_k(vaddr);
 394                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 395                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 396
 397                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 398
 399                 if (srmmu_cache_pagetables)
 400                         pteval |= SRMMU_CACHE;
 401
 402                 srmmu_set_pte(__nocache_fix(pte), pteval);
 403
 404                 vaddr += PAGE_SIZE;
 405                 paddr += PAGE_SIZE;
 406         }
 407
 408         flush_cache_all();
 409         flush_tlb_all();
 410 }
 411
 412 static inline pgd_t *srmmu_get_pgd_fast(void)
 413 {
 414         pgd_t *pgd = NULL;
 415
 416         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 417         if (pgd) {
 418                 pgd_t *init = pgd_offset_k(0);
 419                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 420                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 421                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 422         }
 423
 424         return pgd;
 425 }
 426
 427 static void srmmu_free_pgd_fast(pgd_t *pgd)
 428 {
 429         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 430 }
 431
 432 static pte_t *srmmu_pte_alloc_one_fast(struct mm_struct *mm, unsigned long address)
 433 {
 434         return (pte_t *)srmmu_get_nocache(SRMMU_PTE_TABLE_SIZE, SRMMU_PTE_TABLE_SIZE);
 435 }
 436
 437 static pte_t *srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 438 {
 439         return NULL;
 440 }
 441
 442 static void srmmu_free_pte_fast(pte_t *pte)
 443 {
 444         srmmu_free_nocache((unsigned long)pte, SRMMU_PTE_TABLE_SIZE);
 445 }
 446
 447 static pmd_t *srmmu_pmd_alloc_one_fast(struct mm_struct *mm, unsigned long address)
 448 {
 449         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 450 }
 451
 452 static void srmmu_free_pmd_fast(pmd_t * pmd)
 453 {
 454         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 455 }
 456
 457 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 458 {
 459         struct ctx_list *ctxp;
 460
 461         ctxp = ctx_free.next;
 462         if(ctxp != &ctx_free) {
 463                 remove_from_ctx_list(ctxp);
 464                 add_to_used_ctxlist(ctxp);
 465                 mm->context = ctxp->ctx_number;
 466                 ctxp->ctx_mm = mm;
 467                 return;
 468         }
 469         ctxp = ctx_used.next;
 470         if(ctxp->ctx_mm == old_mm)
 471                 ctxp = ctxp->next;
 472         if(ctxp == &ctx_used)
 473                 panic("out of mmu contexts");
 474         flush_cache_mm(ctxp->ctx_mm);
 475         flush_tlb_mm(ctxp->ctx_mm);
 476         remove_from_ctx_list(ctxp);
 477         add_to_used_ctxlist(ctxp);
 478         ctxp->ctx_mm->context = NO_CONTEXT;
 479         ctxp->ctx_mm = mm;
 480         mm->context = ctxp->ctx_number;
 481 }
 482
 483 static inline void free_context(int context)
 484 {
 485         struct ctx_list *ctx_old;
 486
 487         ctx_old = ctx_list_pool + context;
 488         remove_from_ctx_list(ctx_old);
 489         add_to_free_ctxlist(ctx_old);
 490 }
 491
 492
 493 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 494     struct task_struct *tsk, int cpu)
 495 {
 496         if(mm->context == NO_CONTEXT) {
 497                 spin_lock(&srmmu_context_spinlock);
 498                 alloc_context(old_mm, mm);
 499                 spin_unlock(&srmmu_context_spinlock);
 500                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 501         }
 502
 503         if (is_hypersparc)
 504                 hyper_flush_whole_icache();
 505
 506         srmmu_set_context(mm->context);
 507 }
 508
 509 /* Low level IO area allocation on the SRMMU. */
 510 void srmmu_mapioaddr(unsigned long physaddr, unsigned long virt_addr, int bus_type, int rdonly)
 511 {
 512         pgd_t *pgdp;
 513         pmd_t *pmdp;
 514         pte_t *ptep;
 515         unsigned long tmp;
 516
 517         physaddr &= PAGE_MASK;
 518         pgdp = pgd_offset_k(virt_addr);
 519         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 520         ptep = srmmu_pte_offset(pmdp, virt_addr);
 521         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 522
 523         /*
 524          * I need to test whether this is consistent over all
 525          * sun4m's.  The bus_type represents the upper 4 bits of
 526          * 36-bit physical address on the I/O space lines...
 527          */
 528         tmp |= (bus_type << 28);
 529         if(rdonly)
 530                 tmp |= SRMMU_PRIV_RDONLY;
 531         else
 532                 tmp |= SRMMU_PRIV;
 533         __flush_page_to_ram(virt_addr);
 534         srmmu_set_pte(ptep, __pte(tmp));
 535         flush_tlb_all();
 536 }
 537
 538 void srmmu_unmapioaddr(unsigned long virt_addr)
 539 {
 540         pgd_t *pgdp;
 541         pmd_t *pmdp;
 542         pte_t *ptep;
 543
 544         pgdp = pgd_offset_k(virt_addr);
 545         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 546         ptep = srmmu_pte_offset(pmdp, virt_addr);
 547
 548         /* No need to flush uncacheable page. */
 549         srmmu_pte_clear(ptep);
 550         flush_tlb_all();
 551 }
 552
 553 /*
 554  * On the SRMMU we do not have the problems with limited tlb entries
 555  * for mapping kernel pages, so we just take things from the free page
 556  * pool.  As a side effect we are putting a little too much pressure
 557  * on the gfp() subsystem.  This setup also makes the logic of the
 558  * iommu mapping code a lot easier as we can transparently handle
 559  * mappings on the kernel stack without any special code as we did
 560  * need on the sun4c.
 561  */
 562 struct task_struct *srmmu_alloc_task_struct(void)
 563 {
 564         return (struct task_struct *) __get_free_pages(GFP_KERNEL, 1);
 565 }
 566
 567 static void srmmu_free_task_struct(struct task_struct *tsk)
 568 {
 569         free_pages((unsigned long)tsk, 1);
 570 }
 571
 572 static void srmmu_get_task_struct(struct task_struct *tsk)
 573 {
 574         atomic_inc(&virt_to_page(tsk)->count);
 575 }
 576
 577 /* tsunami.S */
 578 extern void tsunami_flush_cache_all(void);
 579 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 580 extern void tsunami_flush_cache_range(struct mm_struct *mm, unsigned long start, unsigned long end);
 581 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 582 extern void tsunami_flush_page_to_ram(unsigned long page);
 583 extern void tsunami_flush_page_for_dma(unsigned long page);
 584 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 585 extern void tsunami_flush_tlb_all(void);
 586 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 587 extern void tsunami_flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end);
 588 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 589 extern void tsunami_setup_blockops(void);
 590
 591 /*
 592  * Workaround, until we find what's going on with Swift. When low on memory,
 593  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 594  * out it is already in page tables/ fault again on the same instruction.
 595  * I really don't understand it, have checked it and contexts
 596  * are right, flush_tlb_all is done as well, and it faults again...
 597  * Strange. -jj
 598  *
 599  * The following code is a deadwood that may be necessary when
 600  * we start to make precise page flushes again. --zaitcev
 601  */
 602 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 603 {
 604 #if 0
 605         static unsigned long last;
 606         unsigned int val;
 607         /* unsigned int n; */
 608
 609         if (address == last) {
 610                 val = srmmu_hwprobe(address);
 611                 if (val != 0 && pte_val(pte) != val) {
 612                         printk("swift_update_mmu_cache: "
 613                             "addr %lx put %08x probed %08x from %p\n",
 614                             address, pte_val(pte), val,
 615                             __builtin_return_address(0));
 616                         srmmu_flush_whole_tlb();
 617                 }
 618         }
 619         last = address;
 620 #endif
 621 }
 622
 623 /* swift.S */
 624 extern void swift_flush_cache_all(void);
 625 extern void swift_flush_cache_mm(struct mm_struct *mm);
 626 extern void swift_flush_cache_range(struct mm_struct *mm,
 627                                     unsigned long start, unsigned long end);
 628 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 629 extern void swift_flush_page_to_ram(unsigned long page);
 630 extern void swift_flush_page_for_dma(unsigned long page);
 631 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 632 extern void swift_flush_tlb_all(void);
 633 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 634 extern void swift_flush_tlb_range(struct mm_struct *mm,
 635                                   unsigned long start, unsigned long end);
 636 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 637
 638 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 639 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 640 {
 641         int cctx, ctx1;
 642
 643         page &= PAGE_MASK;
 644         if ((ctx1 = vma->vm_mm->context) != -1) {
 645                 cctx = srmmu_get_context();
 646 /* Is context # ever different from current context? P3 */
 647                 if (cctx != ctx1) {
 648                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 649                         srmmu_set_context(ctx1);
 650                         swift_flush_page(page);
 651                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 652                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 653                         srmmu_set_context(cctx);
 654                 } else {
 655                          /* Rm. prot. bits from virt. c. */
 656                         /* swift_flush_cache_all(); */
 657                         /* swift_flush_cache_page(vma, page); */
 658                         swift_flush_page(page);
 659
 660                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 661                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 662                         /* same as above: srmmu_flush_tlb_page() */
 663                 }
 664         }
 665 }
 666 #endif
 667
 668 /*
 669  * The following are all MBUS based SRMMU modules, and therefore could
 670  * be found in a multiprocessor configuration.  On the whole, these
 671  * chips seems to be much more touchy about DVMA and page tables
 672  * with respect to cache coherency.
 673  */
 674
 675 /* Cypress flushes. */
 676 static void cypress_flush_cache_all(void)
 677 {
 678         volatile unsigned long cypress_sucks;
 679         unsigned long faddr, tagval;
 680
 681         flush_user_windows();
 682         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 683                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 684                                      "=r" (tagval) :
 685                                      "r" (faddr), "r" (0x40000),
 686                                      "i" (ASI_M_DATAC_TAG));
 687
 688                 /* If modified and valid, kick it. */
 689                 if((tagval & 0x60) == 0x60)
 690                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 691         }
 692 }
 693
 694 static void cypress_flush_cache_mm(struct mm_struct *mm)
 695 {
 696         register unsigned long a, b, c, d, e, f, g;
 697         unsigned long flags, faddr;
 698         int octx;
 699
 700         FLUSH_BEGIN(mm)
 701         flush_user_windows();
 702         __save_and_cli(flags);
 703         octx = srmmu_get_context();
 704         srmmu_set_context(mm->context);
 705         a = 0x20; b = 0x40; c = 0x60;
 706         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 707
 708         faddr = (0x10000 - 0x100);
 709         goto inside;
 710         do {
 711                 faddr -= 0x100;
 712         inside:
 713                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 714                                      "sta %%g0, [%0 + %2] %1\n\t"
 715                                      "sta %%g0, [%0 + %3] %1\n\t"
 716                                      "sta %%g0, [%0 + %4] %1\n\t"
 717                                      "sta %%g0, [%0 + %5] %1\n\t"
 718                                      "sta %%g0, [%0 + %6] %1\n\t"
 719                                      "sta %%g0, [%0 + %7] %1\n\t"
 720                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 721                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 722                                      "r" (a), "r" (b), "r" (c), "r" (d),
 723                                      "r" (e), "r" (f), "r" (g));
 724         } while(faddr);
 725         srmmu_set_context(octx);
 726         __restore_flags(flags);
 727         FLUSH_END
 728 }
 729
 730 static void cypress_flush_cache_range(struct mm_struct *mm, unsigned long start, unsigned long end)
 731 {
 732         register unsigned long a, b, c, d, e, f, g;
 733         unsigned long flags, faddr;
 734         int octx;
 735
 736         FLUSH_BEGIN(mm)
 737         flush_user_windows();
 738         __save_and_cli(flags);
 739         octx = srmmu_get_context();
 740         srmmu_set_context(mm->context);
 741         a = 0x20; b = 0x40; c = 0x60;
 742         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 743
 744         start &= SRMMU_PMD_MASK;
 745         while(start < end) {
 746                 faddr = (start + (0x10000 - 0x100));
 747                 goto inside;
 748                 do {
 749                         faddr -= 0x100;
 750                 inside:
 751                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 752                                              "sta %%g0, [%0 + %2] %1\n\t"
 753                                              "sta %%g0, [%0 + %3] %1\n\t"
 754                                              "sta %%g0, [%0 + %4] %1\n\t"
 755                                              "sta %%g0, [%0 + %5] %1\n\t"
 756                                              "sta %%g0, [%0 + %6] %1\n\t"
 757                                              "sta %%g0, [%0 + %7] %1\n\t"
 758                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 759                                              "r" (faddr),
 760                                              "i" (ASI_M_FLUSH_SEG),
 761                                              "r" (a), "r" (b), "r" (c), "r" (d),
 762                                              "r" (e), "r" (f), "r" (g));
 763                 } while (faddr != start);
 764                 start += SRMMU_PMD_SIZE;
 765         }
 766         srmmu_set_context(octx);
 767         __restore_flags(flags);
 768         FLUSH_END
 769 }
 770
 771 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 772 {
 773         register unsigned long a, b, c, d, e, f, g;
 774         struct mm_struct *mm = vma->vm_mm;
 775         unsigned long flags, line;
 776         int octx;
 777
 778         FLUSH_BEGIN(mm)
 779         flush_user_windows();
 780         __save_and_cli(flags);
 781         octx = srmmu_get_context();
 782         srmmu_set_context(mm->context);
 783         a = 0x20; b = 0x40; c = 0x60;
 784         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 785
 786         page &= PAGE_MASK;
 787         line = (page + PAGE_SIZE) - 0x100;
 788         goto inside;
 789         do {
 790                 line -= 0x100;
 791         inside:
 792                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 793                                              "sta %%g0, [%0 + %2] %1\n\t"
 794                                              "sta %%g0, [%0 + %3] %1\n\t"
 795                                              "sta %%g0, [%0 + %4] %1\n\t"
 796                                              "sta %%g0, [%0 + %5] %1\n\t"
 797                                              "sta %%g0, [%0 + %6] %1\n\t"
 798                                              "sta %%g0, [%0 + %7] %1\n\t"
 799                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 800                                              "r" (line),
 801                                              "i" (ASI_M_FLUSH_PAGE),
 802                                              "r" (a), "r" (b), "r" (c), "r" (d),
 803                                              "r" (e), "r" (f), "r" (g));
 804         } while(line != page);
 805         srmmu_set_context(octx);
 806         __restore_flags(flags);
 807         FLUSH_END
 808 }
 809
 810 /* Cypress is copy-back, at least that is how we configure it. */
 811 static void cypress_flush_page_to_ram(unsigned long page)
 812 {
 813         register unsigned long a, b, c, d, e, f, g;
 814         unsigned long line;
 815
 816         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 817         page &= PAGE_MASK;
 818         line = (page + PAGE_SIZE) - 0x100;
 819         goto inside;
 820         do {
 821                 line -= 0x100;
 822         inside:
 823                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 824                                      "sta %%g0, [%0 + %2] %1\n\t"
 825                                      "sta %%g0, [%0 + %3] %1\n\t"
 826                                      "sta %%g0, [%0 + %4] %1\n\t"
 827                                      "sta %%g0, [%0 + %5] %1\n\t"
 828                                      "sta %%g0, [%0 + %6] %1\n\t"
 829                                      "sta %%g0, [%0 + %7] %1\n\t"
 830                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 831                                      "r" (line),
 832                                      "i" (ASI_M_FLUSH_PAGE),
 833                                      "r" (a), "r" (b), "r" (c), "r" (d),
 834                                      "r" (e), "r" (f), "r" (g));
 835         } while(line != page);
 836 }
 837
 838 /* Cypress is also IO cache coherent. */
 839 static void cypress_flush_page_for_dma(unsigned long page)
 840 {
 841 }
 842
 843 /* Cypress has unified L2 VIPT, from which both instructions and data
 844  * are stored.  It does not have an onboard icache of any sort, therefore
 845  * no flush is necessary.
 846  */
 847 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 848 {
 849 }
 850
 851 static void cypress_flush_tlb_all(void)
 852 {
 853         srmmu_flush_whole_tlb();
 854 }
 855
 856 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 857 {
 858         FLUSH_BEGIN(mm)
 859         __asm__ __volatile__(
 860         "lda    [%0] %3, %%g5\n\t"
 861         "sta    %2, [%0] %3\n\t"
 862         "sta    %%g0, [%1] %4\n\t"
 863         "sta    %%g5, [%0] %3\n"
 864         : /* no outputs */
 865         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 866           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 867         : "g5");
 868         FLUSH_END
 869 }
 870
 871 static void cypress_flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end)
 872 {
 873         unsigned long size;
 874
 875         FLUSH_BEGIN(mm)
 876         start &= SRMMU_PGDIR_MASK;
 877         size = SRMMU_PGDIR_ALIGN(end) - start;
 878         __asm__ __volatile__(
 879                 "lda    [%0] %5, %%g5\n\t"
 880                 "sta    %1, [%0] %5\n"
 881                 "1:\n\t"
 882                 "subcc  %3, %4, %3\n\t"
 883                 "bne    1b\n\t"
 884                 " sta   %%g0, [%2 + %3] %6\n\t"
 885                 "sta    %%g5, [%0] %5\n"
 886         : /* no outputs */
 887         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 888           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 889           "i" (ASI_M_FLUSH_PROBE)
 890         : "g5", "cc");
 891         FLUSH_END
 892 }
 893
 894 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 895 {
 896         struct mm_struct *mm = vma->vm_mm;
 897
 898         FLUSH_BEGIN(mm)
 899         __asm__ __volatile__(
 900         "lda    [%0] %3, %%g5\n\t"
 901         "sta    %1, [%0] %3\n\t"
 902         "sta    %%g0, [%2] %4\n\t"
 903         "sta    %%g5, [%0] %3\n"
 904         : /* no outputs */
 905         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 906           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 907         : "g5");
 908         FLUSH_END
 909 }
 910
 911 /* viking.S */
 912 extern void viking_flush_cache_all(void);
 913 extern void viking_flush_cache_mm(struct mm_struct *mm);
 914 extern void viking_flush_cache_range(struct mm_struct *mm, unsigned long start,
 915                                      unsigned long end);
 916 extern void viking_flush_cache_page(struct vm_area_struct *vma,
 917                                     unsigned long page);
 918 extern void viking_flush_page_to_ram(unsigned long page);
 919 extern void viking_flush_page_for_dma(unsigned long page);
 920 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
 921 extern void viking_flush_page(unsigned long page);
 922 extern void viking_mxcc_flush_page(unsigned long page);
 923 extern void viking_flush_tlb_all(void);
 924 extern void viking_flush_tlb_mm(struct mm_struct *mm);
 925 extern void viking_flush_tlb_range(struct mm_struct *mm, unsigned long start,
 926                                    unsigned long end);
 927 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
 928                                   unsigned long page);
 929 extern void sun4dsmp_flush_tlb_all(void);
 930 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
 931 extern void sun4dsmp_flush_tlb_range(struct mm_struct *mm, unsigned long start,
 932                                    unsigned long end);
 933 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
 934                                   unsigned long page);
 935
 936 /* hypersparc.S */
 937 extern void hypersparc_flush_cache_all(void);
 938 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
 939 extern void hypersparc_flush_cache_range(struct mm_struct *mm, unsigned long start, unsigned long end);
 940 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 941 extern void hypersparc_flush_page_to_ram(unsigned long page);
 942 extern void hypersparc_flush_page_for_dma(unsigned long page);
 943 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 944 extern void hypersparc_flush_tlb_all(void);
 945 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
 946 extern void hypersparc_flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end);
 947 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 948 extern void hypersparc_setup_blockops(void);
 949
 950 /*
 951  * NOTE: All of this startup code assumes the low 16mb (approx.) of
 952  *       kernel mappings are done with one single contiguous chunk of
 953  *       ram.  On small ram machines (classics mainly) we only get
 954  *       around 8mb mapped for us.
 955  */
 956
 957 void __init early_pgtable_allocfail(char *type)
 958 {
 959         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 960         prom_halt();
 961 }
 962
 963 void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end)
 964 {
 965         pgd_t *pgdp;
 966         pmd_t *pmdp;
 967         pte_t *ptep;
 968
 969         while(start < end) {
 970                 pgdp = pgd_offset_k(start);
 971                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
 972                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 973                         if (pmdp == NULL)
 974                                 early_pgtable_allocfail("pmd");
 975                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
 976                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
 977                 }
 978                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
 979                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
 980                         ptep = (pte_t *)__srmmu_get_nocache(SRMMU_PTE_TABLE_SIZE, SRMMU_PTE_TABLE_SIZE);
 981                         if (ptep == NULL)
 982                                 early_pgtable_allocfail("pte");
 983                         memset(__nocache_fix(ptep), 0, SRMMU_PTE_TABLE_SIZE);
 984                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
 985                 }
 986                 start = (start + SRMMU_PMD_SIZE) & SRMMU_PMD_MASK;
 987         }
 988 }
 989
 990 void __init srmmu_allocate_ptable_skeleton(unsigned long start, unsigned long end)
 991 {
 992         pgd_t *pgdp;
 993         pmd_t *pmdp;
 994         pte_t *ptep;
 995
 996         while(start < end) {
 997                 pgdp = pgd_offset_k(start);
 998                 if(srmmu_pgd_none(*pgdp)) {
 999                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1000                         if (pmdp == NULL)
1001                                 early_pgtable_allocfail("pmd");
1002                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1003                         srmmu_pgd_set(pgdp, pmdp);
1004                 }
1005                 pmdp = srmmu_pmd_offset(pgdp, start);
1006                 if(srmmu_pmd_none(*pmdp)) {
1007                         ptep = (pte_t *)__srmmu_get_nocache(SRMMU_PTE_TABLE_SIZE, SRMMU_PTE_TABLE_SIZE);
1008                         if (ptep == NULL)
1009                                 early_pgtable_allocfail("pte");
1010                         memset(ptep, 0, SRMMU_PTE_TABLE_SIZE);
1011                         srmmu_pmd_set(pmdp, ptep);
1012                 }
1013                 start = (start + SRMMU_PMD_SIZE) & SRMMU_PMD_MASK;
1014         }
1015 }
1016
1017 /*
1018  * This is much cleaner than poking around physical address space
1019  * looking at the prom's page table directly which is what most
1020  * other OS's do.  Yuck... this is much better.
1021  */
1022 void __init srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)
1023 {
1024         pgd_t *pgdp;
1025         pmd_t *pmdp;
1026         pte_t *ptep;
1027         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1028         unsigned long prompte;
1029
1030         while(start <= end) {
1031                 if (start == 0)
1032                         break; /* probably wrap around */
1033                 if(start == 0xfef00000)
1034                         start = KADB_DEBUGGER_BEGVM;
1035                 if(!(prompte = srmmu_hwprobe(start))) {
1036                         start += PAGE_SIZE;
1037                         continue;
1038                 }
1039
1040                 /* A red snapper, see what it really is. */
1041                 what = 0;
1042
1043                 if(!(start & ~(SRMMU_PMD_MASK))) {
1044                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PMD_SIZE) == prompte)
1045                                 what = 1;
1046                 }
1047
1048                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1049                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1050                            prompte)
1051                                 what = 2;
1052                 }
1053
1054                 pgdp = pgd_offset_k(start);
1055                 if(what == 2) {
1056                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1057                         start += SRMMU_PGDIR_SIZE;
1058                         continue;
1059                 }
1060                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1061                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1062                         if (pmdp == NULL)
1063                                 early_pgtable_allocfail("pmd");
1064                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1065                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1066                 }
1067                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1068                 if(what == 1) {
1069                         *(pmd_t *)__nocache_fix(pmdp) = __pmd(prompte);
1070                         start += SRMMU_PMD_SIZE;
1071                         continue;
1072                 }
1073                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1074                         ptep = (pte_t *)__srmmu_get_nocache(SRMMU_PTE_TABLE_SIZE, SRMMU_PTE_TABLE_SIZE);
1075                         if (ptep == NULL)
1076                                 early_pgtable_allocfail("pte");
1077                         memset(__nocache_fix(ptep), 0, SRMMU_PTE_TABLE_SIZE);
1078                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1079                 }
1080                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1081                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1082                 start += PAGE_SIZE;
1083         }
1084 }
1085
1086 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1087
1088 /* Create a third-level SRMMU 16MB page mapping. */
1089 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1090 {
1091         pgd_t *pgdp = pgd_offset_k(vaddr);
1092         unsigned long big_pte;
1093
1094         big_pte = KERNEL_PTE(phys_base >> 4);
1095         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1096 }
1097
1098 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1099 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1100 {
1101         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1102         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1103         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1104         /* Map "low" memory only */
1105         const unsigned long min_vaddr = PAGE_OFFSET;
1106         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1107
1108         if (vstart < min_vaddr || vstart >= max_vaddr)
1109                 return vstart;
1110
1111         if (vend > max_vaddr || vend < min_vaddr)
1112                 vend = max_vaddr;
1113
1114         while(vstart < vend) {
1115                 do_large_mapping(vstart, pstart);
1116                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1117         }
1118         return vstart;
1119 }
1120
1121 static inline void memprobe_error(char *msg)
1122 {
1123         prom_printf(msg);
1124         prom_printf("Halting now...\n");
1125         prom_halt();
1126 }
1127
1128 static inline void map_kernel(void)
1129 {
1130         int i;
1131
1132         if (phys_base > 0) {
1133                 do_large_mapping(PAGE_OFFSET, phys_base);
1134         }
1135
1136         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1137                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1138         }
1139
1140         BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1141 }
1142
1143 /* Paging initialization on the Sparc Reference MMU. */
1144 extern void sparc_context_init(int);
1145
1146 extern int linux_num_cpus;
1147 extern unsigned long totalhigh_pages;
1148
1149 void (*poke_srmmu)(void) __initdata = NULL;
1150
1151 extern unsigned long bootmem_init(unsigned long *pages_avail);
1152 extern void sun_serial_setup(void);
1153
1154 void __init srmmu_paging_init(void)
1155 {
1156         int i, cpunode;
1157         char node_str[128];
1158         pgd_t *pgd;
1159         pmd_t *pmd;
1160         pte_t *pte;
1161         unsigned long pages_avail;
1162
1163         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1164
1165         if (sparc_cpu_model == sun4d)
1166                 num_contexts = 65536; /* We know it is Viking */
1167         else {
1168                 /* Find the number of contexts on the srmmu. */
1169                 cpunode = prom_getchild(prom_root_node);
1170                 num_contexts = 0;
1171                 while(cpunode != 0) {
1172                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1173                         if(!strcmp(node_str, "cpu")) {
1174                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1175                                 break;
1176                         }
1177                         cpunode = prom_getsibling(cpunode);
1178                 }
1179         }
1180
1181         if(!num_contexts) {
1182                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1183                 prom_halt();
1184         }
1185
1186         pages_avail = 0;
1187         last_valid_pfn = bootmem_init(&pages_avail);
1188
1189         srmmu_nocache_calcsize();
1190         srmmu_nocache_init();
1191         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1192         map_kernel();
1193
1194         /* ctx table has to be physically aligned to its size */
1195         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1196         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1197
1198         for(i = 0; i < num_contexts; i++)
1199                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1200
1201         flush_cache_all();
1202         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1203         flush_tlb_all();
1204         poke_srmmu();
1205
1206 #if CONFIG_SUN_IO
1207         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1208         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1209 #endif
1210
1211         srmmu_allocate_ptable_skeleton(fix_kmap_begin, fix_kmap_end);
1212         srmmu_allocate_ptable_skeleton(pkmap_base, pkmap_base_end);
1213
1214         pgd = pgd_offset_k(pkmap_base);
1215         pmd = pmd_offset(pgd, pkmap_base);
1216         pte = pte_offset(pmd, pkmap_base);
1217         pkmap_page_table = pte;
1218
1219         flush_cache_all();
1220         flush_tlb_all();
1221
1222         /*
1223          * This does not logically belong here, but we need to
1224          * call it at the moment we are able to use the bootmem
1225          * allocator.
1226          */
1227         sun_serial_setup();
1228
1229         sparc_context_init(num_contexts);
1230
1231         kmap_init();
1232
1233         {
1234                 unsigned long zones_size[MAX_NR_ZONES];
1235                 unsigned long zholes_size[MAX_NR_ZONES];
1236                 unsigned long npages;
1237                 int znum;
1238
1239                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1240                         zones_size[znum] = zholes_size[znum] = 0;
1241
1242                 npages = max_low_pfn - (phys_base >> PAGE_SHIFT);
1243
1244                 zones_size[ZONE_DMA] = npages;
1245                 zholes_size[ZONE_DMA] = npages - pages_avail;
1246
1247                 npages = highend_pfn - max_low_pfn;
1248                 zones_size[ZONE_HIGHMEM] = npages;
1249                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1250
1251                 free_area_init_node(0, NULL, NULL, zones_size,
1252                                     phys_base, zholes_size);
1253         }
1254 }
1255
1256 static void srmmu_mmu_info(struct seq_file *m)
1257 {
1258         seq_printf(m,
1259                    "MMU type\t: %s\n"
1260                    "contexts\t: %d\n"
1261                    "nocache total\t: %ld\n"
1262                    "nocache used\t: %d\n",
1263                    srmmu_name,
1264                    num_contexts,
1265                    srmmu_nocache_size,
1266                    (srmmu_nocache_used << SRMMU_NOCACHE_BITMAP_SHIFT));
1267 }
1268
1269 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1270 {
1271 }
1272
1273 static void srmmu_destroy_context(struct mm_struct *mm)
1274 {
1275
1276         if(mm->context != NO_CONTEXT) {
1277                 flush_cache_mm(mm);
1278                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1279                 flush_tlb_mm(mm);
1280                 spin_lock(&srmmu_context_spinlock);
1281                 free_context(mm->context);
1282                 spin_unlock(&srmmu_context_spinlock);
1283                 mm->context = NO_CONTEXT;
1284         }
1285 }
1286
1287 /* Init various srmmu chip types. */
1288 static void __init srmmu_is_bad(void)
1289 {
1290         prom_printf("Could not determine SRMMU chip type.\n");
1291         prom_halt();
1292 }
1293
1294 static void __init init_vac_layout(void)
1295 {
1296         int nd, cache_lines;
1297         char node_str[128];
1298 #ifdef CONFIG_SMP
1299         int cpu = 0;
1300         unsigned long max_size = 0;
1301         unsigned long min_line_size = 0x10000000;
1302 #endif
1303
1304         nd = prom_getchild(prom_root_node);
1305         while((nd = prom_getsibling(nd)) != 0) {
1306                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1307                 if(!strcmp(node_str, "cpu")) {
1308                         vac_line_size = prom_getint(nd, "cache-line-size");
1309                         if (vac_line_size == -1) {
1310                                 prom_printf("can't determine cache-line-size, "
1311                                             "halting.\n");
1312                                 prom_halt();
1313                         }
1314                         cache_lines = prom_getint(nd, "cache-nlines");
1315                         if (cache_lines == -1) {
1316                                 prom_printf("can't determine cache-nlines, halting.\n");
1317                                 prom_halt();
1318                         }
1319
1320                         vac_cache_size = cache_lines * vac_line_size;
1321 #ifdef CONFIG_SMP
1322                         if(vac_cache_size > max_size)
1323                                 max_size = vac_cache_size;
1324                         if(vac_line_size < min_line_size)
1325                                 min_line_size = vac_line_size;
1326                         cpu++;
1327                         if(cpu == smp_num_cpus)
1328                                 break;
1329 #else
1330                         break;
1331 #endif
1332                 }
1333         }
1334         if(nd == 0) {
1335                 prom_printf("No CPU nodes found, halting.\n");
1336                 prom_halt();
1337         }
1338 #ifdef CONFIG_SMP
1339         vac_cache_size = max_size;
1340         vac_line_size = min_line_size;
1341 #endif
1342         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1343                (int)vac_cache_size, (int)vac_line_size);
1344 }
1345
1346 static void __init poke_hypersparc(void)
1347 {
1348         volatile unsigned long clear;
1349         unsigned long mreg = srmmu_get_mmureg();
1350
1351         hyper_flush_unconditional_combined();
1352
1353         mreg &= ~(HYPERSPARC_CWENABLE);
1354         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1355         mreg |= (HYPERSPARC_CMODE);
1356
1357         srmmu_set_mmureg(mreg);
1358
1359 #if 0 /* XXX I think this is bad news... -DaveM */
1360         hyper_clear_all_tags();
1361 #endif
1362
1363         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1364         hyper_flush_whole_icache();
1365         clear = srmmu_get_faddr();
1366         clear = srmmu_get_fstatus();
1367 }
1368
1369 static void __init init_hypersparc(void)
1370 {
1371         srmmu_name = "ROSS HyperSparc";
1372
1373         init_vac_layout();
1374
1375         is_hypersparc = 1;
1376
1377         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1378         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1379         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1380         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1381         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1382         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1383         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1384
1385         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1386         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1387         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1388         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1389
1390         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1391         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1392         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1393
1394
1395         poke_srmmu = poke_hypersparc;
1396
1397         hypersparc_setup_blockops();
1398 }
1399
1400 static void __init poke_cypress(void)
1401 {
1402         unsigned long mreg = srmmu_get_mmureg();
1403         unsigned long faddr, tagval;
1404         volatile unsigned long cypress_sucks;
1405         volatile unsigned long clear;
1406
1407         clear = srmmu_get_faddr();
1408         clear = srmmu_get_fstatus();
1409
1410         if (!(mreg & CYPRESS_CENABLE)) {
1411                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1412                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1413                                              "sta %%g0, [%0] %2\n\t" : :
1414                                              "r" (faddr), "r" (0x40000),
1415                                              "i" (ASI_M_DATAC_TAG));
1416                 }
1417         } else {
1418                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1419                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1420                                              "=r" (tagval) :
1421                                              "r" (faddr), "r" (0x40000),
1422                                              "i" (ASI_M_DATAC_TAG));
1423
1424                         /* If modified and valid, kick it. */
1425                         if((tagval & 0x60) == 0x60)
1426                                 cypress_sucks = *(unsigned long *)
1427                                                         (0xf0020000 + faddr);
1428                 }
1429         }
1430
1431         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1432         clear = srmmu_get_faddr();
1433         clear = srmmu_get_fstatus();
1434
1435         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1436         srmmu_set_mmureg(mreg);
1437 }
1438
1439 static void __init init_cypress_common(void)
1440 {
1441         init_vac_layout();
1442
1443         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1444         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1445         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1446         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1447         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1448         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1449         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1450
1451         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1452         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1453         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1454         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1455
1456
1457         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1458         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1459         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1460
1461         poke_srmmu = poke_cypress;
1462 }
1463
1464 static void __init init_cypress_604(void)
1465 {
1466         srmmu_name = "ROSS Cypress-604(UP)";
1467         srmmu_modtype = Cypress;
1468         init_cypress_common();
1469 }
1470
1471 static void __init init_cypress_605(unsigned long mrev)
1472 {
1473         srmmu_name = "ROSS Cypress-605(MP)";
1474         if(mrev == 0xe) {
1475                 srmmu_modtype = Cypress_vE;
1476                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1477         } else {
1478                 if(mrev == 0xd) {
1479                         srmmu_modtype = Cypress_vD;
1480                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1481                 } else {
1482                         srmmu_modtype = Cypress;
1483                 }
1484         }
1485         init_cypress_common();
1486 }
1487
1488 static void __init poke_swift(void)
1489 {
1490         unsigned long mreg;
1491
1492         /* Clear any crap from the cache or else... */
1493         swift_flush_cache_all();
1494
1495         /* Enable I & D caches */
1496         mreg = srmmu_get_mmureg();
1497         mreg |= (SWIFT_IE | SWIFT_DE);
1498         /*
1499          * The Swift branch folding logic is completely broken.  At
1500          * trap time, if things are just right, if can mistakenly
1501          * think that a trap is coming from kernel mode when in fact
1502          * it is coming from user mode (it mis-executes the branch in
1503          * the trap code).  So you see things like crashme completely
1504          * hosing your machine which is completely unacceptable.  Turn
1505          * this shit off... nice job Fujitsu.
1506          */
1507         mreg &= ~(SWIFT_BF);
1508         srmmu_set_mmureg(mreg);
1509 }
1510
1511 #define SWIFT_MASKID_ADDR  0x10003018
1512 static void __init init_swift(void)
1513 {
1514         unsigned long swift_rev;
1515
1516         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1517                              "srl %0, 0x18, %0\n\t" :
1518                              "=r" (swift_rev) :
1519                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1520         srmmu_name = "Fujitsu Swift";
1521         switch(swift_rev) {
1522         case 0x11:
1523         case 0x20:
1524         case 0x23:
1525         case 0x30:
1526                 srmmu_modtype = Swift_lots_o_bugs;
1527                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1528                 /*
1529                  * Gee george, I wonder why Sun is so hush hush about
1530                  * this hardware bug... really braindamage stuff going
1531                  * on here.  However I think we can find a way to avoid
1532                  * all of the workaround overhead under Linux.  Basically,
1533                  * any page fault can cause kernel pages to become user
1534                  * accessible (the mmu gets confused and clears some of
1535                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1536                  * horrible eh?  But wait, after extensive testing it appears
1537                  * that if you use pgd_t level large kernel pte's (like the
1538                  * 4MB pages on the Pentium) the bug does not get tripped
1539                  * at all.  This avoids almost all of the major overhead.
1540                  * Welcome to a world where your vendor tells you to,
1541                  * "apply this kernel patch" instead of "sorry for the
1542                  * broken hardware, send it back and we'll give you
1543                  * properly functioning parts"
1544                  */
1545                 break;
1546         case 0x25:
1547         case 0x31:
1548                 srmmu_modtype = Swift_bad_c;
1549                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1550                 /*
1551                  * You see Sun allude to this hardware bug but never
1552                  * admit things directly, they'll say things like,
1553                  * "the Swift chip cache problems" or similar.
1554                  */
1555                 break;
1556         default:
1557                 srmmu_modtype = Swift_ok;
1558                 break;
1559         };
1560
1561         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1562         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1563         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1564         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1565
1566
1567         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1568         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1569         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1570         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1571
1572         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1573         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1574         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1575
1576         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1577
1578         flush_page_for_dma_global = 0;
1579
1580         /*
1581          * Are you now convinced that the Swift is one of the
1582          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1583          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1584          * you examined the microcode of the Swift you'd find
1585          * XXX's all over the place.
1586          */
1587         poke_srmmu = poke_swift;
1588 }
1589
1590 static void turbosparc_flush_cache_all(void)
1591 {
1592         flush_user_windows();
1593         turbosparc_idflash_clear();
1594 }
1595
1596 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1597 {
1598         FLUSH_BEGIN(mm)
1599         flush_user_windows();
1600         turbosparc_idflash_clear();
1601         FLUSH_END
1602 }
1603
1604 static void turbosparc_flush_cache_range(struct mm_struct *mm, unsigned long start, unsigned long end)
1605 {
1606         FLUSH_BEGIN(mm)
1607         flush_user_windows();
1608         turbosparc_idflash_clear();
1609         FLUSH_END
1610 }
1611
1612 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1613 {
1614         FLUSH_BEGIN(vma->vm_mm)
1615         flush_user_windows();
1616         if (vma->vm_flags & VM_EXEC)
1617                 turbosparc_flush_icache();
1618         turbosparc_flush_dcache();
1619         FLUSH_END
1620 }
1621
1622 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1623 static void turbosparc_flush_page_to_ram(unsigned long page)
1624 {
1625 #ifdef TURBOSPARC_WRITEBACK
1626         volatile unsigned long clear;
1627
1628         if (srmmu_hwprobe(page))
1629                 turbosparc_flush_page_cache(page);
1630         clear = srmmu_get_fstatus();
1631 #endif
1632 }
1633
1634 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1635 {
1636 }
1637
1638 static void turbosparc_flush_page_for_dma(unsigned long page)
1639 {
1640         turbosparc_flush_dcache();
1641 }
1642
1643 static void turbosparc_flush_tlb_all(void)
1644 {
1645         srmmu_flush_whole_tlb();
1646 }
1647
1648 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1649 {
1650         FLUSH_BEGIN(mm)
1651         srmmu_flush_whole_tlb();
1652         FLUSH_END
1653 }
1654
1655 static void turbosparc_flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end)
1656 {
1657         FLUSH_BEGIN(mm)
1658         srmmu_flush_whole_tlb();
1659         FLUSH_END
1660 }
1661
1662 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1663 {
1664         FLUSH_BEGIN(vma->vm_mm)
1665         srmmu_flush_whole_tlb();
1666         FLUSH_END
1667 }
1668
1669
1670 static void __init poke_turbosparc(void)
1671 {
1672         unsigned long mreg = srmmu_get_mmureg();
1673         unsigned long ccreg;
1674
1675         /* Clear any crap from the cache or else... */
1676         turbosparc_flush_cache_all();
1677         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1678         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1679         srmmu_set_mmureg(mreg);
1680
1681         ccreg = turbosparc_get_ccreg();
1682
1683 #ifdef TURBOSPARC_WRITEBACK
1684         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1685         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1686                         /* Write-back D-cache, emulate VLSI
1687                          * abortion number three, not number one */
1688 #else
1689         /* For now let's play safe, optimize later */
1690         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1691                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1692         ccreg &= ~(TURBOSPARC_uS2);
1693                         /* Emulate VLSI abortion number three, not number one */
1694 #endif
1695
1696         switch (ccreg & 7) {
1697         case 0: /* No SE cache */
1698         case 7: /* Test mode */
1699                 break;
1700         default:
1701                 ccreg |= (TURBOSPARC_SCENABLE);
1702         }
1703         turbosparc_set_ccreg (ccreg);
1704
1705         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1706         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1707         srmmu_set_mmureg(mreg);
1708 }
1709
1710 static void __init init_turbosparc(void)
1711 {
1712         srmmu_name = "Fujitsu TurboSparc";
1713         srmmu_modtype = TurboSparc;
1714
1715         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1716         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1717         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1718         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1719
1720         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1721         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1722         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1723         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1724
1725         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1726
1727         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1728         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1729
1730         poke_srmmu = poke_turbosparc;
1731 }
1732
1733 static void __init poke_tsunami(void)
1734 {
1735         unsigned long mreg = srmmu_get_mmureg();
1736
1737         tsunami_flush_icache();
1738         tsunami_flush_dcache();
1739         mreg &= ~TSUNAMI_ITD;
1740         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1741         srmmu_set_mmureg(mreg);
1742 }
1743
1744 static void __init init_tsunami(void)
1745 {
1746         /*
1747          * Tsunami's pretty sane, Sun and TI actually got it
1748          * somewhat right this time.  Fujitsu should have
1749          * taken some lessons from them.
1750          */
1751
1752         srmmu_name = "TI Tsunami";
1753         srmmu_modtype = Tsunami;
1754
1755         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1756         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1757         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1758         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1759
1760
1761         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1762         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1763         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1764         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1765
1766         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1767         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1768         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1769
1770         poke_srmmu = poke_tsunami;
1771
1772         tsunami_setup_blockops();
1773 }
1774
1775 static void __init poke_viking(void)
1776 {
1777         unsigned long mreg = srmmu_get_mmureg();
1778         static int smp_catch;
1779
1780         if(viking_mxcc_present) {
1781                 unsigned long mxcc_control = mxcc_get_creg();
1782
1783                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1784                 mxcc_control &= ~(MXCC_CTL_RRC);
1785                 mxcc_set_creg(mxcc_control);
1786
1787                 /*
1788                  * We don't need memory parity checks.
1789                  * XXX This is a mess, have to dig out later. ecd.
1790                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1791                  */
1792
1793                 /* We do cache ptables on MXCC. */
1794                 mreg |= VIKING_TCENABLE;
1795         } else {
1796                 unsigned long bpreg;
1797
1798                 mreg &= ~(VIKING_TCENABLE);
1799                 if(smp_catch++) {
1800                         /* Must disable mixed-cmd mode here for other cpu's. */
1801                         bpreg = viking_get_bpreg();
1802                         bpreg &= ~(VIKING_ACTION_MIX);
1803                         viking_set_bpreg(bpreg);
1804
1805                         /* Just in case PROM does something funny. */
1806                         msi_set_sync();
1807                 }
1808         }
1809
1810         mreg |= VIKING_SPENABLE;
1811         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1812         mreg |= VIKING_SBENABLE;
1813         mreg &= ~(VIKING_ACENABLE);
1814         srmmu_set_mmureg(mreg);
1815
1816 #ifdef CONFIG_SMP
1817         /* Avoid unnecessary cross calls. */
1818         BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
1819         BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
1820         BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
1821         BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
1822         BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
1823         BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
1824         BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
1825         btfixup();
1826 #endif
1827 }
1828
1829 static void __init init_viking(void)
1830 {
1831         unsigned long mreg = srmmu_get_mmureg();
1832
1833         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1834         if(mreg & VIKING_MMODE) {
1835                 srmmu_name = "TI Viking";
1836                 viking_mxcc_present = 0;
1837                 msi_set_sync();
1838
1839                 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1840                 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1841                 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1842
1843                 /*
1844                  * We need this to make sure old viking takes no hits
1845                  * on it's cache for dma snoops to workaround the
1846                  * "load from non-cacheable memory" interrupt bug.
1847                  * This is only necessary because of the new way in
1848                  * which we use the IOMMU.
1849                  */
1850                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1851
1852                 flush_page_for_dma_global = 0;
1853         } else {
1854                 srmmu_name = "TI Viking/MXCC";
1855                 viking_mxcc_present = 1;
1856
1857                 srmmu_cache_pagetables = 1;
1858
1859                 /* MXCC vikings lack the DMA snooping bug. */
1860                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1861         }
1862
1863         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1864         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1865         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1866         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1867
1868 #ifdef CONFIG_SMP
1869         if (sparc_cpu_model == sun4d) {
1870                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1871                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1872                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1873                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1874         } else
1875 #endif
1876         {
1877                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1878                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1879                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1880                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1881         }
1882
1883         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1884         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1885
1886         poke_srmmu = poke_viking;
1887 }
1888
1889 /* Probe for the srmmu chip version. */
1890 static void __init get_srmmu_type(void)
1891 {
1892         unsigned long mreg, psr;
1893         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1894
1895         srmmu_modtype = SRMMU_INVAL_MOD;
1896         hwbug_bitmask = 0;
1897
1898         mreg = srmmu_get_mmureg(); psr = get_psr();
1899         mod_typ = (mreg & 0xf0000000) >> 28;
1900         mod_rev = (mreg & 0x0f000000) >> 24;
1901         psr_typ = (psr >> 28) & 0xf;
1902         psr_vers = (psr >> 24) & 0xf;
1903
1904         /* First, check for HyperSparc or Cypress. */
1905         if(mod_typ == 1) {
1906                 switch(mod_rev) {
1907                 case 7:
1908                         /* UP or MP Hypersparc */
1909                         init_hypersparc();
1910                         break;
1911                 case 0:
1912                 case 2:
1913                         /* Uniprocessor Cypress */
1914                         init_cypress_604();
1915                         break;
1916                 case 10:
1917                 case 11:
1918                 case 12:
1919                         /* _REALLY OLD_ Cypress MP chips... */
1920                 case 13:
1921                 case 14:
1922                 case 15:
1923                         /* MP Cypress mmu/cache-controller */
1924                         init_cypress_605(mod_rev);
1925                         break;
1926                 default:
1927                         /* Some other Cypress revision, assume a 605. */
1928                         init_cypress_605(mod_rev);
1929                         break;
1930                 };
1931                 return;
1932         }
1933
1934         /*
1935          * Now Fujitsu TurboSparc. It might happen that it is
1936          * in Swift emulation mode, so we will check later...
1937          */
1938         if (psr_typ == 0 && psr_vers == 5) {
1939                 init_turbosparc();
1940                 return;
1941         }
1942
1943         /* Next check for Fujitsu Swift. */
1944         if(psr_typ == 0 && psr_vers == 4) {
1945                 int cpunode;
1946                 char node_str[128];
1947
1948                 /* Look if it is not a TurboSparc emulating Swift... */
1949                 cpunode = prom_getchild(prom_root_node);
1950                 while((cpunode = prom_getsibling(cpunode)) != 0) {
1951                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1952                         if(!strcmp(node_str, "cpu")) {
1953                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1954                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1955                                         init_turbosparc();
1956                                         return;
1957                                 }
1958                                 break;
1959                         }
1960                 }
1961
1962                 init_swift();
1963                 return;
1964         }
1965
1966         /* Now the Viking family of srmmu. */
1967         if(psr_typ == 4 &&
1968            ((psr_vers == 0) ||
1969             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1970                 init_viking();
1971                 return;
1972         }
1973
1974         /* Finally the Tsunami. */
1975         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1976                 init_tsunami();
1977                 return;
1978         }
1979
1980         /* Oh well */
1981         srmmu_is_bad();
1982 }
1983
1984 /* dont laugh, static pagetables */
1985 static int srmmu_check_pgt_cache(int low, int high)
1986 {
1987         return 0;
1988 }
1989
1990 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
1991         tsetup_mmu_patchme, rtrap_mmu_patchme;
1992
1993 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
1994         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
1995
1996 extern unsigned long srmmu_fault;
1997
1998 #define PATCH_BRANCH(insn, dest) do { \
1999                 iaddr = &(insn); \
2000                 daddr = &(dest); \
2001                 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2002         } while(0);
2003
2004 static void __init patch_window_trap_handlers(void)
2005 {
2006         unsigned long *iaddr, *daddr;
2007
2008         PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2009         PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2010         PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2011         PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2012         PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2013         PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2014         PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2015 }
2016
2017 #ifdef CONFIG_SMP
2018 /* Local cross-calls. */
2019 static void smp_flush_page_for_dma(unsigned long page)
2020 {
2021         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2022         local_flush_page_for_dma(page);
2023 }
2024
2025 #endif
2026
2027 /* Load up routines and constants for sun4m and sun4d mmu */
2028 void __init ld_mmu_srmmu(void)
2029 {
2030         extern void ld_mmu_iommu(void);
2031         extern void ld_mmu_iounit(void);
2032         extern void ___xchg32_sun4md(void);
2033
2034         /* First the constants */
2035         BTFIXUPSET_SIMM13(pmd_shift, SRMMU_PMD_SHIFT);
2036         BTFIXUPSET_SETHI(pmd_size, SRMMU_PMD_SIZE);
2037         BTFIXUPSET_SETHI(pmd_mask, SRMMU_PMD_MASK);
2038         BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2039         BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2040         BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2041
2042         BTFIXUPSET_SIMM13(ptrs_per_pte, SRMMU_PTRS_PER_PTE);
2043         BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2044         BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2045
2046         BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2047         BTFIXUPSET_INT(page_shared, pgprot_val(SRMMU_PAGE_SHARED));
2048         BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2049         BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2050         BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2051         page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2052         pg_iobits = SRMMU_VALID | SRMMU_WRITE | SRMMU_REF;
2053
2054         /* Functions */
2055 #ifndef CONFIG_SMP
2056         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2057 #endif
2058         BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NORM);
2059
2060         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2061         BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2062
2063         BTFIXUPSET_CALL(pte_page, srmmu_pte_page, BTFIXUPCALL_NORM);
2064         BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2065         BTFIXUPSET_CALL(pgd_page, srmmu_pgd_page, BTFIXUPCALL_NORM);
2066
2067         BTFIXUPSET_SETHI(none_mask, 0xF0000000); /* XXX P3: is it used? */
2068
2069         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2070         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2071
2072         BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2073         BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2074         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2075
2076         BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2077         BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2078         BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2079         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2080
2081         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2082         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2083         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2084         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2085         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2086
2087         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2088         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2089         BTFIXUPSET_CALL(pte_offset, srmmu_pte_offset, BTFIXUPCALL_NORM);
2090         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2091         BTFIXUPSET_CALL(pte_alloc_one_fast, srmmu_pte_alloc_one_fast, BTFIXUPCALL_NORM);
2092         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2093         BTFIXUPSET_CALL(free_pmd_fast, srmmu_free_pmd_fast, BTFIXUPCALL_NORM);
2094         BTFIXUPSET_CALL(pmd_alloc_one_fast, srmmu_pmd_alloc_one_fast, BTFIXUPCALL_NORM);
2095         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2096         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2097
2098         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2099         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2100         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2101         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2102         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2103         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2104         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2105         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2106         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2107         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2108         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2109
2110         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2111
2112         /* Task struct and kernel stack allocating/freeing. */
2113         BTFIXUPSET_CALL(alloc_task_struct, srmmu_alloc_task_struct, BTFIXUPCALL_NORM);
2114         BTFIXUPSET_CALL(free_task_struct, srmmu_free_task_struct, BTFIXUPCALL_NORM);
2115         BTFIXUPSET_CALL(get_task_struct, srmmu_get_task_struct, BTFIXUPCALL_NORM);
2116
2117         get_srmmu_type();
2118         patch_window_trap_handlers();
2119
2120 #ifdef CONFIG_SMP
2121         /* El switcheroo... */
2122
2123         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2124         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2125         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2126         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2127         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2128         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2129         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2130         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2131         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2132         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2133         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2134
2135         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2136         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2137         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2138         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2139         if (sparc_cpu_model != sun4d) {
2140                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2141                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2142                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2143                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2144         }
2145         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2146         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2147         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2148 #endif
2149
2150         if (sparc_cpu_model == sun4d)
2151                 ld_mmu_iounit();
2152         else
2153                 ld_mmu_iommu();
2154 #ifdef CONFIG_SMP
2155         if (sparc_cpu_model == sun4d)
2156                 sun4d_init_smp();
2157         else
2158                 sun4m_init_smp();
2159 #endif
2160 }