2 * eisa.c - provide support for EISA adapters in PA-RISC machines
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
10 * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
12 * There are two distinct EISA adapters. Mongoose is found in machines
13 * before the 712; then the Wax ASIC is used. To complicate matters, the
14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15 * dealt with elsewhere; this file is concerned only with the EISA portions
21 * To allow an ISA card to work properly in the EISA slot you need to
22 * set an edge trigger level. This may be done on the palo command line
23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
24 * n and n2 as the irq levels you want to use.
26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
27 * irq levels 10 and 11.
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/irq.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
39 #include <asm/byteorder.h>
41 #include <asm/hardware.h>
42 #include <asm/processor.h>
43 #include <asm/delay.h>
44 #include <asm/eisa_bus.h>
47 #define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
49 #define EISA_DBG(msg, arg... )
52 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
53 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
55 static spinlock_t eisa_irq_lock = SPIN_LOCK_UNLOCKED;
57 /* We can only have one EISA adapter in the system because neither
58 * implementation can be flexed.
60 static struct eisa_ba {
61 struct pci_hba_data hba;
62 unsigned long eeprom_addr;
67 static inline unsigned long eisa_permute(unsigned short port)
70 return 0xfc000000 | ((port & 0xfc00) >> 6)
71 | ((port & 0x3f8) << 9) | (port & 7);
73 return 0xfc000000 | port;
77 unsigned char eisa_in8(unsigned short port)
80 return gsc_readb(eisa_permute(port));
84 unsigned short eisa_in16(unsigned short port)
87 return le16_to_cpu(gsc_readw(eisa_permute(port)));
91 unsigned int eisa_in32(unsigned short port)
94 return le32_to_cpu(gsc_readl(eisa_permute(port)));
98 void eisa_out8(unsigned char data, unsigned short port)
101 gsc_writeb(data, eisa_permute(port));
104 void eisa_out16(unsigned short data, unsigned short port)
107 gsc_writew(cpu_to_le16(data), eisa_permute(port));
110 void eisa_out32(unsigned int data, unsigned short port)
113 gsc_writel(cpu_to_le32(data), eisa_permute(port));
116 /* Interrupt handling */
118 /* cached interrupt mask registers */
119 static int master_mask;
120 static int slave_mask;
122 /* the trig level can be set with the
123 * eisa_irq_edge=n,n,n commandline parameter
124 * We should really read this from the EEPROM
127 /* irq 13,8,2,1,0 must be edge */
128 static unsigned int eisa_irq_level; /* default to edge triggered */
131 /* called by free irq */
132 static void eisa_disable_irq(void *irq_dev, int irq)
136 EISA_DBG("disable irq %d\n", irq);
137 /* just mask for now */
138 spin_lock_irqsave(&eisa_irq_lock, flags);
140 slave_mask |= (1 << (irq&7));
141 eisa_out8(slave_mask, 0xa1);
143 master_mask |= (1 << (irq&7));
144 eisa_out8(master_mask, 0x21);
146 spin_unlock_irqrestore(&eisa_irq_lock, flags);
147 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
148 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
151 /* called by request irq */
152 static void eisa_enable_irq(void *irq_dev, int irq)
155 EISA_DBG("enable irq %d\n", irq);
157 spin_lock_irqsave(&eisa_irq_lock, flags);
159 slave_mask &= ~(1 << (irq&7));
160 eisa_out8(slave_mask, 0xa1);
162 master_mask &= ~(1 << (irq&7));
163 eisa_out8(master_mask, 0x21);
165 spin_unlock_irqrestore(&eisa_irq_lock, flags);
166 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
167 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
170 static void eisa_mask_irq(void *irq_dev, int irq)
173 EISA_DBG("mask irq %d\n", irq);
176 spin_lock_irqsave(&eisa_irq_lock, flags);
178 slave_mask |= (1 << (irq&7));
179 eisa_out8(slave_mask, 0xa1);
181 master_mask |= (1 << (irq&7));
182 eisa_out8(master_mask, 0x21);
184 spin_unlock_irqrestore(&eisa_irq_lock, flags);
187 static void eisa_unmask_irq(void *irq_dev, int irq)
190 EISA_DBG("unmask irq %d\n", irq);
193 spin_lock_irqsave(&eisa_irq_lock, flags);
195 slave_mask &= ~(1 << (irq&7));
196 eisa_out8(slave_mask, 0xa1);
198 master_mask &= ~(1 << (irq&7));
199 eisa_out8(master_mask, 0x21);
201 spin_unlock_irqrestore(&eisa_irq_lock, flags);
204 static struct irqaction action[IRQ_PER_REGION];
206 /* EISA needs to be fixed at IRQ region #0 (EISA_IRQ_REGION) */
207 static struct irq_region eisa_irq_region = {
208 ops: { eisa_disable_irq, eisa_enable_irq, eisa_mask_irq, eisa_unmask_irq },
209 data: { name: "EISA", irqbase: 0 },
213 static void eisa_irq(int _, void *intr_dev, struct pt_regs *regs)
215 extern void do_irq(struct irqaction *a, int i, struct pt_regs *p);
216 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
219 spin_lock_irqsave(&eisa_irq_lock, flags);
220 /* read IRR command */
221 eisa_out8(0x0a, 0x20);
222 eisa_out8(0x0a, 0xa0);
224 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
225 irq, eisa_in8(0x20), eisa_in8(0xa0));
227 /* read ISR command */
228 eisa_out8(0x0a, 0x20);
229 eisa_out8(0x0a, 0xa0);
230 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
231 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
235 /* mask irq and write eoi */
237 slave_mask |= (1 << (irq&7));
238 eisa_out8(slave_mask, 0xa1);
239 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
240 eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
243 master_mask |= (1 << (irq&7));
244 eisa_out8(master_mask, 0x21);
245 eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */
247 spin_unlock_irqrestore(&eisa_irq_lock, flags);
250 do_irq(&eisa_irq_region.action[irq], EISA_IRQ_REGION + irq, regs);
252 spin_lock_irqsave(&eisa_irq_lock, flags);
255 slave_mask &= ~(1 << (irq&7));
256 eisa_out8(slave_mask, 0xa1);
258 master_mask &= ~(1 << (irq&7));
259 eisa_out8(master_mask, 0x21);
261 spin_unlock_irqrestore(&eisa_irq_lock, flags);
264 static void dummy_irq2_handler(int _, void *dev, struct pt_regs *regs)
266 printk(KERN_ALERT "eisa: uhh, irq2?\n");
269 static void init_eisa_pic(void)
273 spin_lock_irqsave(&eisa_irq_lock, flags);
275 eisa_out8(0xff, 0x21); /* mask during init */
276 eisa_out8(0xff, 0xa1); /* mask during init */
279 eisa_out8(0x11,0x20); /* ICW1 */
280 eisa_out8(0x00,0x21); /* ICW2 */
281 eisa_out8(0x04,0x21); /* ICW3 */
282 eisa_out8(0x01,0x21); /* ICW4 */
283 eisa_out8(0x40,0x20); /* OCW2 */
286 eisa_out8(0x11,0xa0); /* ICW1 */
287 eisa_out8(0x08,0xa1); /* ICW2 */
288 eisa_out8(0x02,0xa1); /* ICW3 */
289 eisa_out8(0x01,0xa1); /* ICW4 */
290 eisa_out8(0x40,0xa0); /* OCW2 */
296 eisa_out8(slave_mask, 0xa1); /* OCW1 */
297 eisa_out8(master_mask, 0x21); /* OCW1 */
299 /* setup trig level */
300 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
302 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
303 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
305 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
306 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
307 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
308 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
310 spin_unlock_irqrestore(&eisa_irq_lock, flags);
313 /* Device initialisation */
315 #define is_mongoose(dev) (dev->id.sversion == 0x00076)
317 static int __devinit eisa_probe(struct parisc_device *dev)
321 char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
323 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
326 eisa_dev.hba.dev = dev;
327 eisa_dev.hba.iommu = ccio_get_iommu(dev);
329 eisa_dev.hba.lmmio_space.name = "EISA";
330 eisa_dev.hba.lmmio_space.start = (unsigned long) 0xfffffffffc000000;
331 eisa_dev.hba.lmmio_space.end = (unsigned long) 0xffffffffffbfffff;
332 eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
333 result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
335 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
338 eisa_dev.hba.io_space.name = "EISA";
339 eisa_dev.hba.io_space.start = 0;
340 eisa_dev.hba.io_space.end = 0xffff;
341 eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
342 result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
344 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
347 pcibios_register_hba(&eisa_dev.hba);
349 result = request_irq(dev->irq, eisa_irq, SA_SHIRQ, "EISA", NULL);
351 printk(KERN_ERR "EISA: request_irq failed!\n");
356 action[2].handler = dummy_irq2_handler;
357 action[2].name = "cascade";
359 eisa_irq_region.data.dev = dev;
360 irq_region[0] = &eisa_irq_region;
363 if (dev->num_addrs) {
364 /* newer firmware hand out the eeprom address */
365 eisa_dev.eeprom_addr = dev->addr[0];
367 /* old firmware, need to figure out the box */
368 if (is_mongoose(dev)) {
369 eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
371 eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
374 eisa_eeprom_init(eisa_dev.eeprom_addr);
375 eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space, &eisa_dev.hba.lmmio_space);
381 static struct parisc_device_id __devinitdata eisa_tbl[] = {
382 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
383 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
387 MODULE_DEVICE_TABLE(parisc, eisa_tbl);
389 static struct parisc_driver eisa_driver = {
390 name: "EISA Bus Adapter",
395 void __init eisa_init(void)
397 register_parisc_driver(&eisa_driver);
401 static unsigned int eisa_irq_configured;
402 void eisa_make_irq_level(int num)
404 if (eisa_irq_configured& (1<<num)) {
406 "IRQ %d polarity configured twice (last to level)\n",
409 eisa_irq_level |= (1<<num); /* set the corresponding bit */
410 eisa_irq_configured |= (1<<num); /* set the corresponding bit */
413 void eisa_make_irq_edge(int num)
415 if (eisa_irq_configured& (1<<num)) {
417 "IRQ %d polarity configured twice (last to edge)\n",
420 eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
421 eisa_irq_configured |= (1<<num); /* set the corresponding bit */
424 static int __init eisa_irq_setup(char *str)
429 EISA_DBG("IRQ setup\n");
430 while (cur != NULL) {
433 val = (int) simple_strtoul(cur, &pe, 0);
434 if (val > 15 || val < 0) {
435 printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
441 eisa_make_irq_edge(val); /* clear the corresponding bit */
442 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
444 if ((cur = strchr(cur, ','))) {
453 __setup("eisa_irq_edge=", eisa_irq_setup);