2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>, <dely.l.sy@intel.com>
30 #include <linux/config.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/types.h>
34 #include <linux/slab.h>
35 #include <linux/vmalloc.h>
36 #include <linux/interrupt.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <asm/system.h>
43 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
44 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
45 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
46 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
47 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
48 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
49 /* Redefine this flagword to set debug level */
50 #define DEBUG_LEVEL DBG_K_STANDARD
52 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
54 #define DBG_PRINT( dbg_flags, args... ) \
56 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
59 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
60 __FILE__, __LINE__, __FUNCTION__ ); \
61 sprintf( __dbg_str_buf + len, args ); \
62 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
66 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
67 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
69 #define DEFINE_DBG_BUFFER
70 #define DBG_ENTER_ROUTINE
71 #define DBG_LEAVE_ROUTINE
90 } __attribute__ ((packed));
92 /* offsets to the controller registers based on the above structure layout */
94 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
95 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
96 CAPREG = offsetof(struct ctrl_reg, cap_reg),
97 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
98 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
99 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
100 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
101 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
102 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
103 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
104 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
105 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
106 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
107 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
109 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
111 #define PCIE_CAP_ID ( pcie_cap_base + PCIECAPID )
112 #define NXT_CAP_PTR ( pcie_cap_base + NXTCAPPTR )
113 #define CAP_REG ( pcie_cap_base + CAPREG )
114 #define DEV_CAP ( pcie_cap_base + DEVCAP )
115 #define DEV_CTRL ( pcie_cap_base + DEVCTRL )
116 #define DEV_STATUS ( pcie_cap_base + DEVSTATUS )
117 #define LNK_CAP ( pcie_cap_base + LNKCAP )
118 #define LNK_CTRL ( pcie_cap_base + LNKCTRL )
119 #define LNK_STATUS ( pcie_cap_base + LNKSTATUS )
120 #define SLOT_CAP ( pcie_cap_base + SLOTCAP )
121 #define SLOT_CTRL ( pcie_cap_base + SLOTCTRL )
122 #define SLOT_STATUS ( pcie_cap_base + SLOTSTATUS )
123 #define ROOT_CTRL ( pcie_cap_base + ROOTCTRL )
124 #define ROOT_STATUS ( pcie_cap_base + ROOTSTATUS )
126 #define hp_register_read_word(pdev, reg , value) \
127 pci_read_config_word(pdev, reg, &value)
129 #define hp_register_read_dword(pdev, reg , value) \
130 pci_read_config_dword(pdev, reg, &value)
132 #define hp_register_write_word(pdev, reg , value) \
133 pci_write_config_word(pdev, reg, value)
135 #define hp_register_dwrite_word(pdev, reg , value) \
136 pci_write_config_dword(pdev, reg, value)
138 /* Field definitions in PCI Express Capabilities Register */
139 #define CAP_VER 0x000F
140 #define DEV_PORT_TYPE 0x00F0
141 #define SLOT_IMPL 0x0100
142 #define MSG_NUM 0x3E00
144 /* Device or Port Type */
145 #define NAT_ENDPT 0x00
146 #define LEG_ENDPT 0x01
147 #define ROOT_PORT 0x04
148 #define UP_STREAM 0x05
149 #define DN_STREAM 0x06
150 #define PCIE_PCI_BRDG 0x07
151 #define PCI_PCIE_BRDG 0x10
153 /* Field definitions in Device Capabilities Register */
154 #define DATTN_BUTTN_PRSN 0x1000
155 #define DATTN_LED_PRSN 0x2000
156 #define DPWR_LED_PRSN 0x4000
158 /* Field definitions in Link Capabilities Register */
159 #define MAX_LNK_SPEED 0x000F
160 #define MAX_LNK_WIDTH 0x03F0
162 /* Link Width Encoding */
171 /*Field definitions of Link Status Register */
172 #define LNK_SPEED 0x000F
173 #define NEG_LINK_WD 0x03F0
174 #define LNK_TRN_ERR 0x0400
175 #define LNK_TRN 0x0800
176 #define SLOT_CLK_CONF 0x1000
178 /* Field definitions in Slot Capabilities Register */
179 #define ATTN_BUTTN_PRSN 0x00000001
180 #define PWR_CTRL_PRSN 0x00000002
181 #define MRL_SENS_PRSN 0x00000004
182 #define ATTN_LED_PRSN 0x00000008
183 #define PWR_LED_PRSN 0x00000010
184 #define HP_SUPR_RM 0x00000020
185 #define HP_CAP 0x00000040
186 #define SLOT_PWR_VALUE 0x000003F8
187 #define SLOT_PWR_LIMIT 0x00000C00
188 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
190 /* Field definitions in Slot Control Register */
191 #define ATTN_BUTTN_ENABLE 0x0001
192 #define PWR_FAULT_DETECT_ENABLE 0x0002
193 #define MRL_DETECT_ENABLE 0x0004
194 #define PRSN_DETECT_ENABLE 0x0008
195 #define CMD_CMPL_INTR_ENABLE 0x0010
196 #define HP_INTR_ENABLE 0x0020
197 #define ATTN_LED_CTRL 0x00C0
198 #define PWR_LED_CTRL 0x0300
199 #define PWR_CTRL 0x0400
201 /* Attention indicator and Power indicator states */
203 #define LED_BLINK 0x10
206 /* Power Control Command */
208 #define POWER_OFF 0x0400
210 /* Field definitions in Slot Status Register */
211 #define ATTN_BUTTN_PRESSED 0x0001
212 #define PWR_FAULT_DETECTED 0x0002
213 #define MRL_SENS_CHANGED 0x0004
214 #define PRSN_DETECT_CHANGED 0x0008
215 #define CMD_COMPLETED 0x0010
216 #define MRL_STATE 0x0020
217 #define PRSN_STATE 0x0040
219 struct php_ctlr_state_s {
220 struct php_ctlr_state_s *pnext;
221 struct pci_dev *pci_dev;
223 unsigned long flags; /* spinlock's */
224 u32 slot_device_offset;
226 struct timer_list int_poll_timer; /* Added for poll event */
227 php_intr_callback_t attention_button_callback;
228 php_intr_callback_t switch_change_callback;
229 php_intr_callback_t presence_change_callback;
230 php_intr_callback_t power_fault_callback;
231 void *callback_instance_id;
232 struct ctrl_reg *creg; /* Ptr to controller register space */
235 static spinlock_t hpc_event_lock;
237 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
238 static struct php_ctlr_state_s *php_ctlr_list_head = 0; /* HPC state linked list */
239 static int ctlr_seq_num = 0; /* Controller sequence # */
240 static spinlock_t list_lock;
241 static void pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
243 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
245 /* This is the interrupt polling timeout function. */
246 static void int_poll_timeout(unsigned long lphp_ctlr)
248 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
253 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
257 /* Poll for interrupt events. regs == NULL => polling */
258 pcie_isr( 0, (void *)php_ctlr, NULL );
260 init_timer(&php_ctlr->int_poll_timer);
262 if (!pciehp_poll_time)
263 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
265 start_int_poll_timer(php_ctlr, pciehp_poll_time);
270 /* This function starts the interrupt polling timer. */
271 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
274 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
278 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
279 seconds = 2; /* Clamp to sane value */
281 php_ctlr->int_poll_timer.function = &int_poll_timeout;
282 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
283 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
284 add_timer(&php_ctlr->int_poll_timer);
289 static int pcie_write_cmd(struct slot *slot, u16 cmd)
291 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
297 dbg("%s : Enter\n", __FUNCTION__);
298 if (!slot->ctrl->hpc_ctlr_handle) {
299 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
303 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
305 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
308 dbg("%s : hp_register_read_word SLOT_STATUS %x\n", __FUNCTION__, slot_status);
310 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
311 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
312 the next command according to spec. Just print out the error message */
313 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
316 dbg("%s : Before hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd);
317 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, cmd | CMD_CMPL_INTR_ENABLE);
319 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
322 dbg("%s : hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd|CMD_CMPL_INTR_ENABLE);
323 dbg("%s : Exit\n", __FUNCTION__);
329 static int hpc_check_lnk_status(struct controller *ctrl)
331 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
337 if (!ctrl->hpc_ctlr_handle) {
338 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
342 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status);
345 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
349 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
350 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
351 !(lnk_status & NEG_LINK_WD)) {
352 err("%s : Link Training Error occurs \n", __FUNCTION__);
361 static int hpc_get_attention_status(struct slot *slot, u8 *status)
363 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
370 if (!slot->ctrl->hpc_ctlr_handle) {
371 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
375 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
378 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
382 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL, slot_ctrl);
384 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
385 //atten_led_state = (slot_ctrl & PWR_LED_CTRL) >> 8;
387 switch (atten_led_state) {
389 *status = 0xFF; /* Reserved */
392 *status = 1; /* On */
395 *status = 2; /* Blink */
398 *status = 0; /* Off */
409 static int hpc_get_power_status(struct slot * slot, u8 *status)
411 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
418 if (!slot->ctrl->hpc_ctlr_handle) {
419 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
423 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
426 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
429 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, slot_ctrl);
431 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
450 static int hpc_get_latch_status(struct slot *slot, u8 *status)
452 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
458 if (!slot->ctrl->hpc_ctlr_handle) {
459 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
463 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
466 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
470 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
476 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
478 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
485 if (!slot->ctrl->hpc_ctlr_handle) {
486 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
490 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
493 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
496 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
497 *status = (card_state == 1) ? 1 : 0;
504 static int hpc_query_power_fault(struct slot * slot)
506 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
514 if (!slot->ctrl->hpc_ctlr_handle) {
515 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
519 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
522 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
525 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
526 status = (pwr_fault != 1) ? 1 : 0;
529 /* Note: Logic 0 => fault */
533 static int hpc_set_attention_status(struct slot *slot, u8 value)
535 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
540 dbg("%s: \n", __FUNCTION__);
541 if (!slot->ctrl->hpc_ctlr_handle) {
542 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
546 if (slot->hp_slot >= php_ctlr->num_slots) {
547 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
550 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
553 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
556 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
559 case 0 : /* turn off */
560 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
561 //slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
563 case 1: /* turn on */
564 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
565 //slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
567 case 2: /* turn blink */
568 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
569 //slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
574 if (!pciehp_poll_mode)
575 slot_cmd = slot_cmd | HP_INTR_ENABLE;
577 pcie_write_cmd(slot, slot_cmd);
578 dbg("%s: SLOT_CTRL %x write cmd %x\n",
579 __FUNCTION__, SLOT_CTRL, slot_cmd);
585 static void hpc_set_green_led_on(struct slot *slot)
587 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
592 dbg("%s: \n", __FUNCTION__);
593 if (!slot->ctrl->hpc_ctlr_handle) {
594 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
598 if (slot->hp_slot >= php_ctlr->num_slots) {
599 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
603 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
606 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
609 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
610 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
611 //slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
613 if (!pciehp_poll_mode)
614 slot_cmd = slot_cmd | HP_INTR_ENABLE;
616 pcie_write_cmd(slot, slot_cmd);
618 dbg("%s: SLOT_CTRL %x write cmd %x\n",
619 __FUNCTION__, SLOT_CTRL, slot_cmd);
623 static void hpc_set_green_led_off(struct slot *slot)
625 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
630 dbg("%s: \n", __FUNCTION__);
631 if (!slot->ctrl->hpc_ctlr_handle) {
632 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
636 if (slot->hp_slot >= php_ctlr->num_slots) {
637 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
641 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
644 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
647 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
649 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
650 //slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00c0;
652 if (!pciehp_poll_mode)
653 slot_cmd = slot_cmd | HP_INTR_ENABLE;
654 pcie_write_cmd(slot, slot_cmd);
656 dbg("%s: SLOT_CTRL %x write cmd %x\n",
657 __FUNCTION__, SLOT_CTRL, slot_cmd);
661 static void hpc_set_green_led_blink(struct slot *slot)
663 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
668 dbg("%s: \n", __FUNCTION__);
669 if (!slot->ctrl->hpc_ctlr_handle) {
670 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
674 if (slot->hp_slot >= php_ctlr->num_slots) {
675 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
679 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
682 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
685 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
687 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
688 //slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
690 if (!pciehp_poll_mode)
691 slot_cmd = slot_cmd | HP_INTR_ENABLE;
692 pcie_write_cmd(slot, slot_cmd);
694 dbg("%s: SLOT_CTRL %x write cmd %x\n",
695 __FUNCTION__, SLOT_CTRL, slot_cmd);
699 int pcie_get_ctlr_slot_config(struct controller *ctrl,
700 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
701 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
702 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
703 int *updown, /* physical_slot_num increament: 1 or -1 */
706 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
712 if (!ctrl->hpc_ctlr_handle) {
713 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
717 *first_device_num = 0;
720 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP, slot_cap);
722 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
726 *physical_slot_num = slot_cap >> 19;
733 static void hpc_release_ctlr(struct controller *ctrl)
735 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
736 struct php_ctlr_state_s *p, *p_prev;
740 if (!ctrl->hpc_ctlr_handle) {
741 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
745 if (pciehp_poll_mode) {
746 del_timer(&php_ctlr->int_poll_timer);
749 free_irq(php_ctlr->irq, ctrl);
753 if (php_ctlr->pci_dev)
754 php_ctlr->pci_dev = 0;
756 spin_lock(&list_lock);
757 p = php_ctlr_list_head;
762 p_prev->pnext = p->pnext;
764 php_ctlr_list_head = p->pnext;
771 spin_unlock(&list_lock);
779 static int hpc_power_on_slot(struct slot * slot)
781 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
788 dbg("%s: \n", __FUNCTION__);
790 if (!slot->ctrl->hpc_ctlr_handle) {
791 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
794 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
795 if (slot->hp_slot >= php_ctlr->num_slots) {
796 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
800 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
803 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
806 dbg("%s: SLOT_CTRL %x, value read %xn", __FUNCTION__, SLOT_CTRL,
809 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
811 if (!pciehp_poll_mode)
812 slot_cmd = slot_cmd | HP_INTR_ENABLE;
814 retval = pcie_write_cmd(slot, slot_cmd);
817 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
820 dbg("%s: SLOT_CTRL %x write cmd %x\n",
821 __FUNCTION__, SLOT_CTRL, slot_cmd);
828 static int hpc_power_off_slot(struct slot * slot)
830 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
837 dbg("%s: \n", __FUNCTION__);
839 if (!slot->ctrl->hpc_ctlr_handle) {
840 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
844 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
846 if (slot->hp_slot >= php_ctlr->num_slots) {
847 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
850 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
853 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
856 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__, SLOT_CTRL,
859 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
861 if (!pciehp_poll_mode)
862 slot_cmd = slot_cmd | HP_INTR_ENABLE;
864 retval = pcie_write_cmd(slot, slot_cmd);
867 err("%s: Write command failed!\n", __FUNCTION__);
870 dbg("%s: SLOT_CTRL %x write cmd %x\n",
871 __FUNCTION__, SLOT_CTRL, slot_cmd);
878 static void pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
880 struct controller *ctrl = NULL;
881 struct php_ctlr_state_s *php_ctlr;
882 u8 schedule_flag = 0;
883 u16 slot_status, intr_detect, intr_loc;
885 int hp_slot = 0; /* only 1 slot per PCI Express port */
889 dbg("%s: dev_id == NULL\n", __FUNCTION__);
893 if (!pciehp_poll_mode) {
894 ctrl = (struct controller *)dev_id;
895 php_ctlr = ctrl->hpc_ctlr_handle;
897 php_ctlr = (struct php_ctlr_state_s *) dev_id;
898 ctrl = (struct controller *)php_ctlr->callback_instance_id;
902 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
906 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
910 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
912 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
916 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
917 PRSN_DETECT_CHANGED | CMD_COMPLETED );
919 intr_loc = slot_status & intr_detect;
921 /* Check to see if it was our interrupt */
925 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
927 /* Mask Hot-plug Interrupt Enable */
928 if (!pciehp_poll_mode) {
929 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
931 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
935 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
937 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
939 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
943 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
945 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
949 /* Clear command complete interrupt caused by this write */
951 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
953 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
958 if (intr_loc & CMD_COMPLETED) {
960 * Command Complete Interrupt Pending
962 dbg("%s: In Command Complete Interrupt Pending\n", __FUNCTION__);
963 wake_up_interruptible(&ctrl->queue);
965 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
966 schedule_flag += php_ctlr->switch_change_callback(
967 hp_slot, php_ctlr->callback_instance_id);
968 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
969 schedule_flag += php_ctlr->attention_button_callback(
970 hp_slot, php_ctlr->callback_instance_id);
971 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
972 schedule_flag += php_ctlr->presence_change_callback(
973 hp_slot , php_ctlr->callback_instance_id);
974 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
975 schedule_flag += php_ctlr->power_fault_callback(
976 hp_slot, php_ctlr->callback_instance_id);
978 /* Clear all events after serving them */
980 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
982 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
986 /* Unmask Hot-plug Interrupt Enable */
987 if (!pciehp_poll_mode) {
988 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
990 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
993 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
995 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
997 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1001 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
1003 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1007 /* Clear command complete interrupt caused by this write */
1009 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
1011 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1018 static int hpc_get_max_lnk_speed (struct slot *slot, enum pcie_link_speed *value)
1020 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1021 enum pcie_link_speed lnk_speed;
1027 if (!slot->ctrl->hpc_ctlr_handle) {
1028 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1032 if (slot->hp_slot >= php_ctlr->num_slots) {
1033 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1037 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP, lnk_cap);
1040 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1044 switch (lnk_cap & 0x000F) {
1046 lnk_speed = PCIE_2PT5GB;
1049 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1054 dbg("Max link speed = %d\n", lnk_speed);
1059 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1061 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1062 enum pcie_link_width lnk_wdth;
1068 if (!slot->ctrl->hpc_ctlr_handle) {
1069 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1073 if (slot->hp_slot >= php_ctlr->num_slots) {
1074 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1078 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP, lnk_cap);
1081 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1085 switch ((lnk_cap & 0x03F0) >> 4){
1087 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1090 lnk_wdth = PCIE_LNK_X1;
1093 lnk_wdth = PCIE_LNK_X2;
1096 lnk_wdth = PCIE_LNK_X4;
1099 lnk_wdth = PCIE_LNK_X8;
1102 lnk_wdth = PCIE_LNK_X12;
1105 lnk_wdth = PCIE_LNK_X16;
1108 lnk_wdth = PCIE_LNK_X32;
1111 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1116 dbg("Max link width = %d\n", lnk_wdth);
1121 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pcie_link_speed *value)
1123 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1124 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1130 if (!slot->ctrl->hpc_ctlr_handle) {
1131 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1135 if (slot->hp_slot >= php_ctlr->num_slots) {
1136 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1140 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status);
1143 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1147 switch (lnk_status & 0x0F) {
1149 lnk_speed = PCIE_2PT5GB;
1152 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1157 dbg("Current link speed = %d\n", lnk_speed);
1162 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1164 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1165 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1171 if (!slot->ctrl->hpc_ctlr_handle) {
1172 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1176 if (slot->hp_slot >= php_ctlr->num_slots) {
1177 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1181 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status);
1184 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1188 switch ((lnk_status & 0x03F0) >> 4){
1190 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1193 lnk_wdth = PCIE_LNK_X1;
1196 lnk_wdth = PCIE_LNK_X2;
1199 lnk_wdth = PCIE_LNK_X4;
1202 lnk_wdth = PCIE_LNK_X8;
1205 lnk_wdth = PCIE_LNK_X12;
1208 lnk_wdth = PCIE_LNK_X16;
1211 lnk_wdth = PCIE_LNK_X32;
1214 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1219 dbg("Current link width = %d\n", lnk_wdth);
1224 static struct hpc_ops pciehp_hpc_ops = {
1225 .power_on_slot = hpc_power_on_slot,
1226 .power_off_slot = hpc_power_off_slot,
1227 .set_attention_status = hpc_set_attention_status,
1228 .get_power_status = hpc_get_power_status,
1229 .get_attention_status = hpc_get_attention_status,
1230 .get_latch_status = hpc_get_latch_status,
1231 .get_adapter_status = hpc_get_adapter_status,
1233 .get_max_bus_speed = hpc_get_max_lnk_speed,
1234 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1235 .get_max_lnk_width = hpc_get_max_lnk_width,
1236 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1238 .query_power_fault = hpc_query_power_fault,
1239 .green_led_on = hpc_set_green_led_on,
1240 .green_led_off = hpc_set_green_led_off,
1241 .green_led_blink = hpc_set_green_led_blink,
1243 .release_ctlr = hpc_release_ctlr,
1244 .check_lnk_status = hpc_check_lnk_status,
1247 int pcie_init(struct controller * ctrl,
1248 struct pci_dev * pdev,
1249 php_intr_callback_t attention_button_callback,
1250 php_intr_callback_t switch_change_callback,
1251 php_intr_callback_t presence_change_callback,
1252 php_intr_callback_t power_fault_callback)
1254 struct php_ctlr_state_s *php_ctlr, *p;
1255 void *instance_id = ctrl;
1257 static int first = 1;
1262 int cap_base, saved_cap_base;
1263 u16 slot_status, slot_ctrl;
1267 spin_lock_init(&list_lock);
1268 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1270 if (!php_ctlr) { /* Allocate controller state data */
1271 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1275 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1277 php_ctlr->pci_dev = pdev; /* Save pci_dev in context */
1279 dbg("%s: pdev->vendor %x pdev->device %x\n", __FUNCTION__,
1280 pdev->vendor, pdev->device);
1282 saved_cap_base = pcie_cap_base;
1284 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1285 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1286 goto abort_free_ctlr;
1288 pcie_cap_base = cap_base;
1290 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1292 rc = hp_register_read_word(pdev, CAP_REG, cap_reg);
1294 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1295 goto abort_free_ctlr;
1297 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG, cap_reg);
1299 if (((cap_reg & SLOT_IMPL) == 0) || ((cap_reg & DEV_PORT_TYPE) != 0x0040)){
1300 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1301 goto abort_free_ctlr;
1304 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP, slot_cap);
1306 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1307 goto abort_free_ctlr;
1309 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP, slot_cap);
1311 if (!(slot_cap & HP_CAP)) {
1312 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1313 goto abort_free_ctlr;
1316 /* For debugging purpose */
1317 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
1319 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1320 goto abort_free_ctlr;
1322 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS, slot_status);
1324 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
1326 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1327 goto abort_free_ctlr;
1329 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL, slot_ctrl);
1332 spin_lock_init(&hpc_event_lock);
1336 dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number,
1337 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), pdev->irq);
1338 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1339 if (pci_resource_len(pdev, rc) > 0)
1340 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
1341 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc));
1343 dbg("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1344 pdev->subsystem_vendor, pdev->subsystem_device);
1346 init_MUTEX(&ctrl->crit_sect);
1347 /* Setup wait queue */
1348 init_waitqueue_head(&ctrl->queue);
1351 php_ctlr->irq = pdev->irq;
1352 dbg("HPC interrupt = %d\n", php_ctlr->irq);
1354 /* Save interrupt callback info */
1355 php_ctlr->attention_button_callback = attention_button_callback;
1356 php_ctlr->switch_change_callback = switch_change_callback;
1357 php_ctlr->presence_change_callback = presence_change_callback;
1358 php_ctlr->power_fault_callback = power_fault_callback;
1359 php_ctlr->callback_instance_id = instance_id;
1361 /* Return PCI Controller Info */
1362 php_ctlr->slot_device_offset = 0;
1363 php_ctlr->num_slots = 1;
1365 /* Mask Hot-plug Interrupt Enable */
1366 rc = hp_register_read_word(pdev, SLOT_CTRL, temp_word);
1368 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1369 goto abort_free_ctlr;
1371 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, temp_word);
1372 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1374 rc = hp_register_write_word(pdev, SLOT_CTRL, temp_word);
1376 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1377 goto abort_free_ctlr;
1379 dbg("%s : Mask HPIE hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, temp_word);
1380 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
1382 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1383 goto abort_free_ctlr;
1385 dbg("%s: Mask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__,
1386 SLOT_STATUS, slot_status);
1388 temp_word = 0x1F; /* Clear all events */
1389 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
1391 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1392 goto abort_free_ctlr;
1394 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, temp_word);
1396 if (pciehp_poll_mode) {/* Install interrupt polling code */
1397 /* Install and start the interrupt polling timer */
1398 init_timer(&php_ctlr->int_poll_timer);
1399 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1401 /* Installs the interrupt handler */
1402 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1403 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1405 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1406 goto abort_free_ctlr;
1410 rc = hp_register_read_word(pdev, SLOT_CTRL, temp_word);
1412 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1413 goto abort_free_ctlr;
1415 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, temp_word);
1417 intr_enable = ATTN_BUTTN_ENABLE | PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
1420 temp_word = (temp_word & ~intr_enable) | intr_enable;
1422 if (pciehp_poll_mode) {
1423 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1425 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1427 dbg("%s: temp_word %x\n", __FUNCTION__, temp_word);
1429 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1430 rc = hp_register_write_word(pdev, SLOT_CTRL, temp_word);
1432 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1433 goto abort_free_ctlr;
1435 dbg("%s : Unmask HPIE hp_register_write_word SLOT_CTRL with %x\n", __FUNCTION__, temp_word);
1437 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
1439 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1440 goto abort_free_ctlr;
1442 dbg("%s: Unmask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__,
1443 SLOT_STATUS, slot_status);
1445 temp_word = 0x1F; /* Clear all events */
1446 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
1448 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1449 goto abort_free_ctlr;
1451 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, temp_word);
1453 /* Add this HPC instance into the HPC list */
1454 spin_lock(&list_lock);
1455 if (php_ctlr_list_head == 0) {
1456 php_ctlr_list_head = php_ctlr;
1457 p = php_ctlr_list_head;
1460 p = php_ctlr_list_head;
1465 p->pnext = php_ctlr;
1467 spin_unlock(&list_lock);
1470 ctrl->hpc_ctlr_handle = php_ctlr;
1471 ctrl->hpc_ops = &pciehp_hpc_ops;
1476 /* We end up here for the many possible ways to fail this API. */
1478 pcie_cap_base = saved_cap_base;