drivers/ide/pci/aec62xx.c

   1 /*
   2  * linux/drivers/ide/pci/aec62xx.c              Version 0.11    March 27, 2002
   3  *
   4  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
   5  *
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/config.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/hdreg.h>
  14 #include <linux/ide.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/io.h>
  18
  19 #include "ide_modes.h"
  20 #include "aec62xx.h"
  21
  22 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
  23 #include <linux/stat.h>
  24 #include <linux/proc_fs.h>
  25
  26 static u8 aec62xx_proc = 0;
  27
  28 #define AEC_MAX_DEVS            5
  29
  30 static struct pci_dev *aec_devs[AEC_MAX_DEVS];
  31 static int n_aec_devs;
  32
  33 #undef DEBUG_AEC_REGS
  34
  35 static int aec62xx_get_info (char *buffer, char **addr, off_t offset, int count)
  36 {
  37         char *p = buffer;
  38         char *chipset_nums[] = {"error", "error", "error", "error",
  39                                 "error", "error", "850UF",   "860",
  40                                  "860R",   "865",  "865R", "error"  };
  41         int len;
  42         int i;
  43
  44         for (i = 0; i < n_aec_devs; i++) {
  45                 struct pci_dev *dev     = aec_devs[i];
  46                 unsigned long iobase = pci_resource_start(dev, 4);
  47                 u8 c0 = 0, c1 = 0, art  = 0;
  48 #ifdef DEBUG_AEC_REGS
  49                 u8 uart                 = 0;
  50 #endif /* DEBUG_AEC_REGS */
  51
  52                 c0 = inb(iobase + 0x02);
  53                 c1 = inb(iobase + 0x0a);
  54
  55                 p += sprintf(p, "\nController: %d\n", i);
  56                 p += sprintf(p, "Chipset: AEC%s\n", chipset_nums[dev->device]);
  57
  58                 p += sprintf(p, "--------------- Primary Channel "
  59                                 "---------------- Secondary Channel "
  60                                 "-------------\n");
  61                 (void) pci_read_config_byte(dev, 0x4a, &art);
  62                 p += sprintf(p, "                %sabled ",
  63                         (art&0x02)?" en":"dis");
  64                 p += sprintf(p, "                        %sabled\n",
  65                         (art&0x04)?" en":"dis");
  66                 p += sprintf(p, "--------------- drive0 --------- drive1 "
  67                                 "-------- drive0 ---------- drive1 ------\n");
  68                 p += sprintf(p, "DMA enabled:    %s              %s ",
  69                         (c0&0x20)?"yes":"no ",(c0&0x40)?"yes":"no ");
  70                 p += sprintf(p, "            %s               %s\n",
  71                         (c1&0x20)?"yes":"no ",(c1&0x40)?"yes":"no ");
  72
  73                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
  74                         (void) pci_read_config_byte(dev, 0x54, &art);
  75                         p += sprintf(p, "DMA Mode:       %s(%s)",
  76                                 (c0&0x20)?((art&0x03)?"UDMA":" DMA"):" PIO",
  77                                 (art&0x02)?"2":(art&0x01)?"1":"0");
  78                         p += sprintf(p, "          %s(%s)",
  79                                 (c0&0x40)?((art&0x0c)?"UDMA":" DMA"):" PIO",
  80                                 (art&0x08)?"2":(art&0x04)?"1":"0");
  81                         p += sprintf(p, "         %s(%s)",
  82                                 (c1&0x20)?((art&0x30)?"UDMA":" DMA"):" PIO",
  83                                 (art&0x20)?"2":(art&0x10)?"1":"0");
  84                         p += sprintf(p, "           %s(%s)\n",
  85                                 (c1&0x40)?((art&0xc0)?"UDMA":" DMA"):" PIO",
  86                                 (art&0x80)?"2":(art&0x40)?"1":"0");
  87 #ifdef DEBUG_AEC_REGS
  88                         (void) pci_read_config_byte(dev, 0x40, &art);
  89                         p += sprintf(p, "Active:         0x%02x", art);
  90                         (void) pci_read_config_byte(dev, 0x42, &art);
  91                         p += sprintf(p, "             0x%02x", art);
  92                         (void) pci_read_config_byte(dev, 0x44, &art);
  93                         p += sprintf(p, "            0x%02x", art);
  94                         (void) pci_read_config_byte(dev, 0x46, &art);
  95                         p += sprintf(p, "              0x%02x\n", art);
  96                         (void) pci_read_config_byte(dev, 0x41, &art);
  97                         p += sprintf(p, "Recovery:       0x%02x", art);
  98                         (void) pci_read_config_byte(dev, 0x43, &art);
  99                         p += sprintf(p, "             0x%02x", art);
 100                         (void) pci_read_config_byte(dev, 0x45, &art);
 101                         p += sprintf(p, "            0x%02x", art);
 102                         (void) pci_read_config_byte(dev, 0x47, &art);
 103                         p += sprintf(p, "              0x%02x\n", art);
 104 #endif /* DEBUG_AEC_REGS */
 105                 } else {
 106                         /*
 107                          * case PCI_DEVICE_ID_ARTOP_ATP860:
 108                          * case PCI_DEVICE_ID_ARTOP_ATP860R:
 109                          * case PCI_DEVICE_ID_ARTOP_ATP865:
 110                          * case PCI_DEVICE_ID_ARTOP_ATP865R:
 111                          */
 112                         (void) pci_read_config_byte(dev, 0x44, &art);
 113                         p += sprintf(p, "DMA Mode:       %s(%s)",
 114                                 (c0&0x20)?((art&0x07)?"UDMA":" DMA"):" PIO",
 115                                 ((art&0x07)==0x07)?"6":
 116                                 ((art&0x06)==0x06)?"5":
 117                                 ((art&0x05)==0x05)?"4":
 118                                 ((art&0x04)==0x04)?"3":
 119                                 ((art&0x03)==0x03)?"2":
 120                                 ((art&0x02)==0x02)?"1":
 121                                 ((art&0x01)==0x01)?"0":"?");
 122                         p += sprintf(p, "          %s(%s)",
 123                                 (c0&0x40)?((art&0x70)?"UDMA":" DMA"):" PIO",
 124                                 ((art&0x70)==0x70)?"6":
 125                                 ((art&0x60)==0x60)?"5":
 126                                 ((art&0x50)==0x50)?"4":
 127                                 ((art&0x40)==0x40)?"3":
 128                                 ((art&0x30)==0x30)?"2":
 129                                 ((art&0x20)==0x20)?"1":
 130                                 ((art&0x10)==0x10)?"0":"?");
 131                         (void) pci_read_config_byte(dev, 0x45, &art);
 132                         p += sprintf(p, "         %s(%s)",
 133                                 (c1&0x20)?((art&0x07)?"UDMA":" DMA"):" PIO",
 134                                 ((art&0x07)==0x07)?"6":
 135                                 ((art&0x06)==0x06)?"5":
 136                                 ((art&0x05)==0x05)?"4":
 137                                 ((art&0x04)==0x04)?"3":
 138                                 ((art&0x03)==0x03)?"2":
 139                                 ((art&0x02)==0x02)?"1":
 140                                 ((art&0x01)==0x01)?"0":"?");
 141                         p += sprintf(p, "           %s(%s)\n",
 142                                 (c1&0x40)?((art&0x70)?"UDMA":" DMA"):" PIO",
 143                                 ((art&0x70)==0x70)?"6":
 144                                 ((art&0x60)==0x60)?"5":
 145                                 ((art&0x50)==0x50)?"4":
 146                                 ((art&0x40)==0x40)?"3":
 147                                 ((art&0x30)==0x30)?"2":
 148                                 ((art&0x20)==0x20)?"1":
 149                                 ((art&0x10)==0x10)?"0":"?");
 150 #ifdef DEBUG_AEC_REGS
 151                         (void) pci_read_config_byte(dev, 0x40, &art);
 152                         p += sprintf(p, "Active:         0x%02x", HIGH_4(art));
 153                         (void) pci_read_config_byte(dev, 0x41, &art);
 154                         p += sprintf(p, "             0x%02x", HIGH_4(art));
 155                         (void) pci_read_config_byte(dev, 0x42, &art);
 156                         p += sprintf(p, "            0x%02x", HIGH_4(art));
 157                         (void) pci_read_config_byte(dev, 0x43, &art);
 158                         p += sprintf(p, "              0x%02x\n", HIGH_4(art));
 159                         (void) pci_read_config_byte(dev, 0x40, &art);
 160                         p += sprintf(p, "Recovery:       0x%02x", LOW_4(art));
 161                         (void) pci_read_config_byte(dev, 0x41, &art);
 162                         p += sprintf(p, "             0x%02x", LOW_4(art));
 163                         (void) pci_read_config_byte(dev, 0x42, &art);
 164                         p += sprintf(p, "            0x%02x", LOW_4(art));
 165                         (void) pci_read_config_byte(dev, 0x43, &art);
 166                         p += sprintf(p, "              0x%02x\n", LOW_4(art));
 167                         (void) pci_read_config_byte(dev, 0x49, &uart);
 168                         p += sprintf(p, "reg49h = 0x%02x ", uart);
 169                         (void) pci_read_config_byte(dev, 0x4a, &uart);
 170                         p += sprintf(p, "reg4ah = 0x%02x\n", uart);
 171 #endif /* DEBUG_AEC_REGS */
 172                 }
 173         }
 174         /* p - buffer must be less than 4k! */
 175         len = (p - buffer) - offset;
 176         *addr = buffer + offset;
 177
 178         return len > count ? count : len;
 179 }
 180 #endif  /* defined(DISPLAY_AEC62xx_TIMINGS) && defined(CONFIG_PROC_FS) */
 181
 182 /*
 183  * TO DO: active tuning and correction of cards without a bios.
 184  */
 185 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 186 {
 187         for ( ; chipset_table->xfer_speed ; chipset_table++)
 188                 if (chipset_table->xfer_speed == speed) {
 189                         return chipset_table->chipset_settings;
 190                 }
 191         return chipset_table->chipset_settings;
 192 }
 193
 194 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 195 {
 196         for ( ; chipset_table->xfer_speed ; chipset_table++)
 197                 if (chipset_table->xfer_speed == speed) {
 198                         return chipset_table->ultra_settings;
 199                 }
 200         return chipset_table->ultra_settings;
 201 }
 202
 203 static u8 aec62xx_ratemask (ide_drive_t *drive)
 204 {
 205         ide_hwif_t *hwif        = HWIF(drive);
 206         u8 mode;
 207
 208         switch(hwif->pci_dev->device) {
 209                 case PCI_DEVICE_ID_ARTOP_ATP865:
 210                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 211 #if 0
 212                         mode = (hwif->INB(hwif->dma_master) & 0x10) ? 4 : 3;
 213 #else
 214                         mode = (hwif->INB(((hwif->channel) ?
 215                                         hwif->mate->dma_status :
 216                                         hwif->dma_status)) & 0x10) ? 4 : 3;
 217 #endif
 218                         break;
 219                 case PCI_DEVICE_ID_ARTOP_ATP860:
 220                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 221                         mode = 2;
 222                         break;
 223                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
 224                 default:
 225                         return 1;
 226         }
 227
 228         if (!eighty_ninty_three(drive))
 229                 mode = min(mode, (u8)1);
 230         return mode;
 231 }
 232
 233 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 234 {
 235         ide_hwif_t *hwif        = HWIF(drive);
 236         struct pci_dev *dev     = hwif->pci_dev;
 237         u16 d_conf              = 0;
 238         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
 239         u8 ultra = 0, ultra_conf = 0;
 240         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
 241         unsigned long flags;
 242
 243         local_irq_save(flags);
 244         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 245         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
 246         SPLIT_BYTE(tmp0,tmp1,tmp2);
 247         MAKE_WORD(d_conf,tmp1,tmp2);
 248         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
 249
 250         tmp1 = 0x00;
 251         tmp2 = 0x00;
 252         pci_read_config_byte(dev, 0x54, &ultra);
 253         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
 254         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 255         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
 256         pci_write_config_byte(dev, 0x54, tmp2);
 257         local_irq_restore(flags);
 258         return(ide_config_drive_speed(drive, speed));
 259 }
 260
 261 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 262 {
 263         ide_hwif_t *hwif        = HWIF(drive);
 264         struct pci_dev *dev     = hwif->pci_dev;
 265         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
 266         u8 unit         = (drive->select.b.unit & 0x01);
 267         u8 tmp1 = 0, tmp2 = 0;
 268         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
 269         unsigned long flags;
 270
 271         local_irq_save(flags);
 272         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
 273         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
 274         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
 275
 276         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
 277         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
 278         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 279         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
 280         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
 281         local_irq_restore(flags);
 282         return(ide_config_drive_speed(drive, speed));
 283 }
 284
 285 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
 286 {
 287         switch (HWIF(drive)->pci_dev->device) {
 288                 case PCI_DEVICE_ID_ARTOP_ATP865:
 289                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 290                 case PCI_DEVICE_ID_ARTOP_ATP860:
 291                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 292                         return ((int) aec6260_tune_chipset(drive, speed));
 293                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
 294                         return ((int) aec6210_tune_chipset(drive, speed));
 295                 default:
 296                         return -1;
 297         }
 298 }
 299
 300 static int config_chipset_for_dma (ide_drive_t *drive)
 301 {
 302         u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));
 303
 304         if (!(speed))
 305                 return 0;
 306
 307         (void) aec62xx_tune_chipset(drive, speed);
 308         return ide_dma_enable(drive);
 309 }
 310
 311 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
 312 {
 313         u8 speed = 0;
 314         u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 315
 316         switch(pio) {
 317                 case 5:         speed = new_pio; break;
 318                 case 4:         speed = XFER_PIO_4; break;
 319                 case 3:         speed = XFER_PIO_3; break;
 320                 case 2:         speed = XFER_PIO_2; break;
 321                 case 1:         speed = XFER_PIO_1; break;
 322                 default:        speed = XFER_PIO_0; break;
 323         }
 324         (void) aec62xx_tune_chipset(drive, speed);
 325 }
 326
 327 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
 328 {
 329         ide_hwif_t *hwif        = HWIF(drive);
 330         struct hd_driveid *id   = drive->id;
 331
 332         if ((id->capability & 1) && drive->autodma) {
 333                 /* Consult the list of known "bad" drives */
 334                 if (hwif->ide_dma_bad_drive(drive))
 335                         goto fast_ata_pio;
 336                 if (id->field_valid & 4) {
 337                         if (id->dma_ultra & hwif->ultra_mask) {
 338                                 /* Force if Capable UltraDMA */
 339                                 int dma = config_chipset_for_dma(drive);
 340                                 if ((id->field_valid & 2) && !dma)
 341                                         goto try_dma_modes;
 342                         }
 343                 } else if (id->field_valid & 2) {
 344 try_dma_modes:
 345                         if ((id->dma_mword & hwif->mwdma_mask) ||
 346                             (id->dma_1word & hwif->swdma_mask)) {
 347                                 /* Force if Capable regular DMA modes */
 348                                 if (!config_chipset_for_dma(drive))
 349                                         goto no_dma_set;
 350                         }
 351                 } else if (hwif->ide_dma_good_drive(drive) &&
 352                            (id->eide_dma_time < 150)) {
 353                         /* Consult the list of known "good" drives */
 354                         if (!config_chipset_for_dma(drive))
 355                                 goto no_dma_set;
 356                 } else {
 357                         goto fast_ata_pio;
 358                 }
 359                 return hwif->ide_dma_on(drive);
 360         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 361 fast_ata_pio:
 362 no_dma_set:
 363                 aec62xx_tune_drive(drive, 5);
 364                 return hwif->ide_dma_off_quietly(drive);
 365         }
 366         /* IORDY not supported */
 367         return 0;
 368 }
 369
 370 static int aec62xx_irq_timeout (ide_drive_t *drive)
 371 {
 372         ide_hwif_t *hwif        = HWIF(drive);
 373         struct pci_dev *dev     = hwif->pci_dev;
 374
 375         switch(dev->device) {
 376                 case PCI_DEVICE_ID_ARTOP_ATP860:
 377                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 378                 case PCI_DEVICE_ID_ARTOP_ATP865:
 379                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 380                         printk(" AEC62XX time out ");
 381 #if 0
 382                         {
 383                                 int i = 0;
 384                                 u8 reg49h = 0;
 385                                 pci_read_config_byte(HWIF(drive)->pci_dev, 0x49, &reg49h);
 386                                 for (i=0;i<256;i++)
 387                                         pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h|0x10);
 388                                 pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h & ~0x10);
 389                         }
 390                         return 0;
 391 #endif
 392                 default:
 393                         break;
 394         }
 395 #if 0
 396         {
 397                 ide_hwif_t *hwif        = HWIF(drive);
 398                 struct pci_dev *dev     = hwif->pci_dev;
 399                 u8 tmp1 = 0, tmp2 = 0, mode6 = 0;
 400
 401                 pci_read_config_byte(dev, 0x44, &tmp1);
 402                 pci_read_config_byte(dev, 0x45, &tmp2);
 403                 printk(" AEC6280 r44=%x r45=%x ",tmp1,tmp2);
 404                 mode6 = HWIF(drive)->INB(((hwif->channel) ?
 405                                            hwif->mate->dma_status :
 406                                            hwif->dma_status));
 407                 printk(" AEC6280 133=%x ", (mode6 & 0x10));
 408         }
 409 #endif
 410         return 0;
 411 }
 412
 413 static unsigned int __init init_chipset_aec62xx (struct pci_dev *dev, const char *name)
 414 {
 415         int bus_speed = system_bus_clock();
 416
 417         if (dev->resource[PCI_ROM_RESOURCE].start) {
 418                 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 419                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
 420         }
 421
 422 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
 423         aec_devs[n_aec_devs++] = dev;
 424
 425         if (!aec62xx_proc) {
 426                 aec62xx_proc = 1;
 427                 ide_pci_register_host_proc(&aec62xx_procs[0]);
 428         }
 429 #endif /* DISPLAY_AEC62XX_TIMINGS && CONFIG_PROC_FS */
 430
 431         if (bus_speed <= 33)
 432                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
 433         else
 434                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
 435
 436         return dev->irq;
 437 }
 438
 439 static void __init init_hwif_aec62xx (ide_hwif_t *hwif)
 440 {
 441         hwif->autodma = 0;
 442         hwif->tuneproc = &aec62xx_tune_drive;
 443         hwif->speedproc = &aec62xx_tune_chipset;
 444
 445         if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 446                 hwif->serialized = hwif->channel;
 447                 hwif->no_dsc = 1;
 448         }
 449
 450         if (hwif->mate)
 451                 hwif->mate->serialized = hwif->serialized;
 452
 453         if (!hwif->dma_base) {
 454                 hwif->drives[0].autotune = 1;
 455                 hwif->drives[1].autotune = 1;
 456                 return;
 457         }
 458
 459         hwif->ultra_mask = 0x7f;
 460         hwif->mwdma_mask = 0x07;
 461         hwif->swdma_mask = 0x07;
 462
 463         hwif->ide_dma_check     = &aec62xx_config_drive_xfer_rate;
 464         hwif->ide_dma_lostirq   = &aec62xx_irq_timeout;
 465         hwif->ide_dma_timeout   = &aec62xx_irq_timeout;
 466         if (!noautodma)
 467                 hwif->autodma = 1;
 468         hwif->drives[0].autodma = hwif->autodma;
 469         hwif->drives[1].autodma = hwif->autodma;
 470 }
 471
 472 static void __init init_dma_aec62xx (ide_hwif_t *hwif, unsigned long dmabase)
 473 {
 474         struct pci_dev *dev     = hwif->pci_dev;
 475
 476         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 477                 u8 reg54h = 0;
 478                 unsigned long flags;
 479
 480                 spin_lock_irqsave(&ide_lock, flags);
 481                 pci_read_config_byte(dev, 0x54, &reg54h);
 482                 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
 483                 spin_unlock_irqrestore(&ide_lock, flags);
 484         } else {
 485                 u8 ata66        = 0;
 486                 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
 487                 if (!(hwif->udma_four))
 488                         hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
 489         }
 490
 491         ide_setup_dma(hwif, dmabase, 8);
 492 }
 493
 494 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
 495
 496 static void __init init_setup_aec62xx (struct pci_dev *dev, ide_pci_device_t *d)
 497 {
 498         ide_setup_pci_device(dev, d);
 499 }
 500
 501 static void __init init_setup_aec6x80 (struct pci_dev *dev, ide_pci_device_t *d)
 502 {
 503         unsigned long bar4reg = pci_resource_start(dev, 4);
 504
 505         if (inb(bar4reg+2) & 0x10) {
 506                 strcpy(d->name, "AEC6880");
 507                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
 508                         strcpy(d->name, "AEC6880R");
 509         } else {
 510                 strcpy(d->name, "AEC6280");
 511                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
 512                         strcpy(d->name, "AEC6280R");
 513         }
 514
 515         ide_setup_pci_device(dev, d);
 516 }
 517
 518 /**
 519  *      aec62xx_init_one        -       called when a AEC is found
 520  *      @dev: the aec62xx device
 521  *      @id: the matching pci id
 522  *
 523  *      Called when the PCI registration layer (or the IDE initialization)
 524  *      finds a device matching our IDE device tables.
 525  */
 526
 527 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 528 {
 529         ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
 530
 531         if (dev->device != d->device)
 532                 BUG();
 533         d->init_setup(dev, d);
 534         MOD_INC_USE_COUNT;
 535         return 0;
 536 }
 537
 538 static struct pci_device_id aec62xx_pci_tbl[] __devinitdata = {
 539         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 540         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
 541         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
 542         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
 543         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
 544         { 0, },
 545 };
 546
 547 static struct pci_driver driver = {
 548         .name           = "AEC62xx IDE",
 549         .id_table       = aec62xx_pci_tbl,
 550         .probe          = aec62xx_init_one,
 551 };
 552
 553 static int aec62xx_ide_init(void)
 554 {
 555         return ide_pci_register_driver(&driver);
 556 }
 557
 558 static void aec62xx_ide_exit(void)
 559 {
 560         ide_pci_unregister_driver(&driver);
 561 }
 562
 563 module_init(aec62xx_ide_init);
 564 module_exit(aec62xx_ide_exit);
 565
 566 MODULE_AUTHOR("Andre Hedrick");
 567 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
 568 MODULE_LICENSE("GPL");
 569
 570 EXPORT_NO_SYMBOLS;