drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *
   6  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   7  *  compiled into the kernel if you have more than one card installed.
   8  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
   9  *  safe chipset tuning, including this support is harmless
  10  *
  11  *  Promise Ultra66 cards with BIOS v1.11 this
  12  *  compiled into the kernel if you have more than one card installed.
  13  *
  14  *  Promise Ultra100 cards.
  15  *
  16  *  The latest chipset code will support the following ::
  17  *  Three Ultra33 controllers and 12 drives.
  18  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  19  *  The 8/4 ratio is a BIOS code limit by promise.
  20  *
  21  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  22  *
  23  */
  24
  25 /*
  26  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  27  *  Author: Frank Tiernan (frankt@promise.com)
  28  *  Released under terms of General Public License
  29  */
  30
  31 #include <linux/config.h>
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/timer.h>
  37 #include <linux/mm.h>
  38 #include <linux/ioport.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/ide.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48
  49 #include "ide_modes.h"
  50 #include "pdc202xx_old.h"
  51
  52 #define PDC202_DEBUG_CABLE      0
  53
  54 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
  55 #include <linux/stat.h>
  56 #include <linux/proc_fs.h>
  57
  58 static u8 pdc202xx_proc = 0;
  59 #define PDC202_MAX_DEVS         5
  60 static struct pci_dev *pdc202_devs[PDC202_MAX_DEVS];
  61 static int n_pdc202_devs;
  62
  63 static char * pdc202xx_info (char *buf, struct pci_dev *dev)
  64 {
  65         char *p = buf;
  66
  67         unsigned long bibma  = pci_resource_start(dev, 4);
  68         u32 reg60h = 0, reg64h = 0, reg68h = 0, reg6ch = 0;
  69         u16 reg50h = 0, pmask = (1<<10), smask = (1<<11);
  70         u8 hi = 0, lo = 0;
  71
  72         /*
  73          * at that point bibma+0x2 et bibma+0xa are byte registers
  74          * to investigate:
  75          */
  76         u8 c0   = inb_p((u16)bibma + 0x02);
  77         u8 c1   = inb_p((u16)bibma + 0x0a);
  78
  79         u8 sc11 = inb_p((u16)bibma + 0x11);
  80         u8 sc1a = inb_p((u16)bibma + 0x1a);
  81         u8 sc1b = inb_p((u16)bibma + 0x1b);
  82         u8 sc1c = inb_p((u16)bibma + 0x1c);
  83         u8 sc1d = inb_p((u16)bibma + 0x1d);
  84         u8 sc1e = inb_p((u16)bibma + 0x1e);
  85         u8 sc1f = inb_p((u16)bibma + 0x1f);
  86
  87         pci_read_config_word(dev, 0x50, &reg50h);
  88         pci_read_config_dword(dev, 0x60, &reg60h);
  89         pci_read_config_dword(dev, 0x64, &reg64h);
  90         pci_read_config_dword(dev, 0x68, &reg68h);
  91         pci_read_config_dword(dev, 0x6c, &reg6ch);
  92
  93         p += sprintf(p, "\n                                ");
  94         switch(dev->device) {
  95                 case PCI_DEVICE_ID_PROMISE_20267:
  96                         p += sprintf(p, "Ultra100"); break;
  97                 case PCI_DEVICE_ID_PROMISE_20265:
  98                         p += sprintf(p, "Ultra100 on M/B"); break;
  99                 case PCI_DEVICE_ID_PROMISE_20263:
 100                         p += sprintf(p, "FastTrak 66"); break;
 101                 case PCI_DEVICE_ID_PROMISE_20262:
 102                         p += sprintf(p, "Ultra66"); break;
 103                 case PCI_DEVICE_ID_PROMISE_20246:
 104                         p += sprintf(p, "Ultra33");
 105                         reg50h |= 0x0c00;
 106                         break;
 107                 default:
 108                         p += sprintf(p, "Ultra Series"); break;
 109         }
 110         p += sprintf(p, " Chipset.\n");
 111
 112         p += sprintf(p, "------------------------------- General Status "
 113                         "---------------------------------\n");
 114         p += sprintf(p, "Burst Mode                           : %sabled\n",
 115                 (sc1f & 0x01) ? "en" : "dis");
 116         p += sprintf(p, "Host Mode                            : %s\n",
 117                 (sc1f & 0x08) ? "Tri-Stated" : "Normal");
 118         p += sprintf(p, "Bus Clocking                         : %s\n",
 119                 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
 120                 ((sc1f & 0x80) == 0x80) ? "66 External" :
 121                 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
 122         p += sprintf(p, "IO pad select                        : %s mA\n",
 123                 ((sc1c & 0x03) == 0x03) ? "10" :
 124                 ((sc1c & 0x02) == 0x02) ? "8" :
 125                 ((sc1c & 0x01) == 0x01) ? "6" :
 126                 ((sc1c & 0x00) == 0x00) ? "4" : "??");
 127         SPLIT_BYTE(sc1e, hi, lo);
 128         p += sprintf(p, "Status Polling Period                : %d\n", hi);
 129         p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
 130         p += sprintf(p, "--------------- Primary Channel "
 131                         "---------------- Secondary Channel "
 132                         "-------------\n");
 133         p += sprintf(p, "                %s                         %s\n",
 134                 (c0&0x80)?"disabled":"enabled ",
 135                 (c1&0x80)?"disabled":"enabled ");
 136         p += sprintf(p, "66 Clocking     %s                         %s\n",
 137                 (sc11&0x02)?"enabled ":"disabled",
 138                 (sc11&0x08)?"enabled ":"disabled");
 139         p += sprintf(p, "           Mode %s                      Mode %s\n",
 140                 (sc1a & 0x01) ? "MASTER" : "PCI   ",
 141                 (sc1b & 0x01) ? "MASTER" : "PCI   ");
 142         p += sprintf(p, "                %s                     %s\n",
 143                 (sc1d & 0x08) ? "Error       " :
 144                 ((sc1d & 0x05) == 0x05) ? "Not My INTR " :
 145                 (sc1d & 0x04) ? "Interrupting" :
 146                 (sc1d & 0x02) ? "FIFO Full   " :
 147                 (sc1d & 0x01) ? "FIFO Empty  " : "????????????",
 148                 (sc1d & 0x80) ? "Error       " :
 149                 ((sc1d & 0x50) == 0x50) ? "Not My INTR " :
 150                 (sc1d & 0x40) ? "Interrupting" :
 151                 (sc1d & 0x20) ? "FIFO Full   " :
 152                 (sc1d & 0x10) ? "FIFO Empty  " : "????????????");
 153         p += sprintf(p, "--------------- drive0 --------- drive1 "
 154                         "-------- drive0 ---------- drive1 ------\n");
 155         p += sprintf(p, "DMA enabled:    %s              %s "
 156                         "            %s               %s\n",
 157                 (c0&0x20)?"yes":"no ", (c0&0x40)?"yes":"no ",
 158                 (c1&0x20)?"yes":"no ", (c1&0x40)?"yes":"no ");
 159         p += sprintf(p, "DMA Mode:       %s           %s "
 160                         "         %s            %s\n",
 161                 pdc202xx_ultra_verbose(reg60h, (reg50h & pmask)),
 162                 pdc202xx_ultra_verbose(reg64h, (reg50h & pmask)),
 163                 pdc202xx_ultra_verbose(reg68h, (reg50h & smask)),
 164                 pdc202xx_ultra_verbose(reg6ch, (reg50h & smask)));
 165         p += sprintf(p, "PIO Mode:       %s            %s "
 166                         "          %s            %s\n",
 167                 pdc202xx_pio_verbose(reg60h),
 168                 pdc202xx_pio_verbose(reg64h),
 169                 pdc202xx_pio_verbose(reg68h),
 170                 pdc202xx_pio_verbose(reg6ch));
 171         return (char *)p;
 172 }
 173
 174 static int pdc202xx_get_info (char *buffer, char **addr, off_t offset, int count)
 175 {
 176         char *p = buffer;
 177         int i, len;
 178
 179         for (i = 0; i < n_pdc202_devs; i++) {
 180                 struct pci_dev *dev     = pdc202_devs[i];
 181                 p = pdc202xx_info(buffer, dev);
 182         }
 183         /* p - buffer must be less than 4k! */
 184         len = (p - buffer) - offset;
 185         *addr = buffer + offset;
 186
 187         return len > count ? count : len;
 188 }
 189 #endif  /* defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS) */
 190
 191
 192 static u8 pdc202xx_ratemask (ide_drive_t *drive)
 193 {
 194         u8 mode;
 195
 196         switch(HWIF(drive)->pci_dev->device) {
 197                 case PCI_DEVICE_ID_PROMISE_20267:
 198                 case PCI_DEVICE_ID_PROMISE_20265:
 199                         mode = 3;
 200                         break;
 201                 case PCI_DEVICE_ID_PROMISE_20263:
 202                 case PCI_DEVICE_ID_PROMISE_20262:
 203                         mode = 2;
 204                         break;
 205                 case PCI_DEVICE_ID_PROMISE_20246:
 206                         return 1;
 207                 default:
 208                         return 0;
 209         }
 210         if (!eighty_ninty_three(drive))
 211                 mode = min(mode, (u8)1);
 212         return mode;
 213 }
 214
 215 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 216 {
 217         struct hd_driveid *id = drive->id;
 218
 219         if (pdc_quirk_drives == list) {
 220                 while (*list) {
 221                         if (strstr(id->model, *list++)) {
 222                                 return 2;
 223                         }
 224                 }
 225         } else {
 226                 while (*list) {
 227                         if (!strcmp(*list++,id->model)) {
 228                                 return 1;
 229                         }
 230                 }
 231         }
 232         return 0;
 233 }
 234
 235 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 236 {
 237         ide_hwif_t *hwif        = HWIF(drive);
 238         struct pci_dev *dev     = hwif->pci_dev;
 239         u8 drive_pci            = 0x60 + (drive->dn << 2);
 240         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 241
 242         u32                     drive_conf;
 243         u8                      AP, BP, CP, DP;
 244         u8                      TA = 0, TB = 0, TC = 0;
 245
 246         if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
 247                 return -1;
 248
 249         pci_read_config_dword(dev, drive_pci, &drive_conf);
 250         pci_read_config_byte(dev, (drive_pci), &AP);
 251         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 252         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 253         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 254
 255         if (speed < XFER_SW_DMA_0) {
 256                 if ((AP & 0x0F) || (BP & 0x07)) {
 257                         /* clear PIO modes of lower 8421 bits of A Register */
 258                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 259                         pci_read_config_byte(dev, (drive_pci), &AP);
 260
 261                         /* clear PIO modes of lower 421 bits of B Register */
 262                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 263                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 264
 265                         pci_read_config_byte(dev, (drive_pci), &AP);
 266                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 267                 }
 268         } else {
 269                 if ((BP & 0xF0) && (CP & 0x0F)) {
 270                         /* clear DMA modes of upper 842 bits of B Register */
 271                         /* clear PIO forced mode upper 1 bit of B Register */
 272                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 273                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 274
 275                         /* clear DMA modes of lower 8421 bits of C Register */
 276                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 277                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 278                 }
 279         }
 280
 281         pci_read_config_byte(dev, (drive_pci), &AP);
 282         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 283         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 284
 285         switch(speed) {
 286                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 287                 case XFER_UDMA_5:
 288                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 289                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 290                 case XFER_UDMA_3:
 291                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 292                 case XFER_UDMA_0:
 293                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 294                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 295                 case XFER_MW_DMA_0:
 296                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 297                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 298                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 299                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 300                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 301                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 302                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 303                 case XFER_PIO_0:
 304                 default:                TA = 0x09; TB = 0x13; break;
 305         }
 306
 307         if (speed < XFER_SW_DMA_0) {
 308                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 309                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 310         } else {
 311                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 312                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 313         }
 314
 315 #if PDC202XX_DECODE_REGISTER_INFO
 316         pci_read_config_byte(dev, (drive_pci), &AP);
 317         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 318         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 319         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 320
 321         decode_registers(REG_A, AP);
 322         decode_registers(REG_B, BP);
 323         decode_registers(REG_C, CP);
 324         decode_registers(REG_D, DP);
 325 #endif /* PDC202XX_DECODE_REGISTER_INFO */
 326 #if PDC202XX_DEBUG_DRIVE_INFO
 327         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 328                 drive->name, ide_xfer_verbose(speed),
 329                 drive->dn, drive_conf);
 330                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 331         printk("0x%08x\n", drive_conf);
 332 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 333
 334         return (ide_config_drive_speed(drive, speed));
 335 }
 336
 337
 338 /*   0    1    2    3    4    5    6   7   8
 339  * 960, 480, 390, 300, 240, 180, 120, 90, 60
 340  *           180, 150, 120,  90,  60
 341  * DMA_Speed
 342  * 180, 120,  90,  90,  90,  60,  30
 343  *  11,   5,   4,   3,   2,   1,   0
 344  */
 345 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 346 {
 347         u8 speed = 0;
 348
 349         if (pio == 5) pio = 4;
 350         speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
 351
 352         pdc202xx_tune_chipset(drive, speed);
 353 }
 354
 355 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 356 {
 357         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 358         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 359         return ((u8)(CIS & mask));
 360 }
 361
 362 static int config_chipset_for_dma (ide_drive_t *drive)
 363 {
 364         struct hd_driveid *id   = drive->id;
 365         ide_hwif_t *hwif        = HWIF(drive);
 366         struct pci_dev *dev     = hwif->pci_dev;
 367         u32 drive_conf          = 0;
 368         u8 mask                 = hwif->channel ? 0x08 : 0x02;
 369         u8 drive_pci            = 0x60 + (drive->dn << 2);
 370         u8 test1 = 0, test2 = 0, speed = -1;
 371         u8 AP = 0, CLKSPD = 0, cable = 0;
 372
 373         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 374                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 375
 376         switch(dev->device) {
 377                 case PCI_DEVICE_ID_PROMISE_20267:
 378                 case PCI_DEVICE_ID_PROMISE_20265:
 379                 case PCI_DEVICE_ID_PROMISE_20263:
 380                 case PCI_DEVICE_ID_PROMISE_20262:
 381                         cable = pdc202xx_old_cable_detect(hwif);
 382 #if PDC202_DEBUG_CABLE
 383                         printk(KERN_DEBUG "%s: %s-pin cable, %s-pin cable, %d\n",
 384                                 hwif->name, hwif->udma_four ? "80" : "40",
 385                                 cable ? "40" : "80", cable);
 386 #endif /* PDC202_DEBUG_CABLE */
 387                         break;
 388                 case PCI_DEVICE_ID_PROMISE_20246:
 389                         ultra_66 = 0;
 390                         break;
 391                 default:
 392                         BUG();
 393         }
 394
 395         CLKSPD = hwif->INB(hwif->dma_master + 0x11);
 396
 397         /*
 398          * Set the control register to use the 66Mhz system
 399          * clock for UDMA 3/4 mode operation. If one drive on
 400          * a channel is U66 capable but the other isn't we
 401          * fall back to U33 mode. The BIOS INT 13 hooks turn
 402          * the clock on then off for each read/write issued. I don't
 403          * do that here because it would require modifying the
 404          * kernel, separating the fop routines from the kernel or
 405          * somehow hooking the fops calls. It may also be possible to
 406          * leave the 66Mhz clock on and readjust the timing
 407          * parameters.
 408          */
 409
 410         if ((ultra_66) && (cable)) {
 411 #ifdef DEBUG
 412                 printk(KERN_DEBUG "ULTRA 66/100/133: %s channel of Ultra 66/100/133 "
 413                         "requires an 80-pin cable for Ultra66 operation.\n",
 414                         hwif->channel ? "Secondary" : "Primary");
 415                 printk(KERN_DEBUG "         Switching to Ultra33 mode.\n");
 416 #endif /* DEBUG */
 417                 /* Primary   : zero out second bit */
 418                 /* Secondary : zero out fourth bit */
 419                 hwif->OUTB(CLKSPD & ~mask, (hwif->dma_master + 0x11));
 420                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 421                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 422         } else {
 423                 if (ultra_66) {
 424                         /*
 425                          * check to make sure drive on same channel
 426                          * is u66 capable. Ignore empty slots.
 427                          */
 428                         if (hwif->drives[!(drive->dn%2)].present) {
 429                                 if (hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0078) {
 430                                         hwif->OUTB(CLKSPD | mask, (hwif->dma_master + 0x11));
 431                                 } else {
 432                                         hwif->OUTB(CLKSPD & ~mask, (hwif->dma_master + 0x11));
 433                                 }
 434                         } else { /* udma4 drive by itself */
 435                                 hwif->OUTB(CLKSPD | mask, (hwif->dma_master + 0x11));
 436                         }
 437                 }
 438         }
 439
 440         drive_pci = 0x60 + (drive->dn << 2);
 441         pci_read_config_dword(dev, drive_pci, &drive_conf);
 442         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 443                 goto chipset_is_set;
 444
 445         pci_read_config_byte(dev, drive_pci, &test1);
 446         if (!(test1 & SYNC_ERRDY_EN)) {
 447                 if (drive->select.b.unit & 0x01) {
 448                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 449                         if ((test2 & SYNC_ERRDY_EN) &&
 450                             !(test1 & SYNC_ERRDY_EN)) {
 451                                 pci_write_config_byte(dev, drive_pci,
 452                                         test1|SYNC_ERRDY_EN);
 453                         }
 454                 } else {
 455                         pci_write_config_byte(dev, drive_pci,
 456                                 test1|SYNC_ERRDY_EN);
 457                 }
 458         }
 459
 460 chipset_is_set:
 461
 462         if (drive->media == ide_disk) {
 463                 pci_read_config_byte(dev, (drive_pci), &AP);
 464                 if (id->capability & 4) /* IORDY_EN */
 465                         pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 466                 pci_read_config_byte(dev, (drive_pci), &AP);
 467                 if (drive->media == ide_disk)   /* PREFETCH_EN */
 468                         pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 469         }
 470
 471         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 472
 473         if (!(speed)) {
 474                 /* restore original pci-config space */
 475                 pci_write_config_dword(dev, drive_pci, drive_conf);
 476                 hwif->tuneproc(drive, 5);
 477                 return 0;
 478         }
 479
 480         (void) hwif->speedproc(drive, speed);
 481         return ide_dma_enable(drive);
 482 }
 483
 484 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 485 {
 486         ide_hwif_t *hwif        = HWIF(drive);
 487         struct hd_driveid *id   = drive->id;
 488
 489         drive->init_speed = 0;
 490
 491         if ((id->capability & 1) && drive->autodma) {
 492                 /* Consult the list of known "bad" drives */
 493                 if (hwif->ide_dma_bad_drive(drive))
 494                         goto fast_ata_pio;
 495                 if (id->field_valid & 4) {
 496                         if (id->dma_ultra & hwif->ultra_mask) {
 497                                 /* Force if Capable UltraDMA */
 498                                 int dma = config_chipset_for_dma(drive);
 499                                 if ((id->field_valid & 2) && !dma)
 500                                         goto try_dma_modes;
 501                         }
 502                 } else if (id->field_valid & 2) {
 503 try_dma_modes:
 504                         if ((id->dma_mword & hwif->mwdma_mask) ||
 505                             (id->dma_1word & hwif->swdma_mask)) {
 506                                 /* Force if Capable regular DMA modes */
 507                                 if (!config_chipset_for_dma(drive))
 508                                         goto no_dma_set;
 509                         }
 510                 } else if (hwif->ide_dma_good_drive(drive) &&
 511                             (id->eide_dma_time < 150)) {
 512                                 goto no_dma_set;
 513                         /* Consult the list of known "good" drives */
 514                         if (!config_chipset_for_dma(drive))
 515                                 goto no_dma_set;
 516                 } else {
 517                         goto fast_ata_pio;
 518                 }
 519                 return hwif->ide_dma_on(drive);
 520         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 521 fast_ata_pio:
 522 no_dma_set:
 523                 hwif->tuneproc(drive, 5);
 524                 return hwif->ide_dma_off_quietly(drive);
 525         }
 526         /* IORDY not supported */
 527         return 0;
 528 }
 529
 530 static int pdc202xx_quirkproc (ide_drive_t *drive)
 531 {
 532         return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
 533 }
 534
 535 static int pdc202xx_old_ide_dma_begin(ide_drive_t *drive)
 536 {
 537         if (drive->addressing == 1) {
 538                 struct request *rq      = HWGROUP(drive)->rq;
 539                 ide_hwif_t *hwif        = HWIF(drive);
 540 //              struct pci_dev *dev     = hwif->pci_dev;
 541 //              unsgned long high_16    = pci_resource_start(dev, 4);
 542                 unsigned long high_16   = hwif->dma_master;
 543                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 544                 u32 word_count  = 0;
 545                 u8 clock = hwif->INB(high_16 + 0x11);
 546
 547                 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
 548                 word_count = (rq->nr_sectors << 8);
 549                 word_count = (rq_data_dir(rq) == READ) ?
 550                                         word_count | 0x05000000 :
 551                                         word_count | 0x06000000;
 552                 hwif->OUTL(word_count, atapi_reg);
 553         }
 554         return __ide_dma_begin(drive);
 555 }
 556
 557 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 558 {
 559         if (drive->addressing == 1) {
 560                 ide_hwif_t *hwif        = HWIF(drive);
 561 //              unsigned long high_16   = pci_resource_start(hwif->pci_dev, 4);
 562                 unsigned long high_16   = hwif->dma_master;
 563                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 564                 u8 clock                = 0;
 565
 566                 hwif->OUTL(0, atapi_reg); /* zero out extra */
 567                 clock = hwif->INB(high_16 + 0x11);
 568                 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
 569         }
 570         return __ide_dma_end(drive);
 571 }
 572
 573 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 574 {
 575         ide_hwif_t *hwif        = HWIF(drive);
 576 //      struct pci_dev *dev     = hwif->pci_dev;
 577 //      unsigned long high_16   = pci_resource_start(dev, 4);
 578         unsigned long high_16   = hwif->dma_master;
 579         u8 dma_stat             = hwif->INB(hwif->dma_status);
 580         u8 sc1d                 = hwif->INB((high_16 + 0x001d));
 581
 582         if (hwif->channel) {
 583                 if ((sc1d & 0x50) == 0x50)
 584                         goto somebody_else;
 585                 else if ((sc1d & 0x40) == 0x40)
 586                         return (dma_stat & 4) == 4;
 587         } else {
 588                 if ((sc1d & 0x05) == 0x05)
 589                         goto somebody_else;
 590                 else if ((sc1d & 0x04) == 0x04)
 591                         return (dma_stat & 4) == 4;
 592         }
 593 somebody_else:
 594         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 595 }
 596
 597 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 598 {
 599         if (HWIF(drive)->resetproc != NULL)
 600                 HWIF(drive)->resetproc(drive);
 601         return __ide_dma_lostirq(drive);
 602 }
 603
 604 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 605 {
 606         if (HWIF(drive)->resetproc != NULL)
 607                 HWIF(drive)->resetproc(drive);
 608         return __ide_dma_timeout(drive);
 609 }
 610
 611 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 612 {
 613 #ifdef CONFIG_BLK_DEV_IDEDMA
 614 //      unsigned long high_16   = hwif->dma_base - (8*(hwif->channel));
 615         unsigned long high_16   = hwif->dma_master;
 616 #else /* !CONFIG_BLK_DEV_IDEDMA */
 617         unsigned long high_16   = pci_resource_start(hwif->pci_dev, 4);
 618 #endif /* CONFIG_BLK_DEV_IDEDMA */
 619         u8 udma_speed_flag      = hwif->INB(high_16|0x001f);
 620
 621         hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
 622         mdelay(100);
 623         hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
 624         mdelay(2000);   /* 2 seconds ?! */
 625
 626         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 627                 hwif->channel ? "Secondary" : "Primary");
 628 }
 629
 630 void pdc202xx_reset (ide_drive_t *drive)
 631 {
 632         ide_hwif_t *hwif        = HWIF(drive);
 633         ide_hwif_t *mate        = hwif->mate;
 634
 635         pdc202xx_reset_host(hwif);
 636         pdc202xx_reset_host(mate);
 637         hwif->tuneproc(drive, 5);
 638 }
 639
 640 /*
 641  * Since SUN Cobalt is attempting to do this operation, I should disclose
 642  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 643  * HOTSWAP ATA Infrastructure.
 644  */
 645 static int pdc202xx_tristate (ide_drive_t * drive, int state)
 646 {
 647         ide_hwif_t *hwif        = HWIF(drive);
 648 //      unsigned long high_16   = hwif->dma_base - (8*(hwif->channel));
 649         unsigned long high_16   = hwif->dma_master;
 650         u8 sc1f                 = hwif->INB(high_16|0x001f);
 651
 652         if (!hwif)
 653                 return -EINVAL;
 654
 655 //      hwif->bus_state = state;
 656
 657         if (state) {
 658                 hwif->OUTB(sc1f | 0x08, (high_16|0x001f));
 659         } else {
 660                 hwif->OUTB(sc1f & ~0x08, (high_16|0x001f));
 661         }
 662         return 0;
 663 }
 664
 665 static unsigned int __init init_chipset_pdc202xx (struct pci_dev *dev, const char *name)
 666 {
 667         if (dev->resource[PCI_ROM_RESOURCE].start) {
 668                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 669                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 670                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
 671                         name, dev->resource[PCI_ROM_RESOURCE].start);
 672         }
 673
 674 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
 675         pdc202_devs[n_pdc202_devs++] = dev;
 676
 677         if (!pdc202xx_proc) {
 678                 pdc202xx_proc = 1;
 679                 ide_pci_register_host_proc(&pdc202xx_procs[0]);
 680         }
 681 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
 682
 683         /*
 684          * software reset -  this is required because the bios
 685          * will set UDMA timing on if the hdd supports it. The
 686          * user may want to turn udma off. A bug in the pdc20262
 687          * is that it cannot handle a downgrade in timing from
 688          * UDMA to DMA. Disk accesses after issuing a set
 689          * feature command will result in errors. A software
 690          * reset leaves the timing registers intact,
 691          * but resets the drives.
 692          */
 693         return dev->irq;
 694 }
 695
 696 static void __init init_hwif_pdc202xx (ide_hwif_t *hwif)
 697 {
 698         hwif->autodma = 0;
 699         hwif->tuneproc  = &config_chipset_for_pio;
 700         hwif->quirkproc = &pdc202xx_quirkproc;
 701
 702         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 703                 hwif->busproc   = &pdc202xx_tristate;
 704                 hwif->resetproc = &pdc202xx_reset;
 705         }
 706
 707         hwif->speedproc = &pdc202xx_tune_chipset;
 708
 709         if (!hwif->dma_base) {
 710                 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 711                 return;
 712         }
 713
 714         hwif->ultra_mask = 0x3f;
 715         hwif->mwdma_mask = 0x07;
 716         hwif->swdma_mask = 0x07;
 717
 718         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 719         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 720         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 721
 722         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 723                 if (!(hwif->udma_four))
 724                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 725                 hwif->ide_dma_begin = &pdc202xx_old_ide_dma_begin;
 726                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 727         }
 728         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 729
 730         if (!noautodma)
 731                 hwif->autodma = 1;
 732         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 733 #if PDC202_DEBUG_CABLE
 734         printk(KERN_DEBUG "%s: %s-pin cable\n",
 735                 hwif->name, hwif->udma_four ? "80" : "40");
 736 #endif /* PDC202_DEBUG_CABLE */
 737 }
 738
 739 static void __init init_dma_pdc202xx (ide_hwif_t *hwif, unsigned long dmabase)
 740 {
 741         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 742
 743         if (hwif->channel) {
 744                 ide_setup_dma(hwif, dmabase, 8);
 745                 return;
 746         }
 747
 748         udma_speed_flag = hwif->INB((dmabase|0x1f));
 749         primary_mode    = hwif->INB((dmabase|0x1a));
 750         secondary_mode  = hwif->INB((dmabase|0x1b));
 751         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 752                 "Primary %s Mode " \
 753                 "Secondary %s Mode.\n", hwif->cds->name,
 754                 (udma_speed_flag & 1) ? "EN" : "DIS",
 755                 (primary_mode & 1) ? "MASTER" : "PCI",
 756                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 757
 758 #ifdef CONFIG_PDC202XX_BURST
 759         if (!(udma_speed_flag & 1)) {
 760                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 761                         hwif->cds->name, udma_speed_flag,
 762                         (udma_speed_flag|1));
 763                 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
 764                 printk("%sACTIVE\n",
 765                         (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
 766         }
 767 #endif /* CONFIG_PDC202XX_BURST */
 768 #ifdef CONFIG_PDC202XX_MASTER
 769         if (!(primary_mode & 1)) {
 770                 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
 771                         "0x%02x -> 0x%02x ", hwif->cds->name,
 772                         primary_mode, (primary_mode|1));
 773                 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
 774                 printk("%s\n",
 775                         (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
 776         }
 777
 778         if (!(secondary_mode & 1)) {
 779                 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
 780                         "0x%02x -> 0x%02x ", hwif->cds->name,
 781                         secondary_mode, (secondary_mode|1));
 782                 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
 783                 printk("%s\n",
 784                         (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
 785         }
 786 #endif /* CONFIG_PDC202XX_MASTER */
 787
 788         ide_setup_dma(hwif, dmabase, 8);
 789 }
 790
 791 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
 792 extern void ide_setup_pci_devices(struct pci_dev *, struct pci_dev *, ide_pci_device_t *);
 793
 794 static void __init init_setup_pdc202ata4 (struct pci_dev *dev, ide_pci_device_t *d)
 795 {
 796         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 797                 u8 irq = 0, irq2 = 0;
 798                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 799                 /* 0xbc */
 800                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 801                 if (irq != irq2) {
 802                         pci_write_config_byte(dev,
 803                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 804                         printk(KERN_INFO "%s: pci-config space interrupt "
 805                                 "mirror fixed.\n", d->name);
 806                 }
 807         }
 808
 809         ide_setup_pci_device(dev, d);
 810 }
 811
 812 static void __init init_setup_pdc20265 (struct pci_dev *dev, ide_pci_device_t *d)
 813 {
 814         if ((dev->bus->self) &&
 815             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 816             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 817              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 818                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 819                         "attached to I2O RAID controller.\n");
 820                 return;
 821         }
 822         ide_setup_pci_device(dev, d);
 823 }
 824
 825 static void __init init_setup_pdc202xx (struct pci_dev *dev, ide_pci_device_t *d)
 826 {
 827         ide_setup_pci_device(dev, d);
 828 }
 829
 830 /**
 831  *      pdc202xx_init_one       -       called when a PDC202xx is found
 832  *      @dev: the pdc202xx device
 833  *      @id: the matching pci id
 834  *
 835  *      Called when the PCI registration layer (or the IDE initialization)
 836  *      finds a device matching our IDE device tables.
 837  */
 838
 839 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 840 {
 841         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 842
 843         if (dev->device != d->device)
 844                 BUG();
 845         d->init_setup(dev, d);
 846         MOD_INC_USE_COUNT;
 847         return 0;
 848 }
 849
 850 static struct pci_device_id pdc202xx_pci_tbl[] __devinitdata = {
 851         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 852         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 853         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 854         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 855         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 856         { 0, },
 857 };
 858
 859 static struct pci_driver driver = {
 860         .name           = "Promise Old IDE",
 861         .id_table       = pdc202xx_pci_tbl,
 862         .probe          = pdc202xx_init_one,
 863 };
 864
 865 static int pdc202xx_ide_init(void)
 866 {
 867         return ide_pci_register_driver(&driver);
 868 }
 869
 870 static void pdc202xx_ide_exit(void)
 871 {
 872         ide_pci_unregister_driver(&driver);
 873 }
 874
 875 module_init(pdc202xx_ide_init);
 876 module_exit(pdc202xx_ide_exit);
 877
 878 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 879 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 880 MODULE_LICENSE("GPL");
 881
 882 EXPORT_NO_SYMBOLS;