2 * linux/drivers/ide/pci/piix.c Version 0.42 January 11, 2003
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
8 * May be copied or modified under the terms of the GNU General Public License
10 * PIO mode setting function for Intel chipsets.
11 * For use instead of BIOS settings.
19 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
20 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
21 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
22 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
24 * sitre = word40 & 0x4000; primary
25 * sitre = word42 & 0x4000; secondary
27 * 44 8421|8421 hdd|hdb
29 * 48 8421 hdd|hdc|hdb|hda udma enabled
41 * ata-33/82801AB ata-66/82801AA
42 * 00|00 udma 0 00|00 reserved
43 * 01|01 udma 1 01|01 udma 3
44 * 10|10 udma 2 10|10 udma 4
45 * 11|11 reserved 11|11 reserved
47 * 54 8421|8421 ata66 drive|ata66 enable
49 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
52 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
53 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
54 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
57 * Publically available from Intel web site. Errata documentation
58 * is also publically available. As an aide to anyone hacking on this
59 * driver the list of errata that are relevant is below.going back to
60 * PIIX4. Older device documentation is now a bit tricky to find.
65 * PIIX4 errata #9 - Only on ultra obscure hw
66 * ICH3 errata #13 - Not observed to affect real hw
69 * Things we must deal with
70 * PIIX4 errata #10 - BM IDE hang with non UDMA
71 * (must stop/start dma to recover)
72 * 440MX errata #15 - As PIIX4 errata #10
73 * PIIX4 errata #15 - Must not read control registers
74 * during a PIO transfer
75 * 440MX errata #13 - As PIIX4 errata #15
76 * ICH2 errata #21 - DMA mode 0 doesn't work right
77 * ICH0/1 errata #55 - As ICH2 errata #21
78 * ICH2 spec c #9 - Extra operations needed to handle
79 * drive hotswap [NOT YET SUPPORTED]
80 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
81 * and must be dword aligned
82 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
84 * Should have been BIOS fixed:
85 * 450NX: errata #19 - DMA hangs on old 450NX
86 * 450NX: errata #20 - DMA hangs on old 450NX
87 * 450NX: errata #25 - Corruption with DMA on old 450NX
88 * ICH3 errata #15 - IDE deadlock under high load
89 * (BIOS must set dev 31 fn 0 bit 23)
90 * ICH3 errata #18 - Don't use native mode
93 #include <linux/config.h>
94 #include <linux/types.h>
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/ioport.h>
98 #include <linux/pci.h>
99 #include <linux/hdreg.h>
100 #include <linux/ide.h>
101 #include <linux/delay.h>
102 #include <linux/init.h>
106 #include "ide_modes.h"
109 #if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
110 #include <linux/stat.h>
111 #include <linux/proc_fs.h>
113 static u8 piix_proc = 0;
114 #define PIIX_MAX_DEVS 5
115 static struct pci_dev *piix_devs[PIIX_MAX_DEVS];
116 static int n_piix_devs;
117 static int no_piix_dma = 0;
120 * piix_get_info - fill in /proc for PIIX ide
121 * @buffer: buffer to fill
122 * @addr: address of user start in buffer
123 * @offset: offset into 'file'
124 * @count: buffer count
126 * Walks the PIIX devices and outputs summary data on the tuning and
127 * anything else that will help with debugging
130 static int piix_get_info (char *buffer, char **addr, off_t offset, int count)
135 for (i = 0; i < n_piix_devs; i++) {
136 struct pci_dev *dev = piix_devs[i];
137 unsigned long bibma = pci_resource_start(dev, 4);
138 u16 reg40 = 0, psitre = 0, reg42 = 0, ssitre = 0;
139 u8 c0 = 0, c1 = 0, reg54 = 0, reg55 = 0;
140 u8 reg44 = 0, reg48 = 0, reg4a = 0, reg4b = 0;
142 p += sprintf(p, "\nController: %d\n", i);
143 p += sprintf(p, "\n Intel ");
144 switch(dev->device) {
145 case PCI_DEVICE_ID_INTEL_82801EB_1:
146 p += sprintf(p, "PIIX4 SATA 150 ");
148 case PCI_DEVICE_ID_INTEL_82801BA_8:
149 case PCI_DEVICE_ID_INTEL_82801BA_9:
150 case PCI_DEVICE_ID_INTEL_82801CA_10:
151 case PCI_DEVICE_ID_INTEL_82801CA_11:
152 case PCI_DEVICE_ID_INTEL_82801DB_10:
153 case PCI_DEVICE_ID_INTEL_82801DB_11:
154 case PCI_DEVICE_ID_INTEL_82801EB_11:
155 case PCI_DEVICE_ID_INTEL_82801E_11:
156 case PCI_DEVICE_ID_INTEL_ESB_2:
157 case PCI_DEVICE_ID_INTEL_ICH6_2:
158 p += sprintf(p, "PIIX4 Ultra 100 ");
160 case PCI_DEVICE_ID_INTEL_82372FB_1:
161 case PCI_DEVICE_ID_INTEL_82801AA_1:
162 p += sprintf(p, "PIIX4 Ultra 66 ");
164 case PCI_DEVICE_ID_INTEL_82451NX:
165 case PCI_DEVICE_ID_INTEL_82801AB_1:
166 case PCI_DEVICE_ID_INTEL_82443MX_1:
167 case PCI_DEVICE_ID_INTEL_82371AB:
168 p += sprintf(p, "PIIX4 Ultra 33 ");
170 case PCI_DEVICE_ID_INTEL_82371SB_1:
171 p += sprintf(p, "PIIX3 ");
173 case PCI_DEVICE_ID_INTEL_82371MX:
174 p += sprintf(p, "MPIIX ");
176 case PCI_DEVICE_ID_INTEL_82371FB_1:
177 case PCI_DEVICE_ID_INTEL_82371FB_0:
179 p += sprintf(p, "PIIX ");
182 p += sprintf(p, "Chipset.\n");
184 if (dev->device == PCI_DEVICE_ID_INTEL_82371MX)
187 pci_read_config_word(dev, 0x40, ®40);
188 pci_read_config_word(dev, 0x42, ®42);
189 pci_read_config_byte(dev, 0x44, ®44);
190 pci_read_config_byte(dev, 0x48, ®48);
191 pci_read_config_byte(dev, 0x4a, ®4a);
192 pci_read_config_byte(dev, 0x4b, ®4b);
193 pci_read_config_byte(dev, 0x54, ®54);
194 pci_read_config_byte(dev, 0x55, ®55);
196 psitre = (reg40 & 0x4000) ? 1 : 0;
197 ssitre = (reg42 & 0x4000) ? 1 : 0;
200 * at that point bibma+0x2 et bibma+0xa are byte registers
203 c0 = inb(bibma + 0x02);
204 c1 = inb(bibma + 0x0a);
206 p += sprintf(p, "--------------- Primary Channel "
207 "---------------- Secondary Channel "
209 p += sprintf(p, " %sabled "
211 (c0&0x80) ? "dis" : " en",
212 (c1&0x80) ? "dis" : " en");
213 p += sprintf(p, "--------------- drive0 --------- drive1 "
214 "-------- drive0 ---------- drive1 ------\n");
215 p += sprintf(p, "DMA enabled: %s %s "
217 (c0&0x20) ? "yes" : "no ",
218 (c0&0x40) ? "yes" : "no ",
219 (c1&0x20) ? "yes" : "no ",
220 (c1&0x40) ? "yes" : "no " );
221 p += sprintf(p, "UDMA enabled: %s %s "
223 (reg48&0x01) ? "yes" : "no ",
224 (reg48&0x02) ? "yes" : "no ",
225 (reg48&0x04) ? "yes" : "no ",
226 (reg48&0x08) ? "yes" : "no " );
227 p += sprintf(p, "UDMA enabled: %s %s "
230 (reg55&0x10) && (reg4a&0x01)) ? "5" :
231 ((reg54&0x11) && (reg4a&0x02)) ? "4" :
232 ((reg54&0x11) && (reg4a&0x01)) ? "3" :
235 (reg4a&0x00) ? "0" : "X",
237 (reg55&0x20) && (reg4a&0x10)) ? "5" :
238 ((reg54&0x22) && (reg4a&0x20)) ? "4" :
239 ((reg54&0x22) && (reg4a&0x10)) ? "3" :
242 (reg4a&0x00) ? "0" : "X",
244 (reg55&0x40) && (reg4b&0x03)) ? "5" :
245 ((reg54&0x44) && (reg4b&0x02)) ? "4" :
246 ((reg54&0x44) && (reg4b&0x01)) ? "3" :
249 (reg4b&0x00) ? "0" : "X",
251 (reg55&0x80) && (reg4b&0x30)) ? "5" :
252 ((reg54&0x88) && (reg4b&0x20)) ? "4" :
253 ((reg54&0x88) && (reg4b&0x10)) ? "3" :
256 (reg4b&0x00) ? "0" : "X");
258 p += sprintf(p, "UDMA\n");
259 p += sprintf(p, "DMA\n");
260 p += sprintf(p, "PIO\n");
263 * FIXME.... Add configuration junk data....blah blah......
266 return p-buffer; /* => must be less than 4k! */
268 #endif /* defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS) */
271 * piix_ratemask - compute rate mask for PIIX IDE
272 * @drive: IDE drive to compute for
274 * Returns the available modes for the PIIX IDE controller.
277 static u8 piix_ratemask (ide_drive_t *drive)
279 struct pci_dev *dev = HWIF(drive)->pci_dev;
282 switch(dev->device) {
283 case PCI_DEVICE_ID_INTEL_82801EB_1:
286 /* UDMA 100 capable */
287 case PCI_DEVICE_ID_INTEL_82801BA_8:
288 case PCI_DEVICE_ID_INTEL_82801BA_9:
289 case PCI_DEVICE_ID_INTEL_82801CA_10:
290 case PCI_DEVICE_ID_INTEL_82801CA_11:
291 case PCI_DEVICE_ID_INTEL_82801E_11:
292 case PCI_DEVICE_ID_INTEL_82801DB_10:
293 case PCI_DEVICE_ID_INTEL_82801DB_11:
294 case PCI_DEVICE_ID_INTEL_82801EB_11:
295 case PCI_DEVICE_ID_INTEL_ESB_2:
296 case PCI_DEVICE_ID_INTEL_ICH6_2:
299 /* UDMA 66 capable */
300 case PCI_DEVICE_ID_INTEL_82801AA_1:
301 case PCI_DEVICE_ID_INTEL_82372FB_1:
304 /* UDMA 33 capable */
305 case PCI_DEVICE_ID_INTEL_82371AB:
306 case PCI_DEVICE_ID_INTEL_82443MX_1:
307 case PCI_DEVICE_ID_INTEL_82451NX:
308 case PCI_DEVICE_ID_INTEL_82801AB_1:
310 /* Non UDMA capable (MWDMA2) */
311 case PCI_DEVICE_ID_INTEL_82371SB_1:
312 case PCI_DEVICE_ID_INTEL_82371FB_1:
313 case PCI_DEVICE_ID_INTEL_82371FB_0:
314 case PCI_DEVICE_ID_INTEL_82371MX:
320 * If we are UDMA66 capable fall back to UDMA33
321 * if the drive cannot see an 80pin cable.
323 if (!eighty_ninty_three(drive))
324 mode = min(mode, (u8)1);
329 * piix_dma_2_pio - return the PIO mode matching DMA
330 * @xfer_rate: transfer speed
332 * Returns the nearest equivalent PIO timing for the PIO or DMA
333 * mode requested by the controller.
336 static u8 piix_dma_2_pio (u8 xfer_rate) {
366 * piix_tune_drive - tune a drive attached to a PIIX
367 * @drive: drive to tune
368 * @pio: desired PIO mode
370 * Set the interface PIO mode based upon the settings done by AMI BIOS
371 * (might be useful if drive is not registered in CMOS for any reason).
373 static void piix_tune_drive (ide_drive_t *drive, u8 pio)
375 ide_hwif_t *hwif = HWIF(drive);
376 struct pci_dev *dev = hwif->pci_dev;
377 int is_slave = (&hwif->drives[1] == drive);
378 int master_port = hwif->channel ? 0x42 : 0x40;
379 int slave_port = 0x44;
384 u8 timings[][2] = { { 0, 0 },
390 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
391 spin_lock_irqsave(&ide_lock, flags);
392 pci_read_config_word(dev, master_port, &master_data);
394 master_data = master_data | 0x4000;
396 /* enable PPE, IE and TIME */
397 master_data = master_data | 0x0070;
398 pci_read_config_byte(dev, slave_port, &slave_data);
399 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
400 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
402 master_data = master_data & 0xccf8;
404 /* enable PPE, IE and TIME */
405 master_data = master_data | 0x0007;
406 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
408 pci_write_config_word(dev, master_port, master_data);
410 pci_write_config_byte(dev, slave_port, slave_data);
411 spin_unlock_irqrestore(&ide_lock, flags);
415 * piix_tune_chipset - tune a PIIX interface
416 * @drive: IDE drive to tune
417 * @xferspeed: speed to configure
419 * Set a PIIX interface channel to the desired speeds. This involves
420 * requires the right timing data into the PIIX configuration space
421 * then setting the drive parameters appropriately
424 static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
426 ide_hwif_t *hwif = HWIF(drive);
427 struct pci_dev *dev = hwif->pci_dev;
428 u8 maslave = hwif->channel ? 0x42 : 0x40;
429 u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed);
430 int a_speed = 3 << (drive->dn * 4);
431 int u_flag = 1 << drive->dn;
432 int v_flag = 0x01 << drive->dn;
433 int w_flag = 0x10 << drive->dn;
437 u8 reg48, reg54, reg55;
439 pci_read_config_word(dev, maslave, ®4042);
440 sitre = (reg4042 & 0x4000) ? 1 : 0;
441 pci_read_config_byte(dev, 0x48, ®48);
442 pci_read_config_word(dev, 0x4a, ®4a);
443 pci_read_config_byte(dev, 0x54, ®54);
444 pci_read_config_byte(dev, 0x55, ®55);
448 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
451 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
452 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
455 case XFER_SW_DMA_2: break;
459 case XFER_PIO_0: break;
463 if (speed >= XFER_UDMA_0) {
464 if (!(reg48 & u_flag))
465 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
466 if (speed == XFER_UDMA_5) {
467 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
469 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
471 if ((reg4a & a_speed) != u_speed)
472 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
473 if (speed > XFER_UDMA_2) {
474 if (!(reg54 & v_flag))
475 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
477 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
480 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
482 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
484 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
486 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
489 piix_tune_drive(drive, piix_dma_2_pio(speed));
490 return (ide_config_drive_speed(drive, speed));
494 * piix_faulty_dma0 - check for DMA0 errata
495 * @hwif: IDE interface to check
497 * If an ICH/ICH0/ICH2 interface is is operating in multi-word
498 * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
499 * inadvertently provide an extra piece of secondary data to the primary
500 * device resulting in data corruption.
502 * With such a device this test function returns true. This allows
503 * our tuning code to follow Intel recommendations and use PIO on
507 static int piix_faulty_dma0(ide_hwif_t *hwif)
509 switch(hwif->pci_dev->device)
511 case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */
512 case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */
513 case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */
514 case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */
521 * piix_config_drive_for_dma - configure drive for DMA
522 * @drive: IDE drive to configure
524 * Set up a PIIX interface channel for the best available speed.
525 * We prefer UDMA if it is available and then MWDMA. If DMA is
526 * not available we switch to PIO and return 0.
529 static int piix_config_drive_for_dma (ide_drive_t *drive)
531 u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
533 /* Some ICH devices cannot support DMA mode 0 */
534 if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
537 /* If no DMA speed was available or the chipset has DMA bugs
538 then disable DMA and use PIO */
540 if (!speed || no_piix_dma) {
541 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
542 speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
545 (void) piix_tune_chipset(drive, speed);
546 return ide_dma_enable(drive);
550 * piix_config_drive_xfer_rate - set up an IDE device
551 * @drive: IDE drive to configure
553 * Set up the PIIX interface for the best available speed on this
554 * interface, preferring DMA to PIO.
557 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
559 ide_hwif_t *hwif = HWIF(drive);
560 struct hd_driveid *id = drive->id;
562 drive->init_speed = 0;
564 if ((id->capability & 1) && (drive->autodma)) {
566 /* Consult the list of known "bad" drives. */
567 if (hwif->ide_dma_bad_drive(drive)) {
572 * Try to turn DMA on if:
573 * - UDMA or EIDE modes are supported or
574 * - drive is a known "good" drive
576 * Checks for best mode supported are down later by
577 * piix_config_drive_for_dma() -> ide_dma_speed()
579 if ((id->field_valid & (4 | 2)) ||
580 (hwif->ide_dma_good_drive(drive) && (id->eide_dma_time < 150))) {
581 if (piix_config_drive_for_dma(drive)) {
582 return hwif->ide_dma_on(drive);
586 /* For some reason DMA wasn't turned on, so try PIO. */
589 } else if ((id->capability & 8) || (id->field_valid & 2)) {
591 /* Find best PIO mode. */
593 hwif->tuneproc(drive, 255);
594 return hwif->ide_dma_off_quietly(drive);
598 /* IORDY not supported */
603 * ich3_busproc - bus isolation ioctl
604 * @drive: drive to isolate/restore
605 * @state: bus state to set
607 * Used by the ICH3 to handle bus isolation. We have to do
608 * a little bit of fixing to keep the hardware happy.
611 static int ich3_busproc (ide_drive_t * drive, int state)
613 ide_hwif_t *hwif = HWIF(drive);
618 if(hwif->channel == 0)
626 hwif->drives[0].failures = 0;
627 hwif->drives[1].failures = 0;
632 case BUSSTATE_TRISTATE:
641 int port = hwif->channel == 0 ? 0x40 : 0x42;
643 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
644 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
645 /* Turn off IORDY checking to avoid hangs */
646 pci_read_config_word(hwif->pci_dev, port, ®);
648 pci_write_config_word(hwif->pci_dev, port, reg);
650 /* Todo: Check locking */
651 pci_read_config_dword(hwif->pci_dev, 0x54, &sig_mode);
652 sig_mode&=~(3<<shift);
653 sig_mode|=(bits<<shift);
654 pci_write_config_dword(hwif->pci_dev, 0x54, sig_mode);
656 hwif->bus_state = state;
662 * init_chipset_piix - set up the PIIX chipset
663 * @dev: PCI device to set up
664 * @name: Name of the device
666 * Initialize the PCI device as required. For the PIIX this turns
667 * out to be nice and simple
670 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
672 switch(dev->device) {
673 case PCI_DEVICE_ID_INTEL_82801EB_1:
674 case PCI_DEVICE_ID_INTEL_82801AA_1:
675 case PCI_DEVICE_ID_INTEL_82801AB_1:
676 case PCI_DEVICE_ID_INTEL_82801BA_8:
677 case PCI_DEVICE_ID_INTEL_82801BA_9:
678 case PCI_DEVICE_ID_INTEL_82801CA_10:
679 case PCI_DEVICE_ID_INTEL_82801CA_11:
680 case PCI_DEVICE_ID_INTEL_82801DB_10:
681 case PCI_DEVICE_ID_INTEL_82801DB_11:
682 case PCI_DEVICE_ID_INTEL_82801EB_11:
683 case PCI_DEVICE_ID_INTEL_82801E_11:
684 case PCI_DEVICE_ID_INTEL_ESB_2:
685 case PCI_DEVICE_ID_INTEL_ICH6_2:
687 unsigned int extra = 0;
688 pci_read_config_dword(dev, 0x54, &extra);
689 pci_write_config_dword(dev, 0x54, extra|0x400);
695 #if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
696 piix_devs[n_piix_devs++] = dev;
700 ide_pci_register_host_proc(&piix_procs[0]);
702 #endif /* DISPLAY_PIIX_TIMINGS && CONFIG_PROC_FS */
707 * init_hwif_piix - fill in the hwif for the PIIX
708 * @hwif: IDE interface
710 * Set up the ide_hwif_t for the PIIX interface according to the
711 * capabilities of the hardware.
714 static void __init init_hwif_piix (ide_hwif_t *hwif)
716 u8 reg54h = 0, reg55h = 0, ata66 = 0;
717 u8 mask = hwif->channel ? 0xc0 : 0x30;
721 hwif->irq = hwif->channel ? 15 : 14;
722 #endif /* CONFIG_IA64 */
724 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
725 /* This is a painful system best to let it self tune for now */
730 hwif->tuneproc = &piix_tune_drive;
731 hwif->speedproc = &piix_tune_chipset;
732 hwif->drives[0].autotune = 1;
733 hwif->drives[1].autotune = 1;
739 hwif->ultra_mask = 0x3f;
740 hwif->mwdma_mask = 0x06;
741 hwif->swdma_mask = 0x04;
743 switch(hwif->pci_dev->device) {
744 case PCI_DEVICE_ID_INTEL_82371MX:
745 hwif->mwdma_mask = 0x80;
746 hwif->swdma_mask = 0x80;
747 case PCI_DEVICE_ID_INTEL_82371FB_0:
748 case PCI_DEVICE_ID_INTEL_82371FB_1:
749 case PCI_DEVICE_ID_INTEL_82371SB_1:
750 hwif->ultra_mask = 0x80;
752 case PCI_DEVICE_ID_INTEL_82371AB:
753 case PCI_DEVICE_ID_INTEL_82443MX_1:
754 case PCI_DEVICE_ID_INTEL_82451NX:
755 case PCI_DEVICE_ID_INTEL_82801AB_1:
756 hwif->ultra_mask = 0x07;
758 case PCI_DEVICE_ID_INTEL_82801CA_10:
759 case PCI_DEVICE_ID_INTEL_82801CA_11:
760 hwif->busproc = ich3_busproc;
763 pci_read_config_byte(hwif->pci_dev, 0x54, ®54h);
764 pci_read_config_byte(hwif->pci_dev, 0x55, ®55h);
765 ata66 = (reg54h & mask) ? 1 : 0;
769 if (!(hwif->udma_four))
770 hwif->udma_four = ata66;
771 hwif->ide_dma_check = &piix_config_drive_xfer_rate;
775 hwif->drives[1].autodma = hwif->autodma;
776 hwif->drives[0].autodma = hwif->autodma;
780 * init_dma_piix - set up the PIIX DMA
781 * @hwif: IDE interface
782 * @dmabase: DMA PCI base
784 * Set up the DMA on the PIIX controller, providing a DMA base is
785 * available. The PIIX follows the normal specs so we do nothing
789 static void __init init_dma_piix (ide_hwif_t *hwif, unsigned long dmabase)
791 ide_setup_dma(hwif, dmabase, 8);
794 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
797 * init_setup_piix - callback for IDE initialize
798 * @dev: PIIX PCI device
801 * Enable the xp fixup for the PIIX controller and then perform
802 * a standard ide PCI setup
805 static void __init init_setup_piix (struct pci_dev *dev, ide_pci_device_t *d)
807 ide_setup_pci_device(dev, d);
811 * piix_init_one - called when a PIIX is found
812 * @dev: the piix device
813 * @id: the matching pci id
815 * Called when the PCI registration layer (or the IDE initialization)
816 * finds a device matching our IDE device tables.
819 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
821 ide_pci_device_t *d = &piix_pci_info[id->driver_data];
823 if (dev->device != d->device)
825 d->init_setup(dev, d);
831 * piix_check_450nx - Check for problem 450NX setup
833 * Check for the present of 450NX errata #19 and errata #25. If
834 * they are found, disable use of DMA IDE
837 static void __init piix_check_450nx(void)
839 struct pci_dev *pdev = NULL;
842 while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
844 /* Look for 450NX PXB. Check for problem configurations
845 A PCI quirk checks bit 6 already */
846 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
847 pci_read_config_word(pdev, 0x41, &cfg);
848 /* Only on the original revision: IDE DMA can hang */
851 /* On all revisions PXB bus lock must be disabled for IDE */
852 else if(cfg & (1<<14))
856 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
858 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
861 static struct pci_device_id piix_pci_tbl[] __devinitdata = {
862 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
863 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
864 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
865 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
866 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
867 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
868 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
869 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
870 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
871 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
872 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
873 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
874 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
875 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
876 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
877 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
878 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
879 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
880 #ifdef CONFIG_BLK_DEV_IDE_SATA
881 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
883 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
884 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
888 static struct pci_driver driver = {
890 .id_table = piix_pci_tbl,
891 .probe = piix_init_one,
894 static int piix_ide_init(void)
897 return ide_pci_register_driver(&driver);
900 static void piix_ide_exit(void)
902 ide_pci_unregister_driver(&driver);
905 module_init(piix_ide_init);
906 module_exit(piix_ide_exit);
908 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
909 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
910 MODULE_LICENSE("GPL");