2 * Copyright (c) 2003 Silicon Graphics, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 * Further, this software is distributed without any warranty that it is
13 * free of the rightful claim of any third person regarding infringement
14 * or the like. Any license provided herein, whether implied or
15 * otherwise, applies only to this software file. Patent licenses, if
16 * any, provided herein do not apply to combinations of this program with
17 * other software, or any other product whatsoever.
19 * You should have received a copy of the GNU General Public
20 * License along with this program; if not, write the Free Software
21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
24 * Mountain View, CA 94043, or:
28 * For further information regarding this notice, see:
30 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
36 #define IDE_ARCH_ACK_INTR 1
37 #include <linux/ide.h>
39 /* IOC4 Specific Definitions */
40 #define IOC4_CMD_OFFSET 0x100
41 #define IOC4_CTRL_OFFSET 0x120
42 #define IOC4_DMA_OFFSET 0x140
43 #define IOC4_INTR_OFFSET 0x0
45 #define IOC4_TIMING 0x00
46 #define IOC4_DMA_PTR_L 0x01
47 #define IOC4_DMA_PTR_H 0x02
48 #define IOC4_DMA_ADDR_L 0x03
49 #define IOC4_DMA_ADDR_H 0x04
50 #define IOC4_BC_DEV 0x05
51 #define IOC4_BC_MEM 0x06
52 #define IOC4_DMA_CTRL 0x07
53 #define IOC4_DMA_END_ADDR 0x08
55 /* Bits in the IOC4 Control/Status Register */
56 #define IOC4_S_DMA_START 0x01
57 #define IOC4_S_DMA_STOP 0x02
58 #define IOC4_S_DMA_DIR 0x04
59 #define IOC4_S_DMA_ACTIVE 0x08
60 #define IOC4_S_DMA_ERROR 0x10
61 #define IOC4_ATA_MEMERR 0x02
63 /* Read/Write Directions */
64 #define IOC4_DMA_WRITE 0x04
65 #define IOC4_DMA_READ 0x00
67 /* Interrupt Register Offsets */
68 #define IOC4_INTR_REG 0x03
69 #define IOC4_INTR_SET 0x05
70 #define IOC4_INTR_CLEAR 0x07
72 #define IOC4_IDE_CACHELINE_SIZE 128
73 #define IOC4_SUPPORTED_FIRMWARE_REV 46
76 /* Weeds out non-IDE interrupts to the IOC4 */
77 #define ide_ack_intr(hwif) ((hwif)->hw.ack_intr ? (hwif)->hw.ack_intr(hwif) : 1)
79 #define SGIIOC4_MAX_DEVS 32
81 #if defined(CONFIG_PROC_FS)
82 #include <linux/stat.h>
83 #include <linux/proc_fs.h>
85 static u8 sgiioc4_proc;
87 static struct pci_dev *sgiioc4_devs[SGIIOC4_MAX_DEVS];
88 static int sgiioc4_get_info(char *, char **, off_t, int);
90 static ide_pci_host_proc_t sgiioc4_procs[] __initdata = {
94 .get_info = sgiioc4_get_info,
100 typedef volatile struct {
112 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
113 /* IOC4 has only 1 IDE channel */
114 #define IOC4_PRD_BYTES 16
115 #define IOC4_PRD_ENTRIES (PAGE_SIZE /IOC4_PRD_BYTES)
117 typedef enum pciio_endian_e {
122 static void sgiioc4_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
123 ide_ioreg_t ctrl_port, ide_ioreg_t irq_port);
124 static void sgiioc4_ide_setup_pci_device(struct pci_dev *dev, const char *name);
125 static void sgiioc4_resetproc(ide_drive_t * drive);
126 static void sgiioc4_maskproc(ide_drive_t * drive, int mask);
127 static void sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive);
128 static void __init ide_init_sgiioc4(ide_hwif_t * hwif);
129 static void __init ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base);
130 static int sgiioc4_checkirq(ide_hwif_t * hwif);
131 static int sgiioc4_clearirq(ide_drive_t * drive);
132 static int sgiioc4_get_info(char *buffer, char **addr, off_t offset, int count);
133 static int sgiioc4_ide_dma_read(ide_drive_t * drive);
134 static int sgiioc4_ide_dma_write(ide_drive_t * drive);
135 static int sgiioc4_ide_dma_begin(ide_drive_t * drive);
136 static int sgiioc4_ide_dma_end(ide_drive_t * drive);
137 static int sgiioc4_ide_dma_check(ide_drive_t * drive);
138 static int sgiioc4_ide_dma_on(ide_drive_t * drive);
139 static int sgiioc4_ide_dma_off(ide_drive_t * drive);
140 static int sgiioc4_ide_dma_off_quietly(ide_drive_t * drive);
141 static int sgiioc4_ide_dma_test_irq(ide_drive_t * drive);
142 static int sgiioc4_ide_dma_host_on(ide_drive_t * drive);
143 static int sgiioc4_ide_dma_host_off(ide_drive_t * drive);
144 static int sgiioc4_ide_dma_count(ide_drive_t * drive);
145 static int sgiioc4_ide_dma_verbose(ide_drive_t * drive);
146 static int sgiioc4_ide_dma_lostirq(ide_drive_t * drive);
147 static int sgiioc4_ide_dma_timeout(ide_drive_t * drive);
148 static int sgiioc4_ide_build_sglist(ide_hwif_t * hwif, struct request *rq,
150 static int sgiioc4_ide_raw_build_sglist(ide_hwif_t * hwif, struct request *rq);
152 static u8 sgiioc4_INB(unsigned long port);
153 static inline void xide_delay(long ticks);
154 extern int (*sgiioc4_display_info) (char *, char **, off_t, int); /* ide-proc.c */
155 static unsigned int sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq,
157 static unsigned int __init pci_init_sgiioc4(struct pci_dev *dev, const char *name);
159 static ide_pci_device_t sgiioc4_chipsets[] __devinitdata = {
162 .vendor = PCI_VENDOR_ID_SGI,
163 .device = PCI_DEVICE_ID_SGI_IOC4,
165 .init_chipset = pci_init_sgiioc4,
167 .init_hwif = ide_init_sgiioc4,
168 .init_dma = ide_dma_sgiioc4,
171 .enablebits = { { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 } },
172 .bootable = ON_BOARD,