2 * linux/drivers/ide/ppc/ide-m8xx.c
4 * Copyright (C) 2000, 2001 Wolfgang Denk, wd@denx.de
5 * Modified for direct IDE interface
6 * by Thomas Lange, thomas@corelatus.com
7 * Modified for direct IDE interface on 8xx without using the PCMCIA
9 * by Steven.Scholz@imc-berlin.de
10 * Moved out of arch/ppc/kernel/m8xx_setup.c, other minor cleanups
11 * by Mathew Locke <mattl@mvista.com>
14 #include <linux/config.h>
15 #include <linux/errno.h>
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
19 #include <linux/stddef.h>
20 #include <linux/unistd.h>
21 #include <linux/ptrace.h>
22 #include <linux/slab.h>
23 #include <linux/user.h>
24 #include <linux/a.out.h>
25 #include <linux/tty.h>
26 #include <linux/major.h>
27 #include <linux/interrupt.h>
28 #include <linux/reboot.h>
29 #include <linux/init.h>
30 #include <linux/blk.h>
31 #include <linux/ioport.h>
32 #include <linux/ide.h>
33 #include <linux/bootmem.h>
35 #include <asm/mpc8xx.h>
37 #include <asm/processor.h>
38 #include <asm/residual.h>
40 #include <asm/pgtable.h>
42 #include <asm/8xx_immap.h>
43 #include <asm/machdep.h>
46 #include "ide_modes.h"
47 static int identify (volatile u8 *p);
48 static void print_fixed (volatile u8 *p);
49 static void print_funcid (int func);
50 static int check_ide_device (unsigned long base);
52 static void ide_interrupt_ack (void *dev);
53 static void m8xx_ide_tuneproc(ide_drive_t *drive, u8 pio);
55 typedef struct ide_ioport_desc {
56 unsigned long base_off; /* Offset to PCMCIA memory */
57 ide_ioreg_t reg_off[IDE_NR_PORTS]; /* controller register offsets */
61 ide_ioport_desc_t ioport_dsc[MAX_HWIFS] = {
62 #ifdef IDE0_BASE_OFFSET
66 IDE0_ERROR_REG_OFFSET,
67 IDE0_NSECTOR_REG_OFFSET,
68 IDE0_SECTOR_REG_OFFSET,
71 IDE0_SELECT_REG_OFFSET,
72 IDE0_STATUS_REG_OFFSET,
73 IDE0_CONTROL_REG_OFFSET,
78 #ifdef IDE1_BASE_OFFSET
82 IDE1_ERROR_REG_OFFSET,
83 IDE1_NSECTOR_REG_OFFSET,
84 IDE1_SECTOR_REG_OFFSET,
87 IDE1_SELECT_REG_OFFSET,
88 IDE1_STATUS_REG_OFFSET,
89 IDE1_CONTROL_REG_OFFSET,
94 #endif /* IDE1_BASE_OFFSET */
95 #endif /* IDE0_BASE_OFFSET */
98 ide_pio_timings_t ide_pio_clocks[6];
99 int hold_time[6] = {30, 20, 15, 10, 10, 10 }; /* PIO Mode 5 with IORDY (nonstandard) */
102 * Warning: only 1 (ONE) PCMCIA slot supported here,
103 * which must be correctly initialized by the firmware (PPCBoot).
105 static int _slot_ = -1; /* will be read from PCMCIA registers */
107 /* Make clock cycles and always round up */
108 #define PCMCIA_MK_CLKS( t, T ) (( (t) * ((T)/1000000) + 999U ) / 1000U )
116 m8xx_ide_default_irq(ide_ioreg_t base)
118 #ifdef CONFIG_BLK_DEV_MPC8xx_IDE
119 if (base >= MAX_HWIFS)
122 printk("[%d] m8xx_ide_default_irq %d\n",__LINE__,ioport_dsc[base].irq);
124 return (ioport_dsc[base].irq);
131 m8xx_ide_default_io_base(int index)
136 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
137 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
140 * The TQM850L hardware has two pins swapped! Grrrrgh!
142 #ifdef CONFIG_TQM850L
143 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
144 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
146 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
147 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
150 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
151 #define PCMCIA_SCHLVL IDE0_INTERRUPT /* Status Change Interrupt Level */
152 static int pcmcia_schlvl = PCMCIA_SCHLVL;
156 * See include/linux/ide.h for definition of hw_regs_t (p, base)
160 * m8xx_ide_init_hwif_ports for a direct IDE interface _using_
162 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
164 m8xx_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port,
165 ide_ioreg_t ctrl_port, int *irq)
167 ide_ioreg_t *p = hw->io_ports;
174 volatile pcmcia_win_t *win;
175 volatile pcmconf8xx_t *pcmp;
180 static unsigned long pcmcia_base = 0;
187 pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
191 * Read out PCMCIA registers. Since the reset values
192 * are undefined, we sure hope that they have been
196 /* Scan all registers for valid settings */
197 pcmcia_phy_base = 0xFFFFFFFF;
199 /* br0 is start of brX and orX regs */
200 win = (pcmcia_win_t *) \
201 (&(((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0));
202 for (i = 0; i < 8; i++) {
203 if (win->or & 1) { /* This bank is marked as valid */
204 if (win->br < pcmcia_phy_base) {
205 pcmcia_phy_base = win->br;
207 if ((win->br + PCMCIA_MEM_SIZE) > pcmcia_phy_end) {
208 pcmcia_phy_end = win->br + PCMCIA_MEM_SIZE;
210 /* Check which slot that has been defined */
211 _slot_ = (win->or >> 2) & 1;
217 printk ("PCMCIA slot %c: phys mem %08x...%08x (size %08x)\n",
219 pcmcia_phy_base, pcmcia_phy_end,
220 pcmcia_phy_end - pcmcia_phy_base);
222 pcmcia_base=(unsigned long)ioremap(pcmcia_phy_base,
223 pcmcia_phy_end-pcmcia_phy_base);
226 printk ("PCMCIA virt base: %08lx\n", pcmcia_base);
228 /* Compute clock cycles for PIO timings */
229 for (i=0; i<6; ++i) {
230 bd_t *binfo = (bd_t *)__res;
233 PCMCIA_MK_CLKS (hold_time[i],
235 ide_pio_clocks[i].setup_time =
236 PCMCIA_MK_CLKS (ide_pio_timings[i].setup_time,
238 ide_pio_clocks[i].active_time =
239 PCMCIA_MK_CLKS (ide_pio_timings[i].active_time,
241 ide_pio_clocks[i].cycle_time =
242 PCMCIA_MK_CLKS (ide_pio_timings[i].cycle_time,
245 printk ("PIO mode %d timings: %d/%d/%d => %d/%d/%d\n",
247 ide_pio_clocks[i].setup_time,
248 ide_pio_clocks[i].active_time,
249 ide_pio_clocks[i].hold_time,
250 ide_pio_clocks[i].cycle_time,
251 ide_pio_timings[i].setup_time,
252 ide_pio_timings[i].active_time,
253 ide_pio_timings[i].hold_time,
254 ide_pio_timings[i].cycle_time);
259 if (data_port >= MAX_HWIFS)
263 printk ("PCMCIA slot has not been defined! Using A as default\n");
267 #ifdef CONFIG_IDE_8xx_PCCARD
270 printk ("PIPR = 0x%08X slot %c ==> mask = 0x%X\n",
273 M8XX_PCMCIA_CD1(_slot_) | M8XX_PCMCIA_CD2(_slot_) );
276 if (pcmp->pcmc_pipr & (M8XX_PCMCIA_CD1(_slot_)|M8XX_PCMCIA_CD2(_slot_))) {
277 printk ("No card in slot %c: PIPR=%08x\n",
278 'A' + _slot_, (u32) pcmp->pcmc_pipr);
279 return; /* No card in slot */
282 check_ide_device (pcmcia_base);
284 #endif /* CONFIG_IDE_8xx_PCCARD */
286 base = pcmcia_base + ioport_dsc[data_port].base_off;
288 printk ("base: %08x + %08x = %08x\n",
289 pcmcia_base, ioport_dsc[data_port].base_off, base);
292 for (i = 0; i < IDE_NR_PORTS; ++i) {
294 printk ("port[%d]: %08x + %08x = %08x\n",
297 ioport_dsc[data_port].reg_off[i],
298 i, base + ioport_dsc[data_port].reg_off[i]);
300 *p++ = base + ioport_dsc[data_port].reg_off[i];
304 #ifdef CONFIG_IDE_8xx_PCCARD
307 *irq = ioport_dsc[data_port].irq;
309 pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcrb;
311 pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcra;
314 reg |= mk_int_int_mask (pcmcia_schlvl) << 24;
315 reg |= mk_int_int_mask (pcmcia_schlvl) << 16;
317 #else /* direct connected IDE drive, i.e. external IRQ, not the PCMCIA irq */
318 *irq = ioport_dsc[data_port].irq;
319 #endif /* CONFIG_IDE_8xx_PCCARD */
322 /* register routine to tune PIO mode */
323 ide_hwifs[data_port].tuneproc = m8xx_ide_tuneproc;
325 hw->ack_intr = (ide_ack_intr_t *) ide_interrupt_ack;
326 /* Enable Harddisk Interrupt,
327 * and make it edge sensitive
329 /* (11-18) Set edge detect for irq, no wakeup from low power mode */
330 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
331 (0x80000000 >> ioport_dsc[data_port].irq);
333 #ifdef CONFIG_IDE_8xx_PCCARD
334 /* Make sure we dont get garbage irq */
335 ((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pscr = 0xFFFF;
337 /* Enable falling edge irq */
338 pcmp->pcmc_per = 0x100000 >> (16 * _slot_);
339 #endif /* CONFIG_IDE_8xx_PCCARD */
340 } /* m8xx_ide_init_hwif_ports() using 8xx internal PCMCIA interface */
341 #endif /* CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT */
344 * m8xx_ide_init_hwif_ports for a direct IDE interface _not_ using
345 * MPC8xx's internal PCMCIA interface
347 #if defined(CONFIG_IDE_EXT_DIRECT)
348 void m8xx_ide_init_hwif_ports (hw_regs_t *hw,
349 ide_ioreg_t data_port, ide_ioreg_t ctrl_port, int *irq)
351 ide_ioreg_t *p = hw->io_ports;
356 static unsigned long ide_base = 0;
366 * - add code to read ORx, BRx
368 ide_phy_base = CFG_ATA_BASE_ADDR;
369 ide_phy_end = CFG_ATA_BASE_ADDR + 0x200;
371 printk ("IDE phys mem : %08x...%08x (size %08x)\n",
372 ide_phy_base, ide_phy_end,
373 ide_phy_end - ide_phy_base);
375 ide_base=(unsigned long)ioremap(ide_phy_base,
376 ide_phy_end-ide_phy_base);
379 printk ("IDE virt base: %08lx\n", ide_base);
383 if (data_port >= MAX_HWIFS)
386 base = ide_base + ioport_dsc[data_port].base_off;
388 printk ("base: %08x + %08x = %08x\n",
389 ide_base, ioport_dsc[data_port].base_off, base);
392 for (i = 0; i < IDE_NR_PORTS; ++i) {
394 printk ("port[%d]: %08x + %08x = %08x\n",
397 ioport_dsc[data_port].reg_off[i],
398 i, base + ioport_dsc[data_port].reg_off[i]);
400 *p++ = base + ioport_dsc[data_port].reg_off[i];
404 /* direct connected IDE drive, i.e. external IRQ */
405 *irq = ioport_dsc[data_port].irq;
408 /* register routine to tune PIO mode */
409 ide_hwifs[data_port].tuneproc = m8xx_ide_tuneproc;
411 hw->ack_intr = (ide_ack_intr_t *) ide_interrupt_ack;
412 /* Enable Harddisk Interrupt,
413 * and make it edge sensitive
415 /* (11-18) Set edge detect for irq, no wakeup from low power mode */
416 ((immap_t *) IMAP_ADDR)->im_siu_conf.sc_siel |=
417 (0x80000000 >> ioport_dsc[data_port].irq);
418 } /* m8xx_ide_init_hwif_ports() for CONFIG_IDE_8xx_DIRECT */
420 #endif /* CONFIG_IDE_8xx_DIRECT */
423 /* -------------------------------------------------------------------- */
428 #define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */
429 #define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */
430 #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */
434 /* Calculate PIO timings */
436 m8xx_ide_tuneproc(ide_drive_t *drive, u8 pio)
439 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
440 volatile pcmconf8xx_t *pcmp;
441 ulong timing, mask, reg;
444 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
447 printk("%s[%d] %s: best PIO mode: %d\n",
448 __FILE__,__LINE__,__FUNCTION__, pio);
451 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
452 pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
454 mask = ~(PCMCIA_SHT(0xFF) | PCMCIA_SST(0xFF) | PCMCIA_SL(0xFF));
456 timing = PCMCIA_SHT(hold_time[pio] )
457 | PCMCIA_SST(ide_pio_clocks[pio].setup_time )
458 | PCMCIA_SL (ide_pio_clocks[pio].active_time)
462 printk ("Setting timing bits 0x%08lx in PCMCIA controller\n", timing);
464 if ((reg = pcmp->pcmc_por0 & mask) != 0)
465 pcmp->pcmc_por0 = reg | timing;
467 if ((reg = pcmp->pcmc_por1 & mask) != 0)
468 pcmp->pcmc_por1 = reg | timing;
470 if ((reg = pcmp->pcmc_por2 & mask) != 0)
471 pcmp->pcmc_por2 = reg | timing;
473 if ((reg = pcmp->pcmc_por3 & mask) != 0)
474 pcmp->pcmc_por3 = reg | timing;
476 if ((reg = pcmp->pcmc_por4 & mask) != 0)
477 pcmp->pcmc_por4 = reg | timing;
479 if ((reg = pcmp->pcmc_por5 & mask) != 0)
480 pcmp->pcmc_por5 = reg | timing;
482 if ((reg = pcmp->pcmc_por6 & mask) != 0)
483 pcmp->pcmc_por6 = reg | timing;
485 if ((reg = pcmp->pcmc_por7 & mask) != 0)
486 pcmp->pcmc_por7 = reg | timing;
488 #elif defined(CONFIG_IDE_EXT_DIRECT)
490 printk("%s[%d] %s: not implemented yet!\n",
491 __FILE__,__LINE__,__FUNCTION__);
492 #endif /* defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_PCMCIA */
496 ide_interrupt_ack (void *dev)
498 #ifdef CONFIG_IDE_8xx_PCCARD
501 #if (PCMCIA_SOCKETS_NO == 2)
505 /* get interrupt sources */
507 pscr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr;
508 pipr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr;
511 * report only if both card detect signals are the same
513 * we depend on that CD2 is the bit to the left of CD1...
517 printk("PCMCIA slot has not been defined! Using A as default\n");
521 if(((pipr & M8XX_PCMCIA_CD2(_slot_)) >> 1) ^
522 (pipr & M8XX_PCMCIA_CD1(_slot_)) ) {
523 printk ("card detect interrupt\n");
525 /* clear the interrupt sources */
526 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr = pscr;
528 #else /* ! CONFIG_IDE_8xx_PCCARD */
530 * Only CONFIG_IDE_8xx_PCCARD is using the interrupt of the
531 * MPC8xx's PCMCIA controller, so there is nothing to be done here
532 * for CONFIG_IDE_8xx_DIRECT and CONFIG_IDE_EXT_DIRECT.
533 * The interrupt is handled somewhere else. -- Steven
535 #endif /* CONFIG_IDE_8xx_PCCARD */
543 #define CISTPL_NULL 0x00
544 #define CISTPL_DEVICE 0x01
545 #define CISTPL_LONGLINK_CB 0x02
546 #define CISTPL_INDIRECT 0x03
547 #define CISTPL_CONFIG_CB 0x04
548 #define CISTPL_CFTABLE_ENTRY_CB 0x05
549 #define CISTPL_LONGLINK_MFC 0x06
550 #define CISTPL_BAR 0x07
551 #define CISTPL_PWR_MGMNT 0x08
552 #define CISTPL_EXTDEVICE 0x09
553 #define CISTPL_CHECKSUM 0x10
554 #define CISTPL_LONGLINK_A 0x11
555 #define CISTPL_LONGLINK_C 0x12
556 #define CISTPL_LINKTARGET 0x13
557 #define CISTPL_NO_LINK 0x14
558 #define CISTPL_VERS_1 0x15
559 #define CISTPL_ALTSTR 0x16
560 #define CISTPL_DEVICE_A 0x17
561 #define CISTPL_JEDEC_C 0x18
562 #define CISTPL_JEDEC_A 0x19
563 #define CISTPL_CONFIG 0x1a
564 #define CISTPL_CFTABLE_ENTRY 0x1b
565 #define CISTPL_DEVICE_OC 0x1c
566 #define CISTPL_DEVICE_OA 0x1d
567 #define CISTPL_DEVICE_GEO 0x1e
568 #define CISTPL_DEVICE_GEO_A 0x1f
569 #define CISTPL_MANFID 0x20
570 #define CISTPL_FUNCID 0x21
571 #define CISTPL_FUNCE 0x22
572 #define CISTPL_SWIL 0x23
573 #define CISTPL_END 0xff
576 * CIS Function ID codes
578 #define CISTPL_FUNCID_MULTI 0x00
579 #define CISTPL_FUNCID_MEMORY 0x01
580 #define CISTPL_FUNCID_SERIAL 0x02
581 #define CISTPL_FUNCID_PARALLEL 0x03
582 #define CISTPL_FUNCID_FIXED 0x04
583 #define CISTPL_FUNCID_VIDEO 0x05
584 #define CISTPL_FUNCID_NETWORK 0x06
585 #define CISTPL_FUNCID_AIMS 0x07
586 #define CISTPL_FUNCID_SCSI 0x08
589 * Fixed Disk FUNCE codes
591 #define CISTPL_IDE_INTERFACE 0x01
593 #define CISTPL_FUNCE_IDE_IFACE 0x01
594 #define CISTPL_FUNCE_IDE_MASTER 0x02
595 #define CISTPL_FUNCE_IDE_SLAVE 0x03
597 /* First feature byte */
598 #define CISTPL_IDE_SILICON 0x04
599 #define CISTPL_IDE_UNIQUE 0x08
600 #define CISTPL_IDE_DUAL 0x10
602 /* Second feature byte */
603 #define CISTPL_IDE_HAS_SLEEP 0x01
604 #define CISTPL_IDE_HAS_STANDBY 0x02
605 #define CISTPL_IDE_HAS_IDLE 0x04
606 #define CISTPL_IDE_LOW_POWER 0x08
607 #define CISTPL_IDE_REG_INHIBIT 0x10
608 #define CISTPL_IDE_HAS_INDEX 0x20
609 #define CISTPL_IDE_IOIS16 0x40
612 /* -------------------------------------------------------------------- */
615 #define MAX_TUPEL_SZ 512
616 #define MAX_FEATURES 4
618 static int check_ide_device (unsigned long base)
620 volatile u8 *ident = NULL;
621 volatile u8 *feature_p[MAX_FEATURES];
622 volatile u8 *p, *start;
626 unsigned short config_base = 0;
631 printk ("PCMCIA MEM: %08lX\n", base);
633 start = p = (volatile u8 *) base;
635 while ((p - start) < MAX_TUPEL_SZ) {
639 if (code == 0xFF) { /* End of chain */
645 { volatile u8 *q = p;
646 printk ("\nTuple code %02x length %d\n\tData:",
649 for (i = 0; i < len; ++i) {
650 printk (" %02x", *q);
654 #endif /* DEBUG_PCMCIA */
663 if (n_features < MAX_FEATURES)
664 feature_p[n_features++] = p;
667 config_base = (*(p+6) << 8) + (*(p+4));
674 found = identify (ident);
676 if (func_id != ((u8)~0)) {
677 print_funcid (func_id);
679 if (func_id == CISTPL_FUNCID_FIXED)
682 return (1); /* no disk drive */
685 for (i=0; i<n_features; ++i) {
686 print_fixed (feature_p[i]);
690 printk ("unknown card type\n");
694 /* set level mode irq and I/O mapped device in config reg*/
695 *((u8 *)(base + config_base)) = 0x41;
700 /* ------------------------------------------------------------------------- */
702 static void print_funcid (int func)
705 case CISTPL_FUNCID_MULTI:
706 printk (" Multi-Function");
708 case CISTPL_FUNCID_MEMORY:
711 case CISTPL_FUNCID_SERIAL:
712 printk (" Serial Port");
714 case CISTPL_FUNCID_PARALLEL:
715 printk (" Parallel Port");
717 case CISTPL_FUNCID_FIXED:
718 printk (" Fixed Disk");
720 case CISTPL_FUNCID_VIDEO:
721 printk (" Video Adapter");
723 case CISTPL_FUNCID_NETWORK:
724 printk (" Network Adapter");
726 case CISTPL_FUNCID_AIMS:
727 printk (" AIMS Card");
729 case CISTPL_FUNCID_SCSI:
730 printk (" SCSI Adapter");
739 /* ------------------------------------------------------------------------- */
741 static void print_fixed (volatile u8 *p)
747 case CISTPL_FUNCE_IDE_IFACE:
750 printk ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
751 printk (" interface ");
754 case CISTPL_FUNCE_IDE_MASTER:
755 case CISTPL_FUNCE_IDE_SLAVE:
759 printk ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
761 if (f1 & CISTPL_IDE_UNIQUE)
762 printk (" [unique]");
764 printk ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
766 if (f2 & CISTPL_IDE_HAS_SLEEP)
769 if (f2 & CISTPL_IDE_HAS_STANDBY)
770 printk (" [standby]");
772 if (f2 & CISTPL_IDE_HAS_IDLE)
775 if (f2 & CISTPL_IDE_LOW_POWER)
776 printk (" [low power]");
778 if (f2 & CISTPL_IDE_REG_INHIBIT)
779 printk (" [reg inhibit]");
781 if (f2 & CISTPL_IDE_HAS_INDEX)
784 if (f2 & CISTPL_IDE_IOIS16)
785 printk (" [IOis16]");
793 /* ------------------------------------------------------------------------- */
796 #define MAX_IDENT_CHARS 64
797 #define MAX_IDENT_FIELDS 4
799 static u8 *known_cards[] = {
804 static int identify (volatile u8 *p)
806 u8 id_str[MAX_IDENT_CHARS];
813 return (0); /* Don't know */
818 for (i=0; i<=4 && !done; ++i, p+=2) {
819 while ((data = *p) != '\0') {
825 if (t == &id_str[MAX_IDENT_CHARS-1]) {
835 while (--t > id_str) {
841 printk ("Card ID: %s\n", id_str);
843 for (card=known_cards; *card; ++card) {
844 if (strcmp(*card, id_str) == 0) { /* found! */
849 return (0); /* don't know */
852 void m8xx_ide_init(void)
854 ppc_ide_md.default_irq = m8xx_ide_default_irq;
855 ppc_ide_md.default_io_base = m8xx_ide_default_io_base;
856 ppc_ide_md.ide_init_hwif = m8xx_ide_init_hwif_ports;