drivers/ieee1394/pcilynx.c

   1 /*
   2  * ti_pcilynx.c - Texas Instruments PCILynx driver
   3  * Copyright (C) 1999,2000 Andreas Bombe <andreas.bombe@munich.netsurf.de>,
   4  *                         Stephan Linz <linz@mazet.de>
   5  *                         Manfred Weihs <weihs@ict.tuwien.ac.at>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software Foundation,
  19  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 /*
  23  * Contributions:
  24  *
  25  * Manfred Weihs <weihs@ict.tuwien.ac.at>
  26  *        reading bus info block (containing GUID) from serial
  27  *            eeprom via i2c and storing it in config ROM
  28  *        Reworked code for initiating bus resets
  29  *            (long, short, with or without hold-off)
  30  *        Enhancements in async and iso send code
  31  */
  32
  33 #include <linux/config.h>
  34 #include <linux/kernel.h>
  35 #include <linux/slab.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/wait.h>
  38 #include <linux/errno.h>
  39 #include <linux/module.h>
  40 #include <linux/init.h>
  41 #include <linux/pci.h>
  42 #include <linux/fs.h>
  43 #include <linux/poll.h>
  44 #include <linux/irq.h>
  45 #include <asm/byteorder.h>
  46 #include <asm/atomic.h>
  47 #include <asm/io.h>
  48 #include <asm/uaccess.h>
  49
  50 #include "ieee1394.h"
  51 #include "ieee1394_types.h"
  52 #include "hosts.h"
  53 #include "ieee1394_core.h"
  54 #include "highlevel.h"
  55 #include "pcilynx.h"
  56
  57 #include <linux/i2c.h>
  58 #include <linux/i2c-algo-bit.h>
  59
  60 /* print general (card independent) information */
  61 #define PRINT_G(level, fmt, args...) printk(level "pcilynx: " fmt "\n" , ## args)
  62 /* print card specific information */
  63 #define PRINT(level, card, fmt, args...) printk(level "pcilynx%d: " fmt "\n" , card , ## args)
  64
  65 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  66 #define PRINT_GD(level, fmt, args...) printk(level "pcilynx: " fmt "\n" , ## args)
  67 #define PRINTD(level, card, fmt, args...) printk(level "pcilynx%d: " fmt "\n" , card , ## args)
  68 #else
  69 #define PRINT_GD(level, fmt, args...) do {} while (0)
  70 #define PRINTD(level, card, fmt, args...) do {} while (0)
  71 #endif
  72
  73
  74 /* Module Parameters */
  75 MODULE_PARM(skip_eeprom,"i");
  76 MODULE_PARM_DESC(skip_eeprom, "Do not try to read bus info block from serial eeprom, but user generic one (default = 0).");
  77 static int skip_eeprom = 0;
  78
  79
  80 static struct hpsb_host_driver lynx_driver;
  81 static unsigned int card_id;
  82
  83
  84
  85 /*
  86  * I2C stuff
  87  */
  88
  89 /* the i2c stuff was inspired by i2c-philips-par.c */
  90
  91 static void bit_setscl(void *data, int state)
  92 {
  93         if (state) {
  94                   ((struct ti_lynx *) data)->i2c_driven_state |= 0x00000040;
  95         } else {
  96                   ((struct ti_lynx *) data)->i2c_driven_state &= ~0x00000040;
  97         }
  98         reg_write((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL, ((struct ti_lynx *) data)->i2c_driven_state);
  99 }
 100
 101 static void bit_setsda(void *data, int state)
 102 {
 103         if (state) {
 104                   ((struct ti_lynx *) data)->i2c_driven_state |= 0x00000010;
 105         } else {
 106                   ((struct ti_lynx *) data)->i2c_driven_state &= ~0x00000010;
 107         }
 108         reg_write((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL, ((struct ti_lynx *) data)->i2c_driven_state);
 109 }
 110
 111 static int bit_getscl(void *data)
 112 {
 113         return reg_read((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL) & 0x00000040;
 114 }
 115
 116 static int bit_getsda(void *data)
 117 {
 118         return reg_read((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL) & 0x00000010;
 119 }
 120
 121 static int bit_reg(struct i2c_client *client)
 122 {
 123         return 0;
 124 }
 125
 126 static int bit_unreg(struct i2c_client *client)
 127 {
 128         return 0;
 129 }
 130
 131 static struct i2c_algo_bit_data bit_data = {
 132         .setsda                 = bit_setsda,
 133         .setscl                 = bit_setscl,
 134         .getsda                 = bit_getsda,
 135         .getscl                 = bit_getscl,
 136         .udelay                 = 5,
 137         .mdelay                 = 5,
 138         .timeout                = 100,
 139 };
 140
 141 static struct i2c_adapter bit_ops = {
 142         .id                     = 0xAA, //FIXME: probably we should get an id in i2c-id.h
 143         .client_register        = bit_reg,
 144         .client_unregister      = bit_unreg,
 145         .name                   = "PCILynx I2C",
 146 };
 147
 148
 149
 150 /*
 151  * PCL handling functions.
 152  */
 153
 154 static pcl_t alloc_pcl(struct ti_lynx *lynx)
 155 {
 156         u8 m;
 157         int i, j;
 158
 159         spin_lock(&lynx->lock);
 160         /* FIXME - use ffz() to make this readable */
 161         for (i = 0; i < (LOCALRAM_SIZE / 1024); i++) {
 162                 m = lynx->pcl_bmap[i];
 163                 for (j = 0; j < 8; j++) {
 164                         if (m & 1<<j) {
 165                                 continue;
 166                         }
 167                         m |= 1<<j;
 168                         lynx->pcl_bmap[i] = m;
 169                         spin_unlock(&lynx->lock);
 170                         return 8 * i + j;
 171                 }
 172         }
 173         spin_unlock(&lynx->lock);
 174
 175         return -1;
 176 }
 177
 178
 179 #if 0
 180 static void free_pcl(struct ti_lynx *lynx, pcl_t pclid)
 181 {
 182         int off, bit;
 183
 184         off = pclid / 8;
 185         bit = pclid % 8;
 186
 187         if (pclid < 0) {
 188                 return;
 189         }
 190
 191         spin_lock(&lynx->lock);
 192         if (lynx->pcl_bmap[off] & 1<<bit) {
 193                 lynx->pcl_bmap[off] &= ~(1<<bit);
 194         } else {
 195                 PRINT(KERN_ERR, lynx->id,
 196                       "attempted to free unallocated PCL %d", pclid);
 197         }
 198         spin_unlock(&lynx->lock);
 199 }
 200
 201 /* functions useful for debugging */
 202 static void pretty_print_pcl(const struct ti_pcl *pcl)
 203 {
 204         int i;
 205
 206         printk("PCL next %08x, userdata %08x, status %08x, remtrans %08x, nextbuf %08x\n",
 207                pcl->next, pcl->user_data, pcl->pcl_status,
 208                pcl->remaining_transfer_count, pcl->next_data_buffer);
 209
 210         printk("PCL");
 211         for (i=0; i<13; i++) {
 212                 printk(" c%x:%08x d%x:%08x",
 213                        i, pcl->buffer[i].control, i, pcl->buffer[i].pointer);
 214                 if (!(i & 0x3) && (i != 12)) printk("\nPCL");
 215         }
 216         printk("\n");
 217 }
 218
 219 static void print_pcl(const struct ti_lynx *lynx, pcl_t pclid)
 220 {
 221         struct ti_pcl pcl;
 222
 223         get_pcl(lynx, pclid, &pcl);
 224         pretty_print_pcl(&pcl);
 225 }
 226 #endif
 227
 228
 229
 230 /***********************************
 231  * IEEE-1394 functionality section *
 232  ***********************************/
 233
 234
 235 static int get_phy_reg(struct ti_lynx *lynx, int addr)
 236 {
 237         int retval;
 238         int i = 0;
 239
 240         unsigned long flags;
 241
 242         if (addr > 15) {
 243                 PRINT(KERN_ERR, lynx->id,
 244                       "%s: PHY register address %d out of range",
 245                       __FUNCTION__, addr);
 246                 return -1;
 247         }
 248
 249         spin_lock_irqsave(&lynx->phy_reg_lock, flags);
 250
 251         reg_write(lynx, LINK_PHY, LINK_PHY_READ | LINK_PHY_ADDR(addr));
 252         do {
 253                 retval = reg_read(lynx, LINK_PHY);
 254
 255                 if (i > 10000) {
 256                         PRINT(KERN_ERR, lynx->id, "%s: runaway loop, aborting",
 257                               __FUNCTION__);
 258                         retval = -1;
 259                         break;
 260                 }
 261                 i++;
 262         } while ((retval & 0xf00) != LINK_PHY_RADDR(addr));
 263
 264         reg_write(lynx, LINK_INT_STATUS, LINK_INT_PHY_REG_RCVD);
 265         spin_unlock_irqrestore(&lynx->phy_reg_lock, flags);
 266
 267         if (retval != -1) {
 268                 return retval & 0xff;
 269         } else {
 270                 return -1;
 271         }
 272 }
 273
 274 static int set_phy_reg(struct ti_lynx *lynx, int addr, int val)
 275 {
 276         unsigned long flags;
 277
 278         if (addr > 15) {
 279                 PRINT(KERN_ERR, lynx->id,
 280                       "%s: PHY register address %d out of range", __FUNCTION__, addr);
 281                 return -1;
 282         }
 283
 284         if (val > 0xff) {
 285                 PRINT(KERN_ERR, lynx->id,
 286                       "%s: PHY register value %d out of range", __FUNCTION__, val);
 287                 return -1;
 288         }
 289
 290         spin_lock_irqsave(&lynx->phy_reg_lock, flags);
 291
 292         reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | LINK_PHY_ADDR(addr)
 293                   | LINK_PHY_WDATA(val));
 294
 295         spin_unlock_irqrestore(&lynx->phy_reg_lock, flags);
 296
 297         return 0;
 298 }
 299
 300 static int sel_phy_reg_page(struct ti_lynx *lynx, int page)
 301 {
 302         int reg;
 303
 304         if (page > 7) {
 305                 PRINT(KERN_ERR, lynx->id,
 306                       "%s: PHY page %d out of range", __FUNCTION__, page);
 307                 return -1;
 308         }
 309
 310         reg = get_phy_reg(lynx, 7);
 311         if (reg != -1) {
 312                 reg &= 0x1f;
 313                 reg |= (page << 5);
 314                 set_phy_reg(lynx, 7, reg);
 315                 return 0;
 316         } else {
 317                 return -1;
 318         }
 319 }
 320
 321 #if 0 /* not needed at this time */
 322 static int sel_phy_reg_port(struct ti_lynx *lynx, int port)
 323 {
 324         int reg;
 325
 326         if (port > 15) {
 327                 PRINT(KERN_ERR, lynx->id,
 328                       "%s: PHY port %d out of range", __FUNCTION__, port);
 329                 return -1;
 330         }
 331
 332         reg = get_phy_reg(lynx, 7);
 333         if (reg != -1) {
 334                 reg &= 0xf0;
 335                 reg |= port;
 336                 set_phy_reg(lynx, 7, reg);
 337                 return 0;
 338         } else {
 339                 return -1;
 340         }
 341 }
 342 #endif
 343
 344 static u32 get_phy_vendorid(struct ti_lynx *lynx)
 345 {
 346         u32 pvid = 0;
 347         sel_phy_reg_page(lynx, 1);
 348         pvid |= (get_phy_reg(lynx, 10) << 16);
 349         pvid |= (get_phy_reg(lynx, 11) << 8);
 350         pvid |= get_phy_reg(lynx, 12);
 351         PRINT(KERN_INFO, lynx->id, "PHY vendor id 0x%06x", pvid);
 352         return pvid;
 353 }
 354
 355 static u32 get_phy_productid(struct ti_lynx *lynx)
 356 {
 357         u32 id = 0;
 358         sel_phy_reg_page(lynx, 1);
 359         id |= (get_phy_reg(lynx, 13) << 16);
 360         id |= (get_phy_reg(lynx, 14) << 8);
 361         id |= get_phy_reg(lynx, 15);
 362         PRINT(KERN_INFO, lynx->id, "PHY product id 0x%06x", id);
 363         return id;
 364 }
 365
 366 static quadlet_t generate_own_selfid(struct ti_lynx *lynx,
 367                                      struct hpsb_host *host)
 368 {
 369         quadlet_t lsid;
 370         char phyreg[7];
 371         int i;
 372
 373         phyreg[0] = lynx->phy_reg0;
 374         for (i = 1; i < 7; i++) {
 375                 phyreg[i] = get_phy_reg(lynx, i);
 376         }
 377
 378         /* FIXME? We assume a TSB21LV03A phy here.  This code doesn't support
 379            more than 3 ports on the PHY anyway. */
 380
 381         lsid = 0x80400000 | ((phyreg[0] & 0xfc) << 22);
 382         lsid |= (phyreg[1] & 0x3f) << 16; /* gap count */
 383         lsid |= (phyreg[2] & 0xc0) << 8; /* max speed */
 384         lsid |= (phyreg[6] & 0x01) << 11; /* contender (phy dependent) */
 385         /* lsid |= 1 << 11; *//* set contender (hack) */
 386         lsid |= (phyreg[6] & 0x10) >> 3; /* initiated reset */
 387
 388         for (i = 0; i < (phyreg[2] & 0xf); i++) { /* ports */
 389                 if (phyreg[3 + i] & 0x4) {
 390                         lsid |= (((phyreg[3 + i] & 0x8) | 0x10) >> 3)
 391                                 << (6 - i*2);
 392                 } else {
 393                         lsid |= 1 << (6 - i*2);
 394                 }
 395         }
 396
 397         cpu_to_be32s(&lsid);
 398         PRINT(KERN_DEBUG, lynx->id, "generated own selfid 0x%x", lsid);
 399         return lsid;
 400 }
 401
 402 static void handle_selfid(struct ti_lynx *lynx, struct hpsb_host *host)
 403 {
 404         quadlet_t *q = lynx->rcv_page;
 405         int phyid, isroot, size;
 406         quadlet_t lsid = 0;
 407         int i;
 408
 409         if (lynx->phy_reg0 == -1 || lynx->selfid_size == -1) return;
 410
 411         size = lynx->selfid_size;
 412         phyid = lynx->phy_reg0;
 413
 414         i = (size > 16 ? 16 : size) / 4 - 1;
 415         while (i >= 0) {
 416                 cpu_to_be32s(&q[i]);
 417                 i--;
 418         }
 419
 420         if (!lynx->phyic.reg_1394a) {
 421                 lsid = generate_own_selfid(lynx, host);
 422         }
 423
 424         isroot = (phyid & 2) != 0;
 425         phyid >>= 2;
 426         PRINT(KERN_INFO, lynx->id, "SelfID process finished (phyid %d, %s)",
 427               phyid, (isroot ? "root" : "not root"));
 428         reg_write(lynx, LINK_ID, (0xffc0 | phyid) << 16);
 429
 430         if (!lynx->phyic.reg_1394a && !size) {
 431                 hpsb_selfid_received(host, lsid);
 432         }
 433
 434         while (size > 0) {
 435                 struct selfid *sid = (struct selfid *)q;
 436
 437                 if (!lynx->phyic.reg_1394a && !sid->extended
 438                     && (sid->phy_id == (phyid + 1))) {
 439                         hpsb_selfid_received(host, lsid);
 440                 }
 441
 442                 if (q[0] == ~q[1]) {
 443                         PRINT(KERN_DEBUG, lynx->id, "SelfID packet 0x%x rcvd",
 444                               q[0]);
 445                         hpsb_selfid_received(host, q[0]);
 446                 } else {
 447                         PRINT(KERN_INFO, lynx->id,
 448                               "inconsistent selfid 0x%x/0x%x", q[0], q[1]);
 449                 }
 450                 q += 2;
 451                 size -= 8;
 452         }
 453
 454         if (!lynx->phyic.reg_1394a && isroot && phyid != 0) {
 455                 hpsb_selfid_received(host, lsid);
 456         }
 457
 458         hpsb_selfid_complete(host, phyid, isroot);
 459
 460         if (host->in_bus_reset) return; /* in bus reset again */
 461
 462         if (isroot) reg_set_bits(lynx, LINK_CONTROL, LINK_CONTROL_CYCMASTER); //FIXME: I do not think, we need this here
 463         reg_set_bits(lynx, LINK_CONTROL,
 464                      LINK_CONTROL_RCV_CMP_VALID | LINK_CONTROL_TX_ASYNC_EN
 465                      | LINK_CONTROL_RX_ASYNC_EN | LINK_CONTROL_CYCTIMEREN);
 466 }
 467
 468
 469
 470 /* This must be called with the respective queue_lock held. */
 471 static void send_next(struct ti_lynx *lynx, int what)
 472 {
 473         struct ti_pcl pcl;
 474         struct lynx_send_data *d;
 475         struct hpsb_packet *packet;
 476
 477         d = (what == hpsb_iso ? &lynx->iso_send : &lynx->async);
 478         if (!list_empty(&d->pcl_queue)) {
 479                 PRINT(KERN_ERR, lynx->id, "trying to queue a new packet in nonempty fifo");
 480                 BUG();
 481         }
 482
 483         packet = driver_packet(d->queue.next);
 484         list_del(&packet->driver_list);
 485         list_add_tail(&packet->driver_list, &d->pcl_queue);
 486
 487         d->header_dma = pci_map_single(lynx->dev, packet->header,
 488                                        packet->header_size, PCI_DMA_TODEVICE);
 489         if (packet->data_size) {
 490                 d->data_dma = pci_map_single(lynx->dev, packet->data,
 491                                              packet->data_size,
 492                                              PCI_DMA_TODEVICE);
 493         } else {
 494                 d->data_dma = 0;
 495         }
 496
 497         pcl.next = PCL_NEXT_INVALID;
 498         pcl.async_error_next = PCL_NEXT_INVALID;
 499         pcl.pcl_status = 0;
 500 #ifdef __BIG_ENDIAN
 501         pcl.buffer[0].control = packet->speed_code << 14 | packet->header_size;
 502 #else
 503         pcl.buffer[0].control = packet->speed_code << 14 | packet->header_size
 504                 | PCL_BIGENDIAN;
 505 #endif
 506         pcl.buffer[0].pointer = d->header_dma;
 507         pcl.buffer[1].control = PCL_LAST_BUFF | packet->data_size;
 508         pcl.buffer[1].pointer = d->data_dma;
 509
 510         switch (packet->type) {
 511         case hpsb_async:
 512                 pcl.buffer[0].control |= PCL_CMD_XMT;
 513                 break;
 514         case hpsb_iso:
 515                 pcl.buffer[0].control |= PCL_CMD_XMT | PCL_ISOMODE;
 516                 break;
 517         case hpsb_raw:
 518                 pcl.buffer[0].control |= PCL_CMD_UNFXMT;
 519                 break;
 520         }
 521
 522         if (!packet->data_be) {
 523                 pcl.buffer[1].control |= PCL_BIGENDIAN;
 524         }
 525
 526         put_pcl(lynx, d->pcl, &pcl);
 527         run_pcl(lynx, d->pcl_start, d->channel);
 528 }
 529
 530
 531 /* called from subsystem core */
 532 static int lynx_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
 533 {
 534         struct ti_lynx *lynx = host->hostdata;
 535         struct lynx_send_data *d;
 536         unsigned long flags;
 537
 538         if (packet->data_size >= 4096) {
 539                 PRINT(KERN_ERR, lynx->id, "transmit packet data too big (%Zd)",
 540                       packet->data_size);
 541                 return 0;
 542         }
 543
 544         switch (packet->type) {
 545         case hpsb_async:
 546         case hpsb_raw:
 547                 d = &lynx->async;
 548                 break;
 549         case hpsb_iso:
 550                 d = &lynx->iso_send;
 551                 break;
 552         default:
 553                 PRINT(KERN_ERR, lynx->id, "invalid packet type %d",
 554                       packet->type);
 555                 return 0;
 556         }
 557
 558         if (packet->tcode == TCODE_WRITEQ
 559             || packet->tcode == TCODE_READQ_RESPONSE) {
 560                 cpu_to_be32s(&packet->header[3]);
 561         }
 562
 563         spin_lock_irqsave(&d->queue_lock, flags);
 564
 565         list_add_tail(&packet->driver_list, &d->queue);
 566         if (list_empty(&d->pcl_queue))
 567                 send_next(lynx, packet->type);
 568
 569         spin_unlock_irqrestore(&d->queue_lock, flags);
 570
 571         return 1;
 572 }
 573
 574
 575 /* called from subsystem core */
 576 static int lynx_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
 577 {
 578         struct ti_lynx *lynx = host->hostdata;
 579         int retval = 0;
 580         struct hpsb_packet *packet;
 581         LIST_HEAD(packet_list);
 582         unsigned long flags;
 583         int phy_reg;
 584
 585         switch (cmd) {
 586         case RESET_BUS:
 587                 if (reg_read(lynx, LINK_INT_STATUS) & LINK_INT_PHY_BUSRESET) {
 588                         retval = 0;
 589                         break;
 590                 }
 591
 592                 switch (arg) {
 593                 case SHORT_RESET:
 594                         if (lynx->phyic.reg_1394a) {
 595                                 phy_reg = get_phy_reg(lynx, 5);
 596                                 if (phy_reg == -1) {
 597                                         PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
 598                                         retval = -1;
 599                                         break;
 600                                 }
 601                                 phy_reg |= 0x40;
 602
 603                                 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset) on request");
 604
 605                                 lynx->selfid_size = -1;
 606                                 lynx->phy_reg0 = -1;
 607                                 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
 608                                 break;
 609                         } else {
 610                                 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
 611                                 /* fall through to long bus reset */
 612                         }
 613                 case LONG_RESET:
 614                         phy_reg = get_phy_reg(lynx, 1);
 615                         if (phy_reg == -1) {
 616                                 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
 617                                 retval = -1;
 618                                 break;
 619                         }
 620                         phy_reg |= 0x40;
 621
 622                         PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset) on request");
 623
 624                         lynx->selfid_size = -1;
 625                         lynx->phy_reg0 = -1;
 626                         set_phy_reg(lynx, 1, phy_reg); /* clear RHB, set IBR */
 627                         break;
 628                 case SHORT_RESET_NO_FORCE_ROOT:
 629                         if (lynx->phyic.reg_1394a) {
 630                                 phy_reg = get_phy_reg(lynx, 1);
 631                                 if (phy_reg == -1) {
 632                                         PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
 633                                         retval = -1;
 634                                         break;
 635                                 }
 636                                 if (phy_reg & 0x80) {
 637                                         phy_reg &= ~0x80;
 638                                         set_phy_reg(lynx, 1, phy_reg); /* clear RHB */
 639                                 }
 640
 641                                 phy_reg = get_phy_reg(lynx, 5);
 642                                 if (phy_reg == -1) {
 643                                         PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
 644                                         retval = -1;
 645                                         break;
 646                                 }
 647                                 phy_reg |= 0x40;
 648
 649                                 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset, no force_root) on request");
 650
 651                                 lynx->selfid_size = -1;
 652                                 lynx->phy_reg0 = -1;
 653                                 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
 654                                 break;
 655                         } else {
 656                                 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
 657                                 /* fall through to long bus reset */
 658                         }
 659                 case LONG_RESET_NO_FORCE_ROOT:
 660                         phy_reg = get_phy_reg(lynx, 1);
 661                         if (phy_reg == -1) {
 662                                 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
 663                                 retval = -1;
 664                                 break;
 665                         }
 666                         phy_reg &= ~0x80;
 667                         phy_reg |= 0x40;
 668
 669                         PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset, no force_root) on request");
 670
 671                         lynx->selfid_size = -1;
 672                         lynx->phy_reg0 = -1;
 673                         set_phy_reg(lynx, 1, phy_reg); /* clear RHB, set IBR */
 674                         break;
 675                 case SHORT_RESET_FORCE_ROOT:
 676                         if (lynx->phyic.reg_1394a) {
 677                                 phy_reg = get_phy_reg(lynx, 1);
 678                                 if (phy_reg == -1) {
 679                                         PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
 680                                         retval = -1;
 681                                         break;
 682                                 }
 683                                 if (!(phy_reg & 0x80)) {
 684                                         phy_reg |= 0x80;
 685                                         set_phy_reg(lynx, 1, phy_reg); /* set RHB */
 686                                 }
 687
 688                                 phy_reg = get_phy_reg(lynx, 5);
 689                                 if (phy_reg == -1) {
 690                                         PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
 691                                         retval = -1;
 692                                         break;
 693                                 }
 694                                 phy_reg |= 0x40;
 695
 696                                 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset, force_root set) on request");
 697
 698                                 lynx->selfid_size = -1;
 699                                 lynx->phy_reg0 = -1;
 700                                 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
 701                                 break;
 702                         } else {
 703                                 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
 704                                 /* fall through to long bus reset */
 705                         }
 706                 case LONG_RESET_FORCE_ROOT:
 707                         phy_reg = get_phy_reg(lynx, 1);
 708                         if (phy_reg == -1) {
 709                                 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
 710                                 retval = -1;
 711                                 break;
 712                         }
 713                         phy_reg |= 0xc0;
 714
 715                         PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset, force_root set) on request");
 716
 717                         lynx->selfid_size = -1;
 718                         lynx->phy_reg0 = -1;
 719                         set_phy_reg(lynx, 1, phy_reg); /* set IBR and RHB */
 720                         break;
 721                 default:
 722                         PRINT(KERN_ERR, lynx->id, "unknown argument for reset_bus command %d", arg);
 723                         retval = -1;
 724                 }
 725
 726                 break;
 727
 728         case GET_CYCLE_COUNTER:
 729                 retval = reg_read(lynx, CYCLE_TIMER);
 730                 break;
 731
 732         case SET_CYCLE_COUNTER:
 733                 reg_write(lynx, CYCLE_TIMER, arg);
 734                 break;
 735
 736         case SET_BUS_ID:
 737                 reg_write(lynx, LINK_ID,
 738                           (arg << 22) | (reg_read(lynx, LINK_ID) & 0x003f0000));
 739                 break;
 740
 741         case ACT_CYCLE_MASTER:
 742                 if (arg) {
 743                         reg_set_bits(lynx, LINK_CONTROL,
 744                                      LINK_CONTROL_CYCMASTER);
 745                 } else {
 746                         reg_clear_bits(lynx, LINK_CONTROL,
 747                                        LINK_CONTROL_CYCMASTER);
 748                 }
 749                 break;
 750
 751         case CANCEL_REQUESTS:
 752                 spin_lock_irqsave(&lynx->async.queue_lock, flags);
 753
 754                 reg_write(lynx, DMA_CHAN_CTRL(CHANNEL_ASYNC_SEND), 0);
 755                 list_splice(&lynx->async.queue, &packet_list);
 756                 INIT_LIST_HEAD(&lynx->async.queue);
 757
 758                 if (list_empty(&lynx->async.pcl_queue)) {
 759                         spin_unlock_irqrestore(&lynx->async.queue_lock, flags);
 760                         PRINTD(KERN_DEBUG, lynx->id, "no async packet in PCL to cancel");
 761                 } else {
 762                         struct ti_pcl pcl;
 763                         u32 ack;
 764                         struct hpsb_packet *packet;
 765
 766                         PRINT(KERN_INFO, lynx->id, "cancelling async packet, that was already in PCL");
 767
 768                         get_pcl(lynx, lynx->async.pcl, &pcl);
 769
 770                         packet = driver_packet(lynx->async.pcl_queue.next);
 771                         list_del(&packet->driver_list);
 772
 773                         pci_unmap_single(lynx->dev, lynx->async.header_dma,
 774                                          packet->header_size, PCI_DMA_TODEVICE);
 775                         if (packet->data_size) {
 776                                 pci_unmap_single(lynx->dev, lynx->async.data_dma,
 777                                                  packet->data_size, PCI_DMA_TODEVICE);
 778                         }
 779
 780                         spin_unlock_irqrestore(&lynx->async.queue_lock, flags);
 781
 782                         if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
 783                                 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
 784                                         ack = (pcl.pcl_status >> 15) & 0xf;
 785                                         PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
 786                                         ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
 787                                 } else {
 788                                         ack = (pcl.pcl_status >> 15) & 0xf;
 789                                 }
 790                         } else {
 791                                 PRINT(KERN_INFO, lynx->id, "async packet was not completed");
 792                                 ack = ACKX_ABORTED;
 793                         }
 794                         hpsb_packet_sent(host, packet, ack);
 795                 }
 796
 797                 while (!list_empty(&packet_list)) {
 798                         packet = driver_packet(packet_list.next);
 799                         list_del(&packet->driver_list);
 800                         hpsb_packet_sent(host, packet, ACKX_ABORTED);
 801                 }
 802
 803                 break;
 804
 805         case MODIFY_USAGE:
 806                 if (arg) {
 807                         MOD_INC_USE_COUNT;
 808                 } else {
 809                         MOD_DEC_USE_COUNT;
 810                 }
 811
 812                 retval = 1;
 813                 break;
 814
 815         case ISO_LISTEN_CHANNEL:
 816                 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
 817
 818                 if (lynx->iso_rcv.chan_count++ == 0) {
 819                         reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
 820                                   DMA_WORD1_CMP_ENABLE_MASTER);
 821                 }
 822
 823                 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
 824                 break;
 825
 826         case ISO_UNLISTEN_CHANNEL:
 827                 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
 828
 829                 if (--lynx->iso_rcv.chan_count == 0) {
 830                         reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
 831                                   0);
 832                 }
 833
 834                 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
 835                 break;
 836
 837         default:
 838                 PRINT(KERN_ERR, lynx->id, "unknown devctl command %d", cmd);
 839                 retval = -1;
 840         }
 841
 842         return retval;
 843 }
 844
 845
 846 /***************************************
 847  * IEEE-1394 functionality section END *
 848  ***************************************/
 849
 850 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
 851 /* VFS functions for local bus / aux device access.  Access to those
 852  * is implemented as a character device instead of block devices
 853  * because buffers are not wanted for this.  Therefore llseek (from
 854  * VFS) can be used for these char devices with obvious effects.
 855  */
 856 static int mem_open(struct inode*, struct file*);
 857 static int mem_release(struct inode*, struct file*);
 858 static unsigned int aux_poll(struct file*, struct poll_table_struct*);
 859 static loff_t mem_llseek(struct file*, loff_t, int);
 860 static ssize_t mem_read (struct file*, char*, size_t, loff_t*);
 861 static ssize_t mem_write(struct file*, const char*, size_t, loff_t*);
 862
 863
 864 static struct file_operations aux_ops = {
 865         .owner =        THIS_MODULE,
 866         .read =         mem_read,
 867         .write =        mem_write,
 868         .poll =         aux_poll,
 869         .llseek =       mem_llseek,
 870         .open =         mem_open,
 871         .release =      mem_release,
 872 };
 873
 874
 875 static void aux_setup_pcls(struct ti_lynx *lynx)
 876 {
 877         struct ti_pcl pcl;
 878
 879         pcl.next = PCL_NEXT_INVALID;
 880         pcl.user_data = pcl_bus(lynx, lynx->dmem_pcl);
 881         put_pcl(lynx, lynx->dmem_pcl, &pcl);
 882 }
 883
 884 static int mem_open(struct inode *inode, struct file *file)
 885 {
 886         int cid = MINOR(inode->i_rdev);
 887         enum { t_rom, t_aux, t_ram } type;
 888         struct memdata *md;
 889
 890         if (cid < PCILYNX_MINOR_AUX_START) {
 891                 /* just for completeness */
 892                 return -ENXIO;
 893         } else if (cid < PCILYNX_MINOR_ROM_START) {
 894                 cid -= PCILYNX_MINOR_AUX_START;
 895                 if (cid >= num_of_cards || !cards[cid].aux_port)
 896                         return -ENXIO;
 897                 type = t_aux;
 898         } else if (cid < PCILYNX_MINOR_RAM_START) {
 899                 cid -= PCILYNX_MINOR_ROM_START;
 900                 if (cid >= num_of_cards || !cards[cid].local_rom)
 901                         return -ENXIO;
 902                 type = t_rom;
 903         } else {
 904                 /* WARNING: Know what you are doing when opening RAM.
 905                  * It is currently used inside the driver! */
 906                 cid -= PCILYNX_MINOR_RAM_START;
 907                 if (cid >= num_of_cards || !cards[cid].local_ram)
 908                         return -ENXIO;
 909                 type = t_ram;
 910         }
 911
 912         md = (struct memdata *)kmalloc(sizeof(struct memdata), SLAB_KERNEL);
 913         if (md == NULL)
 914                 return -ENOMEM;
 915
 916         md->lynx = &cards[cid];
 917         md->cid = cid;
 918
 919         switch (type) {
 920         case t_rom:
 921                 md->type = rom;
 922                 break;
 923         case t_ram:
 924                 md->type = ram;
 925                 break;
 926         case t_aux:
 927                 atomic_set(&md->aux_intr_last_seen,
 928                            atomic_read(&cards[cid].aux_intr_seen));
 929                 md->type = aux;
 930                 break;
 931         }
 932
 933         file->private_data = md;
 934
 935         return 0;
 936 }
 937
 938 static int mem_release(struct inode *inode, struct file *file)
 939 {
 940         kfree(file->private_data);
 941         return 0;
 942 }
 943
 944 static unsigned int aux_poll(struct file *file, poll_table *pt)
 945 {
 946         struct memdata *md = (struct memdata *)file->private_data;
 947         int cid = md->cid;
 948         unsigned int mask;
 949
 950         /* reading and writing is always allowed */
 951         mask = POLLIN | POLLRDNORM | POLLOUT | POLLWRNORM;
 952
 953         if (md->type == aux) {
 954                 poll_wait(file, &cards[cid].aux_intr_wait, pt);
 955
 956                 if (atomic_read(&md->aux_intr_last_seen)
 957                     != atomic_read(&cards[cid].aux_intr_seen)) {
 958                         mask |= POLLPRI;
 959                         atomic_inc(&md->aux_intr_last_seen);
 960                 }
 961         }
 962
 963         return mask;
 964 }
 965
 966 loff_t mem_llseek(struct file *file, loff_t offs, int orig)
 967 {
 968         loff_t newoffs;
 969
 970         switch (orig) {
 971         case 0:
 972                 newoffs = offs;
 973                 break;
 974         case 1:
 975                 newoffs = offs + file->f_pos;
 976                 break;
 977         case 2:
 978                 newoffs = PCILYNX_MAX_MEMORY + 1 + offs;
 979                 break;
 980         default:
 981                 return -EINVAL;
 982         }
 983
 984         if (newoffs < 0 || newoffs > PCILYNX_MAX_MEMORY + 1) return -EINVAL;
 985
 986         file->f_pos = newoffs;
 987         return newoffs;
 988 }
 989
 990 /*
 991  * do not DMA if count is too small because this will have a serious impact
 992  * on performance - the value 2400 was found by experiment and may not work
 993  * everywhere as good as here - use mem_mindma option for modules to change
 994  */
 995 short mem_mindma = 2400;
 996 MODULE_PARM(mem_mindma, "h");
 997
 998 static ssize_t mem_dmaread(struct memdata *md, u32 physbuf, ssize_t count,
 999                            int offset)
1000 {
1001         pcltmp_t pcltmp;
1002         struct ti_pcl *pcl;
1003         size_t retval;
1004         int i;
1005         DECLARE_WAITQUEUE(wait, current);
1006
1007         count &= ~3;
1008         count = min(count, 53196);
1009         retval = count;
1010
1011         if (reg_read(md->lynx, DMA_CHAN_CTRL(CHANNEL_LOCALBUS))
1012             & DMA_CHAN_CTRL_BUSY) {
1013                 PRINT(KERN_WARNING, md->lynx->id, "DMA ALREADY ACTIVE!");
1014         }
1015
1016         reg_write(md->lynx, LBUS_ADDR, md->type | offset);
1017
1018         pcl = edit_pcl(md->lynx, md->lynx->dmem_pcl, &pcltmp);
1019         pcl->buffer[0].control = PCL_CMD_LBUS_TO_PCI | min(count, 4092);
1020         pcl->buffer[0].pointer = physbuf;
1021         count -= 4092;
1022
1023         i = 0;
1024         while (count > 0) {
1025                 i++;
1026                 pcl->buffer[i].control = min(count, 4092);
1027                 pcl->buffer[i].pointer = physbuf + i * 4092;
1028                 count -= 4092;
1029         }
1030         pcl->buffer[i].control |= PCL_LAST_BUFF;
1031         commit_pcl(md->lynx, md->lynx->dmem_pcl, &pcltmp);
1032
1033         set_current_state(TASK_INTERRUPTIBLE);
1034         add_wait_queue(&md->lynx->mem_dma_intr_wait, &wait);
1035         run_sub_pcl(md->lynx, md->lynx->dmem_pcl, 2, CHANNEL_LOCALBUS);
1036
1037         schedule();
1038         while (reg_read(md->lynx, DMA_CHAN_CTRL(CHANNEL_LOCALBUS))
1039                & DMA_CHAN_CTRL_BUSY) {
1040                 if (signal_pending(current)) {
1041                         retval = -EINTR;
1042                         break;
1043                 }
1044                 schedule();
1045         }
1046
1047         reg_write(md->lynx, DMA_CHAN_CTRL(CHANNEL_LOCALBUS), 0);
1048         remove_wait_queue(&md->lynx->mem_dma_intr_wait, &wait);
1049
1050         if (reg_read(md->lynx, DMA_CHAN_CTRL(CHANNEL_LOCALBUS))
1051             & DMA_CHAN_CTRL_BUSY) {
1052                 PRINT(KERN_ERR, md->lynx->id, "DMA STILL ACTIVE!");
1053         }
1054
1055         return retval;
1056 }
1057
1058 static ssize_t mem_read(struct file *file, char *buffer, size_t count,
1059                         loff_t *offset)
1060 {
1061         struct memdata *md = (struct memdata *)file->private_data;
1062         ssize_t bcount;
1063         size_t alignfix;
1064         loff_t off = *offset; /* avoid useless 64bit-arithmetic */
1065         ssize_t retval;
1066         void *membase;
1067
1068         if (!count)
1069                 return 0;
1070         if (off < 0)
1071                 return -EINVAL;
1072         if (off > PCILYNX_MAX_MEMORY)
1073                 return -ENOSPC;
1074
1075         if (count > PCILYNX_MAX_MEMORY + 1 - off)
1076                 count = PCILYNX_MAX_MEMORY + 1 - off;
1077
1078         switch (md->type) {
1079         case rom:
1080                 membase = md->lynx->local_rom;
1081                 break;
1082         case ram:
1083                 membase = md->lynx->local_ram;
1084                 break;
1085         case aux:
1086                 membase = md->lynx->aux_port;
1087                 break;
1088         default:
1089                 panic("pcilynx%d: unsupported md->type %d in %s",
1090                       md->lynx->id, md->type, __FUNCTION__);
1091         }
1092
1093         down(&md->lynx->mem_dma_mutex);
1094
1095         if (count < mem_mindma) {
1096                 memcpy_fromio(md->lynx->mem_dma_buffer, membase+off, count);
1097                 off += count;
1098                 goto out;
1099         }
1100
1101         bcount = count;
1102         alignfix = 4 - (off % 4);
1103         if (alignfix != 4) {
1104                 if (bcount < alignfix) {
1105                         alignfix = bcount;
1106                 }
1107                 memcpy_fromio(md->lynx->mem_dma_buffer, membase+off,
1108                               alignfix);
1109                 if (bcount == alignfix) {
1110                         goto out;
1111                 }
1112                 bcount -= alignfix;
1113                 off += alignfix;
1114         }
1115
1116         while (bcount >= 4) {
1117                 retval = mem_dmaread(md, md->lynx->mem_dma_buffer_dma
1118                                      + count - bcount, bcount, off);
1119                 if (retval < 0) return retval;
1120
1121                 bcount -= retval;
1122                 off += retval;
1123         }
1124
1125         if (bcount) {
1126                 memcpy_fromio(md->lynx->mem_dma_buffer + count - bcount,
1127                               membase+off, bcount);
1128                 off += bcount;
1129         }
1130
1131  out:
1132         retval = copy_to_user(buffer, md->lynx->mem_dma_buffer, count);
1133         up(&md->lynx->mem_dma_mutex);
1134
1135         if (retval) return -EFAULT;
1136         *offset = off;
1137         return count;
1138 }
1139
1140
1141 static ssize_t mem_write(struct file *file, const char *buffer, size_t count,
1142                          loff_t *offset)
1143 {
1144         struct memdata *md = (struct memdata *)file->private_data;
1145         loff_t off = *offset;
1146
1147         if (!count)
1148                 return 0;
1149         if (off < 0)
1150                 return -EINVAL;
1151         if (off > PCILYNX_MAX_MEMORY)
1152                 return -ENOSPC;
1153
1154         if (count > PCILYNX_MAX_MEMORY + 1 - off)
1155                 count = PCILYNX_MAX_MEMORY + 1 - off;
1156
1157         /* FIXME: dereferencing pointers to PCI mem doesn't work everywhere */
1158         switch (md->type) {
1159         case aux:
1160                 if (copy_from_user(md->lynx->aux_port+off, buffer, count))
1161                         return -EFAULT;
1162                 break;
1163         case ram:
1164                 if (copy_from_user(md->lynx->local_ram+off, buffer, count))
1165                         return -EFAULT;
1166                 break;
1167         case rom:
1168                 /* the ROM may be writeable */
1169                 if (copy_from_user(md->lynx->local_rom+off, buffer, count))
1170                         return -EFAULT;
1171                 break;
1172         }
1173
1174         *offset = off + count;
1175         return count;
1176 }
1177 #endif /* CONFIG_IEEE1394_PCILYNX_PORTS */
1178
1179
1180 /********************************************************
1181  * Global stuff (interrupt handler, init/shutdown code) *
1182  ********************************************************/
1183
1184
1185 static void lynx_irq_handler(int irq, void *dev_id,
1186                              struct pt_regs *regs_are_unused)
1187 {
1188         struct ti_lynx *lynx = (struct ti_lynx *)dev_id;
1189         struct hpsb_host *host = lynx->host;
1190         u32 intmask;
1191         u32 linkint;
1192
1193         linkint = reg_read(lynx, LINK_INT_STATUS);
1194         intmask = reg_read(lynx, PCI_INT_STATUS);
1195
1196         if (!(intmask & PCI_INT_INT_PEND)) return;
1197
1198         PRINTD(KERN_DEBUG, lynx->id, "interrupt: 0x%08x / 0x%08x", intmask,
1199                linkint);
1200
1201         reg_write(lynx, LINK_INT_STATUS, linkint);
1202         reg_write(lynx, PCI_INT_STATUS, intmask);
1203
1204 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
1205         if (intmask & PCI_INT_AUX_INT) {
1206                 atomic_inc(&lynx->aux_intr_seen);
1207                 wake_up_interruptible(&lynx->aux_intr_wait);
1208         }
1209
1210         if (intmask & PCI_INT_DMA_HLT(CHANNEL_LOCALBUS)) {
1211                 wake_up_interruptible(&lynx->mem_dma_intr_wait);
1212         }
1213 #endif
1214
1215
1216         if (intmask & PCI_INT_1394) {
1217                 if (linkint & LINK_INT_PHY_TIMEOUT) {
1218                         PRINT(KERN_INFO, lynx->id, "PHY timeout occurred");
1219                 }
1220                 if (linkint & LINK_INT_PHY_BUSRESET) {
1221                         PRINT(KERN_INFO, lynx->id, "bus reset interrupt");
1222                         lynx->selfid_size = -1;
1223                         lynx->phy_reg0 = -1;
1224                         if (!host->in_bus_reset)
1225                                 hpsb_bus_reset(host);
1226                 }
1227                 if (linkint & LINK_INT_PHY_REG_RCVD) {
1228                         u32 reg;
1229
1230                         spin_lock(&lynx->phy_reg_lock);
1231                         reg = reg_read(lynx, LINK_PHY);
1232                         spin_unlock(&lynx->phy_reg_lock);
1233
1234                         if (!host->in_bus_reset) {
1235                                 PRINT(KERN_INFO, lynx->id,
1236                                       "phy reg received without reset");
1237                         } else if (reg & 0xf00) {
1238                                 PRINT(KERN_INFO, lynx->id,
1239                                       "unsolicited phy reg %d received",
1240                                       (reg >> 8) & 0xf);
1241                         } else {
1242                                 lynx->phy_reg0 = reg & 0xff;
1243                                 handle_selfid(lynx, host);
1244                         }
1245                 }
1246                 if (linkint & LINK_INT_ISO_STUCK) {
1247                         PRINT(KERN_INFO, lynx->id, "isochronous transmitter stuck");
1248                 }
1249                 if (linkint & LINK_INT_ASYNC_STUCK) {
1250                         PRINT(KERN_INFO, lynx->id, "asynchronous transmitter stuck");
1251                 }
1252                 if (linkint & LINK_INT_SENT_REJECT) {
1253                         PRINT(KERN_INFO, lynx->id, "sent reject");
1254                 }
1255                 if (linkint & LINK_INT_TX_INVALID_TC) {
1256                         PRINT(KERN_INFO, lynx->id, "invalid transaction code");
1257                 }
1258                 if (linkint & LINK_INT_GRF_OVERFLOW) {
1259                         /* flush FIFO if overflow happens during reset */
1260                         if (host->in_bus_reset)
1261                                 reg_write(lynx, FIFO_CONTROL,
1262                                           FIFO_CONTROL_GRF_FLUSH);
1263                         PRINT(KERN_INFO, lynx->id, "GRF overflow");
1264                 }
1265                 if (linkint & LINK_INT_ITF_UNDERFLOW) {
1266                         PRINT(KERN_INFO, lynx->id, "ITF underflow");
1267                 }
1268                 if (linkint & LINK_INT_ATF_UNDERFLOW) {
1269                         PRINT(KERN_INFO, lynx->id, "ATF underflow");
1270                 }
1271         }
1272
1273         if (intmask & PCI_INT_DMA_HLT(CHANNEL_ISO_RCV)) {
1274                 PRINTD(KERN_DEBUG, lynx->id, "iso receive");
1275
1276                 spin_lock(&lynx->iso_rcv.lock);
1277
1278                 lynx->iso_rcv.stat[lynx->iso_rcv.next] =
1279                         reg_read(lynx, DMA_CHAN_STAT(CHANNEL_ISO_RCV));
1280
1281                 lynx->iso_rcv.used++;
1282                 lynx->iso_rcv.next = (lynx->iso_rcv.next + 1) % NUM_ISORCV_PCL;
1283
1284                 if ((lynx->iso_rcv.next == lynx->iso_rcv.last)
1285                     || !lynx->iso_rcv.chan_count) {
1286                         PRINTD(KERN_DEBUG, lynx->id, "stopped");
1287                         reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), 0);
1288                 }
1289
1290                 run_sub_pcl(lynx, lynx->iso_rcv.pcl_start, lynx->iso_rcv.next,
1291                             CHANNEL_ISO_RCV);
1292
1293                 spin_unlock(&lynx->iso_rcv.lock);
1294
1295                 tasklet_schedule(&lynx->iso_rcv.tq);
1296         }
1297
1298         if (intmask & PCI_INT_DMA_HLT(CHANNEL_ASYNC_SEND)) {
1299                 PRINTD(KERN_DEBUG, lynx->id, "async sent");
1300                 spin_lock(&lynx->async.queue_lock);
1301
1302                 if (list_empty(&lynx->async.pcl_queue)) {
1303                         spin_unlock(&lynx->async.queue_lock);
1304                         PRINT(KERN_WARNING, lynx->id, "async dma halted, but no queued packet (maybe it was cancelled)");
1305                 } else {
1306                         struct ti_pcl pcl;
1307                         u32 ack;
1308                         struct hpsb_packet *packet;
1309
1310                         get_pcl(lynx, lynx->async.pcl, &pcl);
1311
1312                         packet = driver_packet(lynx->async.pcl_queue.next);
1313                         list_del(&packet->driver_list);
1314
1315                         pci_unmap_single(lynx->dev, lynx->async.header_dma,
1316                                          packet->header_size, PCI_DMA_TODEVICE);
1317                         if (packet->data_size) {
1318                                 pci_unmap_single(lynx->dev, lynx->async.data_dma,
1319                                                  packet->data_size, PCI_DMA_TODEVICE);
1320                         }
1321
1322                         if (!list_empty(&lynx->async.queue)) {
1323                                 send_next(lynx, hpsb_async);
1324                         }
1325
1326                         spin_unlock(&lynx->async.queue_lock);
1327
1328                         if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
1329                                 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
1330                                         ack = (pcl.pcl_status >> 15) & 0xf;
1331                                         PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
1332                                         ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
1333                                 } else {
1334                                         ack = (pcl.pcl_status >> 15) & 0xf;
1335                                 }
1336                         } else {
1337                                 PRINT(KERN_INFO, lynx->id, "async packet was not completed");
1338                                 ack = ACKX_SEND_ERROR;
1339                         }
1340                         hpsb_packet_sent(host, packet, ack);
1341                 }
1342         }
1343
1344         if (intmask & PCI_INT_DMA_HLT(CHANNEL_ISO_SEND)) {
1345                 PRINTD(KERN_DEBUG, lynx->id, "iso sent");
1346                 spin_lock(&lynx->iso_send.queue_lock);
1347
1348                 if (list_empty(&lynx->iso_send.pcl_queue)) {
1349                         spin_unlock(&lynx->iso_send.queue_lock);
1350                         PRINT(KERN_ERR, lynx->id, "iso send dma halted, but no queued packet");
1351                 } else {
1352                         struct ti_pcl pcl;
1353                         u32 ack;
1354                         struct hpsb_packet *packet;
1355
1356                         get_pcl(lynx, lynx->iso_send.pcl, &pcl);
1357
1358                         packet = driver_packet(lynx->iso_send.pcl_queue.next);
1359                         list_del(&packet->driver_list);
1360
1361                         pci_unmap_single(lynx->dev, lynx->iso_send.header_dma,
1362                                          packet->header_size, PCI_DMA_TODEVICE);
1363                         if (packet->data_size) {
1364                                 pci_unmap_single(lynx->dev, lynx->iso_send.data_dma,
1365                                                  packet->data_size, PCI_DMA_TODEVICE);
1366                         }
1367
1368                         if (!list_empty(&lynx->iso_send.queue)) {
1369                                 send_next(lynx, hpsb_iso);
1370                         }
1371
1372                         spin_unlock(&lynx->iso_send.queue_lock);
1373
1374                         if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
1375                                 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
1376                                         ack = (pcl.pcl_status >> 15) & 0xf;
1377                                         PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
1378                                         ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
1379                                 } else {
1380                                         ack = (pcl.pcl_status >> 15) & 0xf;
1381                                 }
1382                         } else {
1383                                 PRINT(KERN_INFO, lynx->id, "iso send packet was not completed");
1384                                 ack = ACKX_SEND_ERROR;
1385                         }
1386
1387                         hpsb_packet_sent(host, packet, ack); //FIXME: maybe we should just use ACK_COMPLETE and ACKX_SEND_ERROR
1388                 }
1389         }
1390
1391         if (intmask & PCI_INT_DMA_HLT(CHANNEL_ASYNC_RCV)) {
1392                 /* general receive DMA completed */
1393                 int stat = reg_read(lynx, DMA_CHAN_STAT(CHANNEL_ASYNC_RCV));
1394
1395                 PRINTD(KERN_DEBUG, lynx->id, "received packet size %d",
1396                        stat & 0x1fff);
1397
1398                 if (stat & DMA_CHAN_STAT_SELFID) {
1399                         lynx->selfid_size = stat & 0x1fff;
1400                         handle_selfid(lynx, host);
1401                 } else {
1402                         quadlet_t *q_data = lynx->rcv_page;
1403                         if ((*q_data >> 4 & 0xf) == TCODE_READQ_RESPONSE
1404                             || (*q_data >> 4 & 0xf) == TCODE_WRITEQ) {
1405                                 cpu_to_be32s(q_data + 3);
1406                         }
1407                         hpsb_packet_received(host, q_data, stat & 0x1fff, 0);
1408                 }
1409
1410                 run_pcl(lynx, lynx->rcv_pcl_start, CHANNEL_ASYNC_RCV);
1411         }
1412 }
1413
1414
1415 static void iso_rcv_bh(struct ti_lynx *lynx)
1416 {
1417         unsigned int idx;
1418         quadlet_t *data;
1419         unsigned long flags;
1420
1421         spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
1422
1423         while (lynx->iso_rcv.used) {
1424                 idx = lynx->iso_rcv.last;
1425                 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
1426
1427                 data = lynx->iso_rcv.page[idx / ISORCV_PER_PAGE]
1428                         + (idx % ISORCV_PER_PAGE) * MAX_ISORCV_SIZE;
1429
1430                 if ((*data >> 16) + 4 != (lynx->iso_rcv.stat[idx] & 0x1fff)) {
1431                         PRINT(KERN_ERR, lynx->id,
1432                               "iso length mismatch 0x%08x/0x%08x", *data,
1433                               lynx->iso_rcv.stat[idx]);
1434                 }
1435
1436                 if (lynx->iso_rcv.stat[idx]
1437                     & (DMA_CHAN_STAT_PCIERR | DMA_CHAN_STAT_PKTERR)) {
1438                         PRINT(KERN_INFO, lynx->id,
1439                               "iso receive error on %d to 0x%p", idx, data);
1440                 } else {
1441                         hpsb_packet_received(lynx->host, data,
1442                                              lynx->iso_rcv.stat[idx] & 0x1fff,
1443                                              0);
1444                 }
1445
1446                 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
1447                 lynx->iso_rcv.last = (idx + 1) % NUM_ISORCV_PCL;
1448                 lynx->iso_rcv.used--;
1449         }
1450
1451         if (lynx->iso_rcv.chan_count) {
1452                 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
1453                           DMA_WORD1_CMP_ENABLE_MASTER);
1454         }
1455         spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
1456 }
1457
1458
1459 static void remove_card(struct pci_dev *dev)
1460 {
1461         struct ti_lynx *lynx;
1462         int i;
1463
1464         lynx = pci_get_drvdata(dev);
1465         if (!lynx) return;
1466         pci_set_drvdata(dev, NULL);
1467
1468         switch (lynx->state) {
1469         case is_host:
1470                 reg_write(lynx, PCI_INT_ENABLE, 0);
1471                 hpsb_remove_host(lynx->host);
1472         case have_intr:
1473                 reg_write(lynx, PCI_INT_ENABLE, 0);
1474                 free_irq(lynx->dev->irq, lynx);
1475
1476                 /* Disable IRM Contender and LCtrl */
1477                 if (lynx->phyic.reg_1394a)
1478                         set_phy_reg(lynx, 4, ~0xc0 & get_phy_reg(lynx, 4));
1479
1480                 /* Let all other nodes know to ignore us */
1481                 lynx_devctl(lynx->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
1482
1483         case have_iomappings:
1484                 reg_set_bits(lynx, MISC_CONTROL, MISC_CONTROL_SWRESET);
1485                 /* Fix buggy cards with autoboot pin not tied low: */
1486                 reg_write(lynx, DMA0_CHAN_CTRL, 0);
1487                 iounmap(lynx->registers);
1488                 iounmap(lynx->local_rom);
1489                 iounmap(lynx->local_ram);
1490                 iounmap(lynx->aux_port);
1491         case have_1394_buffers:
1492                 for (i = 0; i < ISORCV_PAGES; i++) {
1493                         if (lynx->iso_rcv.page[i]) {
1494                                 pci_free_consistent(lynx->dev, PAGE_SIZE,
1495                                                     lynx->iso_rcv.page[i],
1496                                                     lynx->iso_rcv.page_dma[i]);
1497                         }
1498                 }
1499                 pci_free_consistent(lynx->dev, PAGE_SIZE, lynx->rcv_page,
1500                                     lynx->rcv_page_dma);
1501         case have_aux_buf:
1502 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
1503                 pci_free_consistent(lynx->dev, 65536, lynx->mem_dma_buffer,
1504                                     lynx->mem_dma_buffer_dma);
1505 #endif
1506         case have_pcl_mem:
1507 #ifndef CONFIG_IEEE1394_PCILYNX_LOCALRAM
1508                 pci_free_consistent(lynx->dev, LOCALRAM_SIZE, lynx->pcl_mem,
1509                                     lynx->pcl_mem_dma);
1510 #endif
1511         case clear:
1512                 /* do nothing - already freed */
1513                 ;
1514         }
1515
1516         tasklet_kill(&lynx->iso_rcv.tq);
1517         hpsb_unref_host(lynx->host);
1518 }
1519
1520
1521 static int __devinit add_card(struct pci_dev *dev,
1522                               const struct pci_device_id *devid_is_unused)
1523 {
1524 #define FAIL(fmt, args...) do { \
1525         PRINT_G(KERN_ERR, fmt , ## args); \
1526         remove_card(dev); \
1527         return error; \
1528         } while (0)
1529
1530         char irq_buf[16];
1531         struct hpsb_host *host;
1532         struct ti_lynx *lynx; /* shortcut to currently handled device */
1533         struct ti_pcl pcl;
1534         u32 *pcli;
1535         int i;
1536         int error;
1537
1538         /* needed for i2c communication with serial eeprom */
1539         struct i2c_adapter i2c_adapter;
1540         struct i2c_algo_bit_data i2c_adapter_data;
1541
1542         int got_valid_bus_info_block = 0; /* set to 1, if we were able to get a valid bus info block from serial eeprom */
1543
1544         error = -ENXIO;
1545
1546         if (pci_set_dma_mask(dev, 0xffffffff))
1547                 FAIL("DMA address limits not supported for PCILynx hardware");
1548         if (pci_enable_device(dev))
1549                 FAIL("failed to enable PCILynx hardware");
1550         pci_set_master(dev);
1551
1552         error = -ENOMEM;
1553
1554         host = hpsb_alloc_host(&lynx_driver, sizeof(struct ti_lynx));
1555         if (!host) FAIL("failed to allocate control structure memory");
1556
1557         lynx = host->hostdata;
1558         lynx->id = card_id++;
1559         lynx->dev = dev;
1560         lynx->state = clear;
1561         lynx->host = host;
1562         host->pdev = dev;
1563         pci_set_drvdata(dev, lynx);
1564
1565         lynx->lock = SPIN_LOCK_UNLOCKED;
1566         lynx->phy_reg_lock = SPIN_LOCK_UNLOCKED;
1567
1568 #ifndef CONFIG_IEEE1394_PCILYNX_LOCALRAM
1569         lynx->pcl_mem = pci_alloc_consistent(dev, LOCALRAM_SIZE,
1570                                              &lynx->pcl_mem_dma);
1571
1572         if (lynx->pcl_mem != NULL) {
1573                 lynx->state = have_pcl_mem;
1574                 PRINT(KERN_INFO, lynx->id,
1575                       "allocated PCL memory %d Bytes @ 0x%p", LOCALRAM_SIZE,
1576                       lynx->pcl_mem);
1577         } else {
1578                 FAIL("failed to allocate PCL memory area");
1579         }
1580 #endif
1581
1582 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
1583         lynx->mem_dma_buffer = pci_alloc_consistent(dev, 65536,
1584                                                     &lynx->mem_dma_buffer_dma);
1585         if (lynx->mem_dma_buffer == NULL) {
1586                 FAIL("failed to allocate DMA buffer for aux");
1587         }
1588         lynx->state = have_aux_buf;
1589 #endif
1590
1591         lynx->rcv_page = pci_alloc_consistent(dev, PAGE_SIZE,
1592                                               &lynx->rcv_page_dma);
1593         if (lynx->rcv_page == NULL) {
1594                 FAIL("failed to allocate receive buffer");
1595         }
1596         lynx->state = have_1394_buffers;
1597
1598         for (i = 0; i < ISORCV_PAGES; i++) {
1599                 lynx->iso_rcv.page[i] =
1600                         pci_alloc_consistent(dev, PAGE_SIZE,
1601                                              &lynx->iso_rcv.page_dma[i]);
1602                 if (lynx->iso_rcv.page[i] == NULL) {
1603                         FAIL("failed to allocate iso receive buffers");
1604                 }
1605         }
1606
1607         lynx->registers = ioremap_nocache(pci_resource_start(dev,0),
1608                                           PCILYNX_MAX_REGISTER);
1609         lynx->local_ram = ioremap(pci_resource_start(dev,1), PCILYNX_MAX_MEMORY);
1610         lynx->aux_port  = ioremap(pci_resource_start(dev,2), PCILYNX_MAX_MEMORY);
1611         lynx->local_rom = ioremap(pci_resource_start(dev,PCI_ROM_RESOURCE),
1612                                   PCILYNX_MAX_MEMORY);
1613         lynx->state = have_iomappings;
1614
1615         if (lynx->registers == NULL) {
1616                 FAIL("failed to remap registers - card not accessible");
1617         }
1618
1619 #ifdef CONFIG_IEEE1394_PCILYNX_LOCALRAM
1620         if (lynx->local_ram == NULL) {
1621                 FAIL("failed to remap local RAM which is required for "
1622                      "operation");
1623         }
1624 #endif
1625
1626         reg_set_bits(lynx, MISC_CONTROL, MISC_CONTROL_SWRESET);
1627         /* Fix buggy cards with autoboot pin not tied low: */
1628         reg_write(lynx, DMA0_CHAN_CTRL, 0);
1629
1630 #ifndef __sparc__
1631         sprintf (irq_buf, "%d", dev->irq);
1632 #else
1633         sprintf (irq_buf, "%s", __irq_itoa(dev->irq));
1634 #endif
1635
1636         if (!request_irq(dev->irq, lynx_irq_handler, SA_SHIRQ,
1637                          PCILYNX_DRIVER_NAME, lynx)) {
1638                 PRINT(KERN_INFO, lynx->id, "allocated interrupt %s", irq_buf);
1639                 lynx->state = have_intr;
1640         } else {
1641                 FAIL("failed to allocate shared interrupt %s", irq_buf);
1642         }
1643
1644         /* alloc_pcl return values are not checked, it is expected that the
1645          * provided PCL space is sufficient for the initial allocations */
1646 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
1647         if (lynx->aux_port != NULL) {
1648                 lynx->dmem_pcl = alloc_pcl(lynx);
1649                 aux_setup_pcls(lynx);
1650                 sema_init(&lynx->mem_dma_mutex, 1);
1651         }
1652 #endif
1653         lynx->rcv_pcl = alloc_pcl(lynx);
1654         lynx->rcv_pcl_start = alloc_pcl(lynx);
1655         lynx->async.pcl = alloc_pcl(lynx);
1656         lynx->async.pcl_start = alloc_pcl(lynx);
1657         lynx->iso_send.pcl = alloc_pcl(lynx);
1658         lynx->iso_send.pcl_start = alloc_pcl(lynx);
1659
1660         for (i = 0; i < NUM_ISORCV_PCL; i++) {
1661                 lynx->iso_rcv.pcl[i] = alloc_pcl(lynx);
1662         }
1663         lynx->iso_rcv.pcl_start = alloc_pcl(lynx);
1664
1665         /* all allocations successful - simple init stuff follows */
1666
1667         reg_write(lynx, PCI_INT_ENABLE, PCI_INT_DMA_ALL);
1668
1669 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
1670         reg_set_bits(lynx, PCI_INT_ENABLE, PCI_INT_AUX_INT);
1671         init_waitqueue_head(&lynx->mem_dma_intr_wait);
1672         init_waitqueue_head(&lynx->aux_intr_wait);
1673 #endif
1674
1675         tasklet_init(&lynx->iso_rcv.tq, (void (*)(unsigned long))iso_rcv_bh,
1676                      (unsigned long)lynx);
1677
1678         lynx->iso_rcv.lock = SPIN_LOCK_UNLOCKED;
1679
1680         lynx->async.queue_lock = SPIN_LOCK_UNLOCKED;
1681         lynx->async.channel = CHANNEL_ASYNC_SEND;
1682         lynx->iso_send.queue_lock = SPIN_LOCK_UNLOCKED;
1683         lynx->iso_send.channel = CHANNEL_ISO_SEND;
1684
1685         PRINT(KERN_INFO, lynx->id, "remapped memory spaces reg 0x%p, rom 0x%p, "
1686               "ram 0x%p, aux 0x%p", lynx->registers, lynx->local_rom,
1687               lynx->local_ram, lynx->aux_port);
1688
1689         /* now, looking for PHY register set */
1690         if ((get_phy_reg(lynx, 2) & 0xe0) == 0xe0) {
1691                 lynx->phyic.reg_1394a = 1;
1692                 PRINT(KERN_INFO, lynx->id,
1693                       "found 1394a conform PHY (using extended register set)");
1694                 lynx->phyic.vendor = get_phy_vendorid(lynx);
1695                 lynx->phyic.product = get_phy_productid(lynx);
1696         } else {
1697                 lynx->phyic.reg_1394a = 0;
1698                 PRINT(KERN_INFO, lynx->id, "found old 1394 PHY");
1699         }
1700
1701         lynx->selfid_size = -1;
1702         lynx->phy_reg0 = -1;
1703
1704         INIT_LIST_HEAD(&lynx->async.queue);
1705         INIT_LIST_HEAD(&lynx->async.pcl_queue);
1706         INIT_LIST_HEAD(&lynx->iso_send.queue);
1707         INIT_LIST_HEAD(&lynx->iso_send.pcl_queue);
1708
1709         pcl.next = pcl_bus(lynx, lynx->rcv_pcl);
1710         put_pcl(lynx, lynx->rcv_pcl_start, &pcl);
1711
1712         pcl.next = PCL_NEXT_INVALID;
1713         pcl.async_error_next = PCL_NEXT_INVALID;
1714 #ifdef __BIG_ENDIAN
1715         pcl.buffer[0].control = PCL_CMD_RCV | 16;
1716         pcl.buffer[1].control = PCL_LAST_BUFF | 4080;
1717 #else
1718         pcl.buffer[0].control = PCL_CMD_RCV | PCL_BIGENDIAN | 16;
1719         pcl.buffer[1].control = PCL_LAST_BUFF | 4080;
1720 #endif
1721         pcl.buffer[0].pointer = lynx->rcv_page_dma;
1722         pcl.buffer[1].pointer = lynx->rcv_page_dma + 16;
1723         put_pcl(lynx, lynx->rcv_pcl, &pcl);
1724
1725         pcl.next = pcl_bus(lynx, lynx->async.pcl);
1726         pcl.async_error_next = pcl_bus(lynx, lynx->async.pcl);
1727         put_pcl(lynx, lynx->async.pcl_start, &pcl);
1728
1729         pcl.next = pcl_bus(lynx, lynx->iso_send.pcl);
1730         pcl.async_error_next = PCL_NEXT_INVALID;
1731         put_pcl(lynx, lynx->iso_send.pcl_start, &pcl);
1732
1733         pcl.next = PCL_NEXT_INVALID;
1734         pcl.async_error_next = PCL_NEXT_INVALID;
1735         pcl.buffer[0].control = PCL_CMD_RCV | 4;
1736 #ifndef __BIG_ENDIAN
1737         pcl.buffer[0].control |= PCL_BIGENDIAN;
1738 #endif
1739         pcl.buffer[1].control = PCL_LAST_BUFF | 2044;
1740
1741         for (i = 0; i < NUM_ISORCV_PCL; i++) {
1742                 int page = i / ISORCV_PER_PAGE;
1743                 int sec = i % ISORCV_PER_PAGE;
1744
1745                 pcl.buffer[0].pointer = lynx->iso_rcv.page_dma[page]
1746                         + sec * MAX_ISORCV_SIZE;
1747                 pcl.buffer[1].pointer = pcl.buffer[0].pointer + 4;
1748                 put_pcl(lynx, lynx->iso_rcv.pcl[i], &pcl);
1749         }
1750
1751         pcli = (u32 *)&pcl;
1752         for (i = 0; i < NUM_ISORCV_PCL; i++) {
1753                 pcli[i] = pcl_bus(lynx, lynx->iso_rcv.pcl[i]);
1754         }
1755         put_pcl(lynx, lynx->iso_rcv.pcl_start, &pcl);
1756
1757         /* FIFO sizes from left to right: ITF=48 ATF=48 GRF=160 */
1758         reg_write(lynx, FIFO_SIZES, 0x003030a0);
1759         /* 20 byte threshold before triggering PCI transfer */
1760         reg_write(lynx, DMA_GLOBAL_REGISTER, 0x2<<24);
1761         /* threshold on both send FIFOs before transmitting:
1762            FIFO size - cache line size - 1 */
1763         i = reg_read(lynx, PCI_LATENCY_CACHELINE) & 0xff;
1764         i = 0x30 - i - 1;
1765         reg_write(lynx, FIFO_XMIT_THRESHOLD, (i << 8) | i);
1766
1767         reg_set_bits(lynx, PCI_INT_ENABLE, PCI_INT_1394);
1768
1769         reg_write(lynx, LINK_INT_ENABLE, LINK_INT_PHY_TIMEOUT
1770                   | LINK_INT_PHY_REG_RCVD  | LINK_INT_PHY_BUSRESET
1771                   | LINK_INT_ISO_STUCK     | LINK_INT_ASYNC_STUCK
1772                   | LINK_INT_SENT_REJECT   | LINK_INT_TX_INVALID_TC
1773                   | LINK_INT_GRF_OVERFLOW  | LINK_INT_ITF_UNDERFLOW
1774                   | LINK_INT_ATF_UNDERFLOW);
1775
1776         reg_write(lynx, DMA_WORD0_CMP_VALUE(CHANNEL_ASYNC_RCV), 0);
1777         reg_write(lynx, DMA_WORD0_CMP_ENABLE(CHANNEL_ASYNC_RCV), 0xa<<4);
1778         reg_write(lynx, DMA_WORD1_CMP_VALUE(CHANNEL_ASYNC_RCV), 0);
1779         reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ASYNC_RCV),
1780                   DMA_WORD1_CMP_MATCH_LOCAL_NODE | DMA_WORD1_CMP_MATCH_BROADCAST
1781                   | DMA_WORD1_CMP_MATCH_EXACT    | DMA_WORD1_CMP_MATCH_BUS_BCAST
1782                   | DMA_WORD1_CMP_ENABLE_SELF_ID | DMA_WORD1_CMP_ENABLE_MASTER);
1783
1784         run_pcl(lynx, lynx->rcv_pcl_start, CHANNEL_ASYNC_RCV);
1785
1786         reg_write(lynx, DMA_WORD0_CMP_VALUE(CHANNEL_ISO_RCV), 0);
1787         reg_write(lynx, DMA_WORD0_CMP_ENABLE(CHANNEL_ISO_RCV), 0x9<<4);
1788         reg_write(lynx, DMA_WORD1_CMP_VALUE(CHANNEL_ISO_RCV), 0);
1789         reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), 0);
1790
1791         run_sub_pcl(lynx, lynx->iso_rcv.pcl_start, 0, CHANNEL_ISO_RCV);
1792
1793         reg_write(lynx, LINK_CONTROL, LINK_CONTROL_RCV_CMP_VALID
1794                   | LINK_CONTROL_TX_ISO_EN   | LINK_CONTROL_RX_ISO_EN
1795                   | LINK_CONTROL_TX_ASYNC_EN | LINK_CONTROL_RX_ASYNC_EN
1796                   | LINK_CONTROL_RESET_TX    | LINK_CONTROL_RESET_RX);
1797
1798         if (!lynx->phyic.reg_1394a) {
1799                 /* attempt to enable contender bit -FIXME- would this work
1800                  * elsewhere? */
1801                 reg_set_bits(lynx, GPIO_CTRL_A, 0x1);
1802                 reg_write(lynx, GPIO_DATA_BASE + 0x3c, 0x1);
1803         } else {
1804                 /* set the contender and LCtrl bit in the extended PHY register
1805                  * set. (Should check that bis 0,1,2 (=0xE0) is set
1806                  * in register 2?)
1807                  */
1808                 i = get_phy_reg(lynx, 4);
1809                 if (i != -1) set_phy_reg(lynx, 4, i | 0xc0);
1810         }
1811
1812
1813         if (!skip_eeprom)
1814         {
1815                 i2c_adapter = bit_ops;
1816                 i2c_adapter_data = bit_data;
1817                 i2c_adapter.algo_data = &i2c_adapter_data;
1818                 i2c_adapter_data.data = lynx;
1819
1820                 PRINTD(KERN_DEBUG, lynx->id,"original eeprom control: %d",
1821                        reg_read(lynx, SERIAL_EEPROM_CONTROL));
1822
1823                 /* reset hardware to sane state */
1824                 lynx->i2c_driven_state = 0x00000070;
1825                 reg_write(lynx, SERIAL_EEPROM_CONTROL, lynx->i2c_driven_state);
1826
1827                 if (i2c_bit_add_bus(&i2c_adapter) < 0)
1828                 {
1829                         PRINT(KERN_ERR, lynx->id,  "unable to register i2c");
1830                 }
1831                 else
1832                 {
1833                         /* do i2c stuff */
1834                         unsigned char i2c_cmd = 0x10;
1835                         struct i2c_msg msg[2] = { { 0x50, 0, 1, &i2c_cmd },
1836                                                   { 0x50, I2C_M_RD, 20, (unsigned char*) lynx->config_rom }
1837                                                 };
1838
1839
1840 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
1841                         union i2c_smbus_data data;
1842
1843                         if (i2c_smbus_xfer(&i2c_adapter, 80, 0, I2C_SMBUS_WRITE, 0, I2C_SMBUS_BYTE,NULL))
1844                                 PRINT(KERN_ERR, lynx->id,"eeprom read start has failed");
1845                         else
1846                         {
1847                                 u16 addr;
1848                                 for (addr=0x00; addr < 0x100; addr++) {
1849                                         if (i2c_smbus_xfer(&i2c_adapter, 80, 0, I2C_SMBUS_READ, 0, I2C_SMBUS_BYTE,& data)) {
1850                                                 PRINT(KERN_ERR, lynx->id, "unable to read i2c %x", addr);
1851                                                 break;
1852                                         }
1853                                         else
1854                                                 PRINT(KERN_DEBUG, lynx->id,"got serial eeprom data at %x: %x",addr, data.byte);
1855                                 }
1856                         }
1857 #endif
1858
1859                         /* we use i2c_transfer, because i2c_smbus_read_block_data does not work properly and we
1860                            do it more efficiently in one transaction rather then using several reads */
1861                         if (i2c_transfer(&i2c_adapter, msg, 2) < 0) {
1862                                 PRINT(KERN_ERR, lynx->id, "unable to read bus info block from i2c");
1863                         } else {
1864                                 int i;
1865
1866                                 PRINT(KERN_INFO, lynx->id, "got bus info block from serial eeprom");
1867                                 /* FIXME: probably we shoud rewrite the max_rec, max_ROM(1394a),
1868                                  * generation(1394a) and link_spd(1394a) field and recalculate
1869                                  * the CRC */
1870
1871                                 for (i = 0; i < 5 ; i++)
1872                                         PRINTD(KERN_DEBUG, lynx->id, "Businfo block quadlet %i: %08x",
1873                                                i, be32_to_cpu(lynx->config_rom[i]));
1874
1875                                 /* info_length, crc_length and 1394 magic number to check, if it is really a bus info block */
1876                                 if (((be32_to_cpu(lynx->config_rom[0]) & 0xffff0000) == 0x04040000) &&
1877                                     (lynx->config_rom[1] == __constant_cpu_to_be32(0x31333934)))
1878                                 {
1879                                         PRINT(KERN_DEBUG, lynx->id, "read a valid bus info block from");
1880                                         got_valid_bus_info_block = 1;
1881                                 } else {
1882                                         PRINT(KERN_WARNING, lynx->id, "read something from serial eeprom, but it does not seem to be a valid bus info block");
1883                                 }
1884
1885                         }
1886
1887                         i2c_bit_del_bus(&i2c_adapter);
1888                 }
1889         }
1890
1891         if (got_valid_bus_info_block) {
1892                 memcpy(lynx->config_rom+5,lynx_csr_rom+5,sizeof(lynx_csr_rom)-20);
1893         } else {
1894                 PRINT(KERN_INFO, lynx->id, "since we did not get a bus info block from serial eeprom, we use a generic one with a hard coded GUID");
1895                 memcpy(lynx->config_rom,lynx_csr_rom,sizeof(lynx_csr_rom));
1896         }
1897
1898         hpsb_add_host(host);
1899         lynx->state = is_host;
1900
1901         return 0;
1902 #undef FAIL
1903 }
1904
1905
1906
1907 static size_t get_lynx_rom(struct hpsb_host *host, quadlet_t **ptr)
1908 {
1909         struct ti_lynx *lynx = host->hostdata;
1910         *ptr = lynx->config_rom;
1911         return sizeof(lynx_csr_rom);
1912 }
1913
1914 static struct pci_device_id pci_table[] __devinitdata = {
1915         {
1916                 .vendor =    PCI_VENDOR_ID_TI,
1917                 .device =    PCI_DEVICE_ID_TI_PCILYNX,
1918                 .subvendor = PCI_ANY_ID,
1919                 .subdevice = PCI_ANY_ID,
1920         },
1921         { }                     /* Terminating entry */
1922 };
1923
1924 static struct pci_driver lynx_pci_driver = {
1925         .name =     PCILYNX_DRIVER_NAME,
1926         .id_table = pci_table,
1927         .probe =    add_card,
1928         .remove =   remove_card,
1929 };
1930
1931 static struct hpsb_host_driver lynx_driver = {
1932         .name =            PCILYNX_DRIVER_NAME,
1933         .get_rom =         get_lynx_rom,
1934         .transmit_packet = lynx_transmit,
1935         .devctl =          lynx_devctl,
1936         .isoctl =          NULL,
1937 };
1938
1939 MODULE_AUTHOR("Andreas E. Bombe <andreas.bombe@munich.netsurf.de>");
1940 MODULE_DESCRIPTION("driver for Texas Instruments PCI Lynx IEEE-1394 controller");
1941 MODULE_LICENSE("GPL");
1942 MODULE_SUPPORTED_DEVICE("pcilynx");
1943 MODULE_DEVICE_TABLE(pci, pci_table);
1944
1945 static int __init pcilynx_init(void)
1946 {
1947         int ret;
1948
1949 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
1950         if (register_chrdev(PCILYNX_MAJOR, PCILYNX_DRIVER_NAME, &aux_ops)) {
1951                 PRINT_G(KERN_ERR, "allocation of char major number %d failed",
1952                         PCILYNX_MAJOR);
1953                 return -EBUSY;
1954         }
1955 #endif
1956
1957         ret = pci_module_init(&lynx_pci_driver);
1958         if (ret < 0) {
1959                 PRINT_G(KERN_ERR, "PCI module init failed");
1960                 goto free_char_dev;
1961         }
1962
1963         return 0;
1964
1965  free_char_dev:
1966 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
1967         unregister_chrdev(PCILYNX_MAJOR, PCILYNX_DRIVER_NAME);
1968 #endif
1969
1970         return ret;
1971 }
1972
1973 static void __exit pcilynx_cleanup(void)
1974 {
1975         pci_unregister_driver(&lynx_pci_driver);
1976
1977 #ifdef CONFIG_IEEE1394_PCILYNX_PORTS
1978         unregister_chrdev(PCILYNX_MAJOR, PCILYNX_DRIVER_NAME);
1979 #endif
1980 }
1981
1982
1983 module_init(pcilynx_init);
1984 module_exit(pcilynx_cleanup);