5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/tech/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
12 * 2002 Thomas Gleixner (tglx@linutronix.de)
14 * 10-29-2001 Thomas Gleixner (tglx@linutronix.de)
15 * - Changed nand_chip structure for controlline function to
16 * support different hardware structures (Access to
17 * controllines ALE,CLE,NCE via hardware specific function.
18 * - exit out of "failed erase block" changed, to avoid
20 * - init_waitqueue_head added in function nand_scan !!
22 * 01-30-2002 Thomas Gleixner (tglx@linutronix.de)
23 * change in nand_writev to block invalid vecs entries
25 * 02-11-2002 Thomas Gleixner (tglx@linutronix.de)
26 * - major rewrite to avoid duplicated code
27 * common nand_write_page function
28 * common get_chip function
29 * - added oob_config structure for out of band layouts
30 * - write_oob changed for partial programming
31 * - read cache for faster access for subsequent reads
33 * - support for different read/write address
34 * - support for device ready/busy line
35 * - read oob for more than one page enabled
37 * 02-27-2002 Thomas Gleixner (tglx@linutronix.de)
38 * - command-delay can be programmed
39 * - fixed exit from erase with callback-function enabled
41 * 03-21-2002 Thomas Gleixner (tglx@linutronix.de)
42 * - DEBUG improvements provided by Elizabeth Clarke
43 * (eclarke@aminocom.com)
44 * - added zero check for this->chip_delay
46 * 04-03-2002 Thomas Gleixner (tglx@linutronix.de)
47 * - added added hw-driver supplied command and wait functions
48 * - changed blocking for erase (erase suspend enabled)
49 * - check pointers before accessing flash provided by
50 * John Hall (john.hall@optionexist.co.uk)
52 * 04-09-2002 Thomas Gleixner (tglx@linutronix.de)
53 * - nand_wait repaired
55 * 04-28-2002 Thomas Gleixner (tglx@linutronix.de)
56 * - OOB config defines moved to nand.h
58 * 08-01-2002 Thomas Gleixner (tglx@linutronix.de)
59 * - changed my mailaddress, added pointer to tech/nand.html
61 * 08-07-2002 Thomas Gleixner (tglx@linutronix.de)
62 * forced bad block location to byte 5 of OOB, even if
63 * CONFIG_MTD_NAND_ECC_JFFS2 is not set, to prevent
64 * erase /dev/mtdX from erasing bad blocks and destroying
67 * 08-10-2002 Thomas Gleixner (tglx@linutronix.de)
68 * Fixed writing tail of data. Thanks to Alice Hennessy
69 * <ahennessy@mvista.com>.
71 * 08-10-2002 Thomas Gleixner (tglx@linutronix.de)
72 * nand_read_ecc and nand_write_page restructured to support
73 * hardware ECC. Thanks to Steven Hein (ssh@sgi.com)
74 * for basic implementation and suggestions.
75 * 3 new pointers in nand_chip structure:
76 * calculate_ecc, correct_data, enabled_hwecc
77 * forcing all hw-drivers to support page cache
78 * eccvalid_pos is now mandatory
80 * 08-17-2002 tglx: fixed signed/unsigned missmatch in write.c
81 * Thanks to Ken Offer <koffer@arlut.utexas.edu>
83 * 08-29-2002 tglx: use buffered read/write only for non pagealigned
84 * access, speed up the aligned path by using the fs-buffer
85 * reset chip removed from nand_select(), implicit done
86 * only, when erase is interrupted
87 * waitfuntion use yield, instead of schedule_timeout
88 * support for 6byte/512byte hardware ECC
89 * read_ecc, write_ecc extended for different oob-layout
90 * selections: Implemented NAND_NONE_OOB, NAND_JFFS2_OOB,
91 * NAND_YAFFS_OOB. fs-driver gives one of these constants
92 * to select the oob-layout fitting the filesystem.
93 * oobdata can be read together with the raw data, when
94 * the fs-driver supplies a big enough buffer.
95 * size = 12 * number of pages to read (256B pagesize)
96 * 24 * number of pages to read (512B pagesize)
97 * the buffer contains 8/16 byte oobdata and 4/8 byte
98 * returncode from calculate_ecc
99 * oobdata can be given from filesystem to program them
100 * in one go together with the raw data. ECC codes are
101 * filled in at the place selected by oobsel.
103 * 09-04-2002 tglx: fixed write_verify (John Hall (john.hall@optionexist.co.uk))
105 * 11-11-2002 tglx: fixed debug output in nand_write_page
106 * (John Hall (john.hall@optionexist.co.uk))
108 * 11-25-2002 tglx: Moved device ID/ manufacturer ID from nand_ids.h
109 * Splitted device ID and manufacturer ID table.
110 * Removed CONFIG_MTD_NAND_ECC, as it defaults to ECC_NONE for
111 * mtd->read / mtd->write and is controllable by the fs driver
112 * for mtd->read_ecc / mtd->write_ecc
113 * some minor cleanups
115 * 12-05-2000 tglx: Dave Ellis (DGE@sixnetio) provided the fix for
116 * WRITE_VERIFY long time ago. Thanks for remembering me.
118 * $Id: nand.c,v 1.36 2002/12/05 20:59:11 gleixner Exp $
120 * This program is free software; you can redistribute it and/or modify
121 * it under the terms of the GNU General Public License version 2 as
122 * published by the Free Software Foundation.
126 #include <linux/delay.h>
127 #include <linux/errno.h>
128 #include <linux/sched.h>
129 #include <linux/types.h>
130 #include <linux/mtd/mtd.h>
131 #include <linux/mtd/nand.h>
132 #include <linux/mtd/nand_ecc.h>
133 #include <linux/interrupt.h>
137 * Macros for low-level register control
139 #define nand_select() this->hwcontrol(NAND_CTL_SETNCE);
141 #define nand_deselect() this->hwcontrol(NAND_CTL_CLRNCE);
144 * out of band configuration for different filesystems
146 static int oobconfigs[][6] = {
149 { NAND_JFFS2_OOB_ECCPOS0, NAND_JFFS2_OOB_ECCPOS1, NAND_JFFS2_OOB_ECCPOS2,
150 NAND_JFFS2_OOB_ECCPOS3, NAND_JFFS2_OOB_ECCPOS4, NAND_JFFS2_OOB_ECCPOS5 },
152 { NAND_YAFFS_OOB_ECCPOS0, NAND_YAFFS_OOB_ECCPOS1, NAND_YAFFS_OOB_ECCPOS2,
153 NAND_YAFFS_OOB_ECCPOS3, NAND_YAFFS_OOB_ECCPOS4, NAND_YAFFS_OOB_ECCPOS5 }
157 * NAND low-level MTD interface functions
159 static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
160 static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
161 size_t * retlen, u_char * buf, u_char * eccbuf, int oobsel);
162 static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
163 static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf);
164 static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
165 size_t * retlen, const u_char * buf, u_char * eccbuf, int oobsel);
166 static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf);
167 static int nand_writev (struct mtd_info *mtd, const struct iovec *vecs,
168 unsigned long count, loff_t to, size_t * retlen);
169 static int nand_writev_ecc (struct mtd_info *mtd, const struct iovec *vecs,
170 unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, int oobsel);
171 static int nand_erase (struct mtd_info *mtd, struct erase_info *instr);
172 static void nand_sync (struct mtd_info *mtd);
173 static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, int col,
174 int last, u_char *oob_buf, int oobsel);
176 * Send command to NAND device
178 static void nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
180 register struct nand_chip *this = mtd->priv;
181 register unsigned long NAND_IO_ADDR = this->IO_ADDR_W;
183 /* Begin command latch cycle */
184 this->hwcontrol (NAND_CTL_SETCLE);
186 * Write out the command to the device.
188 if (command != NAND_CMD_SEQIN)
189 writeb (command, NAND_IO_ADDR);
191 if (mtd->oobblock == 256 && column >= 256) {
193 writeb (NAND_CMD_READOOB, NAND_IO_ADDR);
194 writeb (NAND_CMD_SEQIN, NAND_IO_ADDR);
195 } else if (mtd->oobblock == 512 && column >= 256) {
198 writeb (NAND_CMD_READ1, NAND_IO_ADDR);
199 writeb (NAND_CMD_SEQIN, NAND_IO_ADDR);
202 writeb (NAND_CMD_READOOB, NAND_IO_ADDR);
203 writeb (NAND_CMD_SEQIN, NAND_IO_ADDR);
206 writeb (NAND_CMD_READ0, NAND_IO_ADDR);
207 writeb (NAND_CMD_SEQIN, NAND_IO_ADDR);
211 /* Set ALE and clear CLE to start address cycle */
212 this->hwcontrol (NAND_CTL_CLRCLE);
214 if (column != -1 || page_addr != -1) {
215 this->hwcontrol (NAND_CTL_SETALE);
217 /* Serially input address */
219 writeb (column, NAND_IO_ADDR);
220 if (page_addr != -1) {
221 writeb ((unsigned char) (page_addr & 0xff), NAND_IO_ADDR);
222 writeb ((unsigned char) ((page_addr >> 8) & 0xff), NAND_IO_ADDR);
223 /* One more address cycle for higher density devices */
224 if (mtd->size & 0x0c000000)
225 writeb ((unsigned char) ((page_addr >> 16) & 0x0f), NAND_IO_ADDR);
227 /* Latch in address */
228 this->hwcontrol (NAND_CTL_CLRALE);
232 * program and erase have their own busy handlers
233 * status and sequential in needs no delay
237 case NAND_CMD_PAGEPROG:
238 case NAND_CMD_ERASE1:
239 case NAND_CMD_ERASE2:
241 case NAND_CMD_STATUS:
247 this->hwcontrol (NAND_CTL_SETCLE);
248 writeb (NAND_CMD_STATUS, NAND_IO_ADDR);
249 this->hwcontrol (NAND_CTL_CLRCLE);
250 while ( !(readb (this->IO_ADDR_R) & 0x40));
253 /* This applies to read commands */
256 * If we don't have access to the busy pin, we apply the given
259 if (!this->dev_ready) {
260 udelay (this->chip_delay);
265 /* wait until command is processed */
266 while (!this->dev_ready());
270 * Get chip for selected access
272 static inline void nand_get_chip (struct nand_chip *this, struct mtd_info *mtd, int new_state, int *erase_state)
275 DECLARE_WAITQUEUE (wait, current);
278 * Grab the lock and see if the device is available
279 * For erasing, we keep the spinlock until the
280 * erase command is written.
283 spin_lock_bh (&this->chip_lock);
285 if (this->state == FL_READY) {
286 this->state = new_state;
287 if (new_state != FL_ERASING)
288 spin_unlock_bh (&this->chip_lock);
292 if (this->state == FL_ERASING) {
293 if (new_state != FL_ERASING) {
294 this->state = new_state;
295 spin_unlock_bh (&this->chip_lock);
296 nand_select (); /* select in any case */
297 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
302 set_current_state (TASK_UNINTERRUPTIBLE);
303 add_wait_queue (&this->wq, &wait);
304 spin_unlock_bh (&this->chip_lock);
306 remove_wait_queue (&this->wq, &wait);
311 * Wait for command done. This applies to erase and program only
312 * Erase can take up to 400ms and program up to 20ms according to
313 * general NAND and SmartMedia specs
316 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
319 unsigned long timeo = jiffies;
322 if (state == FL_ERASING)
323 timeo += (HZ * 400) / 1000;
325 timeo += (HZ * 20) / 1000;
327 spin_lock_bh (&this->chip_lock);
328 this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
330 while (time_before(jiffies, timeo)) {
331 /* Check, if we were interrupted */
332 if (this->state != state) {
333 spin_unlock_bh (&this->chip_lock);
336 if (this->dev_ready) {
337 if (this->dev_ready ())
340 if (readb (this->IO_ADDR_R) & 0x40)
343 spin_unlock_bh (&this->chip_lock);
345 spin_lock_bh (&this->chip_lock);
347 status = (int) readb (this->IO_ADDR_R);
348 spin_unlock_bh (&this->chip_lock);
354 * Nand_page_program function is used for write and writev !
356 static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this,
357 int page, int col, int last, u_char *oob_buf, int oobsel)
360 u_char ecc_code[6], *oob_data;
361 int eccmode = oobsel ? this->eccmode : NAND_ECC_NONE;
362 int *oob_config = oobconfigs[oobsel];
364 /* pad oob area, if we have no oob buffer from fs-driver */
366 oob_data = &this->data_buf[mtd->oobblock];
367 for (i = 0; i < mtd->oobsize; i++)
372 /* software ecc 3 Bytes ECC / 256 Byte Data ? */
373 if (eccmode == NAND_ECC_SOFT) {
374 /* Read back previous written data, if col > 0 */
376 this->cmdfunc (mtd, NAND_CMD_READ0, 0, page);
377 for (i = 0; i < col; i++)
378 this->data_poi[i] = readb (this->IO_ADDR_R);
380 if ((col < this->eccsize) && (last >= this->eccsize)) {
381 this->calculate_ecc (&this->data_poi[0], &(ecc_code[0]));
382 for (i = 0; i < 3; i++)
383 oob_data[oob_config[i]] = ecc_code[i];
385 /* Calculate and write the second ECC if we have enough data */
386 if ((mtd->oobblock == 512) && (last == 512)) {
387 this->calculate_ecc (&this->data_poi[256], &(ecc_code[3]));
388 for (i = 3; i < 6; i++)
389 oob_data[oob_config[i]] = ecc_code[i];
392 /* For hardware ECC skip ECC, if we have no full page write */
393 if (eccmode != NAND_ECC_NONE && (col || last != mtd->oobblock))
394 eccmode = NAND_ECC_NONE;
397 /* Prepad for partial page programming !!! */
398 for (i = 0; i < col; i++)
399 this->data_poi[i] = 0xff;
401 /* Postpad for partial page programming !!! oob is already padded */
402 for (i = last; i < mtd->oobblock; i++)
403 this->data_poi[i] = 0xff;
405 /* Send command to begin auto page programming */
406 this->cmdfunc (mtd, NAND_CMD_SEQIN, 0x00, page);
408 /* Write out complete page of data, take care of eccmode */
409 switch (this->eccmode) {
410 /* No ecc and software ecc 3/256, write all */
413 for (i = 0; i < mtd->oobblock; i++)
414 writeb ( this->data_poi[i] , this->IO_ADDR_W);
417 /* Hardware ecc 3 byte / 256 data, write first half, get ecc, then second, if 512 byte pagesize */
418 case NAND_ECC_HW3_256:
419 this->enable_hwecc (NAND_ECC_WRITE); /* enable hardware ecc logic for write */
420 for (i = 0; i < mtd->eccsize; i++)
421 writeb ( this->data_poi[i] , this->IO_ADDR_W);
423 this->calculate_ecc (NULL, &(ecc_code[0]));
424 for (i = 0; i < 3; i++)
425 oob_data[oob_config[i]] = ecc_code[i];
427 if (mtd->oobblock == 512) {
428 this->enable_hwecc (NAND_ECC_WRITE); /* enable hardware ecc logic for write*/
429 for (i = mtd->eccsize; i < mtd->oobblock; i++)
430 writeb ( this->data_poi[i] , this->IO_ADDR_W);
431 this->calculate_ecc (NULL, &(ecc_code[3]));
432 for (i = 3; i < 6; i++)
433 oob_data[oob_config[i]] = ecc_code[i];
437 /* Hardware ecc 3 byte / 512 byte data, write full page */
438 case NAND_ECC_HW3_512:
439 this->enable_hwecc (NAND_ECC_WRITE); /* enable hardware ecc logic */
440 for (i = 0; i < mtd->oobblock; i++)
441 writeb ( this->data_poi[i] , this->IO_ADDR_W);
442 this->calculate_ecc (NULL, &(ecc_code[0]));
443 for (i = 0; i < 3; i++)
444 oob_data[oob_config[i]] = ecc_code[i];
447 /* Hardware ecc 6 byte / 512 byte data, write full page */
448 case NAND_ECC_HW6_512:
449 this->enable_hwecc (NAND_ECC_WRITE); /* enable hardware ecc logic */
450 for (i = 0; i < mtd->oobblock; i++)
451 writeb ( this->data_poi[i] , this->IO_ADDR_W);
452 this->calculate_ecc (NULL, &(ecc_code[0]));
453 for (i = 0; i < 6; i++)
454 oob_data[oob_config[i]] = ecc_code[i];
458 printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
462 /* Write out OOB data */
463 for (i = 0; i < mtd->oobsize; i++)
464 writeb ( oob_data[i] , this->IO_ADDR_W);
466 /* Send command to actually program the data */
467 this->cmdfunc (mtd, NAND_CMD_PAGEPROG, -1, -1);
469 /* call wait ready function */
470 status = this->waitfunc (mtd, this, FL_WRITING);
472 /* See if device thinks it succeeded */
474 DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
478 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
480 * The NAND device assumes that it is always writing to
481 * a cleanly erased page. Hence, it performs its internal
482 * write verification only on bits that transitioned from
483 * 1 to 0. The device does NOT verify the whole page on a
484 * byte by byte basis. It is possible that the page was
485 * not completely erased or the page is becoming unusable
486 * due to wear. The read with ECC would catch the error
487 * later when the ECC page check fails, but we would rather
488 * catch it early in the page write stage. Better to write
489 * no data than invalid data.
492 /* Send command to read back the page */
493 this->cmdfunc (mtd, NAND_CMD_READ0, col, page);
494 /* Loop through and verify the data */
495 for (i = col; i < last; i++) {
496 if (this->data_poi[i] != readb (this->IO_ADDR_R)) {
497 DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
502 /* check, if we have a fs-supplied oob-buffer */
504 for (i = 0; i < mtd->oobsize; i++) {
505 if (oob_data[i] != readb (this->IO_ADDR_R)) {
506 DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
511 if (eccmode != NAND_ECC_NONE && !col && last == mtd->oobblock) {
514 switch (this->eccmode) {
516 case NAND_ECC_HW3_256: ecc_bytes = (mtd->oobblock == 512) ? 6 : 3; break;
517 case NAND_ECC_HW3_512: ecc_bytes = 3; break;
518 case NAND_ECC_HW6_512: ecc_bytes = 6; break;
521 for (i = 0; i < mtd->oobsize; i++)
522 oob_data[i] = readb (this->IO_ADDR_R);
524 for (i = 0; i < ecc_bytes; i++) {
525 if (oob_data[oob_config[i]] != ecc_code[i]) {
526 DEBUG (MTD_DEBUG_LEVEL0,
527 "%s: Failed ECC write "
528 "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
541 static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
543 return (nand_read_ecc (mtd, from, len, retlen, buf, NULL, 0));
550 static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
551 size_t * retlen, u_char * buf, u_char * oob_buf, int oobsel)
553 int j, col, page, end, ecc;
555 int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0;
556 struct nand_chip *this = mtd->priv;
557 u_char *data_poi, *oob_data = oob_buf;
560 int eccmode = oobsel ? this->eccmode : NAND_ECC_NONE;
562 int *oob_config = oobconfigs[oobsel];
564 DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
566 /* Do not allow reads past end of device */
567 if ((from + len) > mtd->size) {
568 DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
573 /* Grab the lock and see if the device is available */
574 nand_get_chip (this, mtd ,FL_READING, &erase_state);
576 /* Select the NAND device */
579 /* First we calculate the starting page */
580 page = from >> this->page_shift;
582 /* Get raw starting column */
583 col = from & (mtd->oobblock - 1);
588 /* Send the read command */
589 this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
591 /* Loop until all data read */
594 /* If we have consequent page reads, apply delay or wait for ready/busy pin */
596 if (!this->dev_ready)
597 udelay (this->chip_delay);
599 while (!this->dev_ready());
603 * If the read is not page aligned, we have to read into data buffer
604 * due to ecc, else we read into return buffer direct
606 if (!col && (len - read) >= end)
607 data_poi = &buf[read];
609 data_poi = this->data_buf;
611 /* get oob area, if we have no oob buffer from fs-driver */
613 oob_data = &this->data_buf[end];
619 case NAND_ECC_NONE: /* No ECC, Read in a page */
621 data_poi[j++] = readb (this->IO_ADDR_R);
624 case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */
626 data_poi[j++] = readb (this->IO_ADDR_R);
627 this->calculate_ecc (&data_poi[0], &ecc_calc[0]);
628 if (mtd->oobblock == 512)
629 this->calculate_ecc (&data_poi[256], &ecc_calc[3]);
632 case NAND_ECC_HW3_256: /* Hardware ECC 3 byte /256 byte data: Read in first 256 byte, get ecc, */
633 this->enable_hwecc (NAND_ECC_READ);
635 data_poi[j++] = readb (this->IO_ADDR_R);
636 this->calculate_ecc (&data_poi[0], &ecc_calc[0]); /* read from hardware */
638 if (mtd->oobblock == 512) { /* read second, if pagesize = 512 */
639 this->enable_hwecc (NAND_ECC_READ);
641 data_poi[j++] = readb (this->IO_ADDR_R);
642 this->calculate_ecc (&data_poi[256], &ecc_calc[3]); /* read from hardware */
646 case NAND_ECC_HW3_512:
647 case NAND_ECC_HW6_512: /* Hardware ECC 3/6 byte / 512 byte data : Read in a page */
648 this->enable_hwecc (NAND_ECC_READ);
650 data_poi[j++] = readb (this->IO_ADDR_R);
651 this->calculate_ecc (&data_poi[0], &ecc_calc[0]); /* read from hardware */
655 printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
660 for (j = 0; j < mtd->oobsize; j++)
661 oob_data[oob + j] = readb (this->IO_ADDR_R);
663 /* Skip ECC, if not active */
664 if (eccmode == NAND_ECC_NONE)
667 /* Pick the ECC bytes out of the oob data */
668 for (j = 0; j < 6; j++)
669 ecc_code[j] = oob_data[oob + oob_config[j]];
671 /* correct data, if neccecary */
672 ecc_status = this->correct_data (&data_poi[0], &ecc_code[0], &ecc_calc[0]);
673 /* check, if we have a fs supplied oob-buffer */
676 *((int *)&oob_data[oob]) = ecc_status;
679 if (ecc_status == -1) {
680 DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page);
684 if (mtd->oobblock == 512 && eccmode != NAND_ECC_HW3_512) {
685 ecc_status = this->correct_data (&data_poi[256], &ecc_code[3], &ecc_calc[3]);
687 *((int *)&oob_data[oob]) = ecc_status;
690 if (ecc_status == -1) {
691 DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page);
696 if (col || (len - read) < end) {
697 for (j = col; j < end && read < len; j++)
698 buf[read++] = data_poi[j];
700 read += mtd->oobblock;
701 /* For subsequent reads align to page boundary. */
703 /* Increment page address */
707 /* De-select the NAND device */
710 /* Wake up anyone waiting on the device */
711 spin_lock_bh (&this->chip_lock);
712 this->state = FL_READY;
714 spin_unlock_bh (&this->chip_lock);
717 * Return success, if no ECC failures, else -EIO
718 * fs driver will take care of that, because
719 * retlen == desired len and result == -EIO
722 return ecc_failed ? -EIO : 0;
726 * NAND read out-of-band
728 static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
732 struct nand_chip *this = mtd->priv;
734 DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
736 /* Shift to get page */
737 page = ((int) from) >> this->page_shift;
739 /* Mask to get column */
742 /* Initialize return length value */
745 /* Do not allow reads past end of device */
746 if ((from + len) > mtd->size) {
747 DEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n");
752 /* Grab the lock and see if the device is available */
753 nand_get_chip (this, mtd , FL_READING, &erase_state);
755 /* Select the NAND device */
758 /* Send the read command */
759 this->cmdfunc (mtd, NAND_CMD_READOOB, col, page);
761 * Read the data, if we read more than one page
762 * oob data, let the device transfer the data !
764 for (i = 0; i < len; i++) {
765 buf[i] = readb (this->IO_ADDR_R);
766 if ((col++ & (mtd->oobsize - 1)) == (mtd->oobsize - 1))
767 udelay (this->chip_delay);
769 /* De-select the NAND device */
772 /* Wake up anyone waiting on the device */
773 spin_lock_bh (&this->chip_lock);
774 this->state = FL_READY;
776 spin_unlock_bh (&this->chip_lock);
786 static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
788 return (nand_write_ecc (mtd, to, len, retlen, buf, NULL, 0));
791 * NAND write with ECC
793 static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
794 size_t * retlen, const u_char * buf, u_char * eccbuf, int oobsel)
796 int i, page, col, cnt, ret = 0, oob = 0, written = 0;
797 struct nand_chip *this = mtd->priv;
799 DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
801 /* Do not allow write past end of device */
802 if ((to + len) > mtd->size) {
803 DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
807 /* Shift to get page */
808 page = ((int) to) >> this->page_shift;
810 /* Get the starting column */
811 col = to & (mtd->oobblock - 1);
813 /* Grab the lock and see if the device is available */
814 nand_get_chip (this, mtd, FL_WRITING, NULL);
816 /* Select the NAND device */
819 /* Check the WP bit */
820 this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
821 if (!(readb (this->IO_ADDR_R) & 0x80)) {
822 DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Device is write protected!!!\n");
827 /* Loop until all data is written */
828 while (written < len) {
830 * Check, if we have a full page write, then we can
831 * use the given buffer, else we have to copy
833 if (!col && (len - written) >= mtd->oobblock) {
834 this->data_poi = (u_char*) &buf[written];
838 for (i = col; i < len && i < mtd->oobblock; i++) {
839 this->data_buf[i] = buf[written + i];
842 this->data_poi = this->data_buf;
844 /* We use the same function for write and writev !) */
846 ret = nand_write_page (mtd, this, page, col, cnt ,&eccbuf[oob], oobsel);
849 ret = nand_write_page (mtd, this, page, col, cnt, NULL, oobsel);
854 /* Update written bytes count */
856 /* Next write is aligned */
858 /* Increment page address */
863 /* De-select the NAND device */
866 /* Wake up anyone waiting on the device */
867 spin_lock_bh (&this->chip_lock);
868 this->state = FL_READY;
870 spin_unlock_bh (&this->chip_lock);
877 * NAND write out-of-band
879 static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
881 int i, column, page, status, ret = 0;
882 struct nand_chip *this = mtd->priv;
884 DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
886 /* Shift to get page */
887 page = ((int) to) >> this->page_shift;
889 /* Mask to get column */
892 /* Initialize return length value */
895 /* Do not allow write past end of page */
896 if ((column + len) > mtd->oobsize) {
897 DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
901 /* Grab the lock and see if the device is available */
902 nand_get_chip (this, mtd, FL_WRITING, NULL);
904 /* Select the NAND device */
907 /* Check the WP bit */
908 this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
909 if (!(readb (this->IO_ADDR_R) & 0x80)) {
910 DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Device is write protected!!!\n");
915 /* Write out desired data */
916 this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page);
917 /* prepad 0xff for partial programming */
918 for (i = 0; i < column; i++)
919 writeb (0xff, this->IO_ADDR_W);
921 for (i = 0; i < len; i++)
922 writeb (buf[i], this->IO_ADDR_W);
923 /* postpad 0xff for partial programming */
924 for (i = len + column; i < mtd->oobsize; i++)
925 writeb (0xff, this->IO_ADDR_W);
927 /* Send command to program the OOB data */
928 this->cmdfunc (mtd, NAND_CMD_PAGEPROG, -1, -1);
930 status = this->waitfunc (mtd, this, FL_WRITING);
932 /* See if device thinks it succeeded */
934 DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page);
941 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
942 /* Send command to read back the data */
943 this->cmdfunc (mtd, NAND_CMD_READOOB, column, page);
945 /* Loop through and verify the data */
946 for (i = 0; i < len; i++) {
947 if (buf[i] != readb (this->IO_ADDR_R)) {
948 DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page);
956 /* De-select the NAND device */
959 /* Wake up anyone waiting on the device */
960 spin_lock_bh (&this->chip_lock);
961 this->state = FL_READY;
963 spin_unlock_bh (&this->chip_lock);
970 * NAND write with iovec
972 static int nand_writev (struct mtd_info *mtd, const struct iovec *vecs, unsigned long count,
973 loff_t to, size_t * retlen)
975 return (nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, 0));
978 static int nand_writev_ecc (struct mtd_info *mtd, const struct iovec *vecs, unsigned long count,
979 loff_t to, size_t * retlen, u_char *eccbuf, int oobsel)
981 int i, page, col, cnt, len, total_len, ret = 0, written = 0;
982 struct nand_chip *this = mtd->priv;
984 /* Calculate total length of data */
986 for (i = 0; i < count; i++)
987 total_len += (int) vecs[i].iov_len;
989 DEBUG (MTD_DEBUG_LEVEL3,
990 "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
992 /* Do not allow write past end of page */
993 if ((to + total_len) > mtd->size) {
994 DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n");
998 /* Shift to get page */
999 page = ((int) to) >> this->page_shift;
1001 /* Get the starting column */
1002 col = to & (mtd->oobblock - 1);
1004 /* Grab the lock and see if the device is available */
1005 nand_get_chip (this, mtd, FL_WRITING, NULL);
1007 /* Select the NAND device */
1010 /* Check the WP bit */
1011 this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
1012 if (!(readb (this->IO_ADDR_R) & 0x80)) {
1013 DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Device is write protected!!!\n");
1018 /* Loop until all iovecs' data has been written */
1024 * Check, if we write from offset 0 and if the tuple
1025 * gives us not enough data for a full page write. Then we
1026 * can use the iov direct, else we have to copy into
1029 if (!cnt && (vecs->iov_len - len) >= mtd->oobblock) {
1030 cnt = mtd->oobblock;
1031 this->data_poi = (u_char *) vecs->iov_base;
1032 this->data_poi += len;
1033 len += mtd->oobblock;
1034 /* Check, if we have to switch to the next tuple */
1035 if (len >= (int) vecs->iov_len) {
1042 * Read data out of each tuple until we have a full page
1043 * to write or we've read all the tuples.
1045 while ((cnt < mtd->oobblock) && count) {
1046 if (vecs->iov_base != NULL && vecs->iov_len) {
1047 this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++];
1049 /* Check, if we have to switch to the next tuple */
1050 if (len >= (int) vecs->iov_len) {
1056 this->data_poi = this->data_buf;
1059 /* We use the same function for write and writev !) */
1060 ret = nand_write_page (mtd, this, page, col, cnt, NULL, oobsel);
1064 /* Update written bytes count */
1065 written += (cnt - col);
1067 /* Reset written byte counter and column */
1070 /* Increment page address */
1075 /* De-select the NAND device */
1078 /* Wake up anyone waiting on the device */
1079 spin_lock_bh (&this->chip_lock);
1080 this->state = FL_READY;
1081 wake_up (&this->wq);
1082 spin_unlock_bh (&this->chip_lock);
1089 * NAND erase a block
1091 static int nand_erase (struct mtd_info *mtd, struct erase_info *instr)
1093 int page, len, status, pages_per_block, ret;
1094 struct nand_chip *this = mtd->priv;
1095 DECLARE_WAITQUEUE (wait, current);
1097 DEBUG (MTD_DEBUG_LEVEL3,
1098 "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
1100 /* Start address must align on block boundary */
1101 if (instr->addr & (mtd->erasesize - 1)) {
1102 DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1106 /* Length must align on block boundary */
1107 if (instr->len & (mtd->erasesize - 1)) {
1108 DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n");
1112 /* Do not allow erase past end of device */
1113 if ((instr->len + instr->addr) > mtd->size) {
1114 DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n");
1118 /* Grab the lock and see if the device is available */
1119 nand_get_chip (this, mtd, FL_ERASING, NULL);
1121 /* Shift to get first page */
1122 page = (int) (instr->addr >> this->page_shift);
1124 /* Calculate pages in each block */
1125 pages_per_block = mtd->erasesize / mtd->oobblock;
1127 /* Select the NAND device */
1130 /* Check the WP bit */
1131 this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
1132 if (!(readb (this->IO_ADDR_R) & 0x80)) {
1133 DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n");
1134 instr->state = MTD_ERASE_FAILED;
1138 /* Loop through the pages */
1141 instr->state = MTD_ERASING;
1144 /* Check if we have a bad block, we do not erase bad blocks ! */
1145 this->cmdfunc (mtd, NAND_CMD_READOOB, NAND_BADBLOCK_POS, page);
1146 if (readb (this->IO_ADDR_R) != 0xff) {
1147 printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
1148 instr->state = MTD_ERASE_FAILED;
1152 /* Send commands to erase a page */
1153 this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page);
1154 this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1);
1156 spin_unlock_bh (&this->chip_lock);
1157 status = this->waitfunc (mtd, this, FL_ERASING);
1159 /* Get spinlock, in case we exit */
1160 spin_lock_bh (&this->chip_lock);
1161 /* See if block erase succeeded */
1162 if (status & 0x01) {
1163 DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page);
1164 instr->state = MTD_ERASE_FAILED;
1168 /* Check, if we were interupted */
1169 if (this->state == FL_ERASING) {
1170 /* Increment page address and decrement length */
1171 len -= mtd->erasesize;
1172 page += pages_per_block;
1174 /* Release the spin lock */
1175 spin_unlock_bh (&this->chip_lock);
1177 spin_lock_bh (&this->chip_lock);
1178 /* Check the state and sleep if it changed */
1179 if (this->state == FL_ERASING || this->state == FL_READY) {
1180 /* Select the NAND device again, if we were interrupted */
1181 this->state = FL_ERASING;
1185 set_current_state (TASK_UNINTERRUPTIBLE);
1186 add_wait_queue (&this->wq, &wait);
1187 spin_unlock_bh (&this->chip_lock);
1189 remove_wait_queue (&this->wq, &wait);
1193 instr->state = MTD_ERASE_DONE;
1196 /* De-select the NAND device */
1198 spin_unlock_bh (&this->chip_lock);
1200 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;;
1201 /* Do call back function */
1202 if (!ret && instr->callback)
1203 instr->callback (instr);
1205 /* The device is ready */
1206 spin_lock_bh (&this->chip_lock);
1207 this->state = FL_READY;
1208 spin_unlock_bh (&this->chip_lock);
1210 /* Return more or less happy */
1217 static void nand_sync (struct mtd_info *mtd)
1219 struct nand_chip *this = mtd->priv;
1220 DECLARE_WAITQUEUE (wait, current);
1222 DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
1225 /* Grab the spinlock */
1226 spin_lock_bh (&this->chip_lock);
1228 /* See what's going on */
1229 switch (this->state) {
1232 this->state = FL_SYNCING;
1233 spin_unlock_bh (&this->chip_lock);
1237 /* Not an idle state */
1238 add_wait_queue (&this->wq, &wait);
1239 spin_unlock_bh (&this->chip_lock);
1242 remove_wait_queue (&this->wq, &wait);
1246 /* Lock the device */
1247 spin_lock_bh (&this->chip_lock);
1249 /* Set the device to be ready again */
1250 if (this->state == FL_SYNCING) {
1251 this->state = FL_READY;
1252 wake_up (&this->wq);
1255 /* Unlock the device */
1256 spin_unlock_bh (&this->chip_lock);
1260 * Scan for the NAND device
1262 int nand_scan (struct mtd_info *mtd)
1264 int i, nand_maf_id, nand_dev_id;
1265 struct nand_chip *this = mtd->priv;
1267 /* check for proper chip_delay setup, set 20us if not */
1268 if (!this->chip_delay)
1269 this->chip_delay = 20;
1271 /* check, if a user supplied command function given */
1272 if (this->cmdfunc == NULL)
1273 this->cmdfunc = nand_command;
1275 /* check, if a user supplied wait function given */
1276 if (this->waitfunc == NULL)
1277 this->waitfunc = nand_wait;
1279 /* Select the device */
1282 /* Send the command for reading device ID */
1283 this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1);
1285 /* Read manufacturer and device IDs */
1286 nand_maf_id = readb (this->IO_ADDR_R);
1287 nand_dev_id = readb (this->IO_ADDR_R);
1289 /* Print and store flash device information */
1290 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
1291 if (nand_dev_id == nand_flash_ids[i].id && !mtd->size) {
1292 mtd->name = nand_flash_ids[i].name;
1293 mtd->erasesize = nand_flash_ids[i].erasesize;
1294 mtd->size = (1 << nand_flash_ids[i].chipshift);
1296 if (nand_flash_ids[i].page256) {
1297 mtd->oobblock = 256;
1299 this->page_shift = 8;
1301 mtd->oobblock = 512;
1303 this->page_shift = 9;
1305 /* Try to identify manufacturer */
1306 for (i = 0; nand_manuf_ids[i].id != 0x0; i++) {
1307 if (nand_manuf_ids[i].id == nand_maf_id)
1310 printk (KERN_INFO "NAND device: Manufacture ID:"
1311 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
1312 nand_manuf_ids[i].name , mtd->name);
1318 * check ECC mode, default to software
1319 * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize
1320 * fallback to software ECC
1322 this->eccsize = 256; /* set default eccsize */
1324 switch (this->eccmode) {
1326 case NAND_ECC_HW3_512:
1327 if (mtd->oobblock == 256) {
1328 printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n");
1329 this->eccmode = NAND_ECC_SOFT;
1330 this->calculate_ecc = nand_calculate_ecc;
1331 this->correct_data = nand_correct_data;
1334 this->eccsize = 512; /* set eccsize to 512 and fall through for function check */
1336 case NAND_ECC_HW3_256:
1337 if (this->calculate_ecc && this->correct_data && this->enable_hwecc)
1339 printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n");
1343 this->eccmode = NAND_ECC_NONE;
1347 this->calculate_ecc = nand_calculate_ecc;
1348 this->correct_data = nand_correct_data;
1352 printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
1356 /* Initialize state, waitqueue and spinlock */
1357 this->state = FL_READY;
1358 init_waitqueue_head (&this->wq);
1359 spin_lock_init (&this->chip_lock);
1361 /* De-select the device */
1364 /* Print warning message for no device */
1366 printk (KERN_WARNING "No NAND device found!!!\n");
1370 /* Fill in remaining MTD driver data */
1371 mtd->type = MTD_NANDFLASH;
1372 mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
1373 mtd->module = THIS_MODULE;
1374 mtd->ecctype = MTD_ECC_SW;
1375 mtd->erase = nand_erase;
1377 mtd->unpoint = NULL;
1378 mtd->read = nand_read;
1379 mtd->write = nand_write;
1380 mtd->read_ecc = nand_read_ecc;
1381 mtd->write_ecc = nand_write_ecc;
1382 mtd->read_oob = nand_read_oob;
1383 mtd->write_oob = nand_write_oob;
1385 mtd->writev = nand_writev;
1386 mtd->writev_ecc = nand_writev_ecc;
1387 mtd->sync = nand_sync;
1390 mtd->suspend = NULL;
1397 EXPORT_SYMBOL (nand_scan);
1399 MODULE_LICENSE ("GPL");
1400 MODULE_AUTHOR ("Steven J. Hill <sjhill@cotw.com>, Thomas Gleixner <tglx@linutronix.de>");
1401 MODULE_DESCRIPTION ("Generic NAND flash driver code");