2 * $Id: proc.c,v 1.13 1998/05/12 07:36:07 mj Exp $
4 * Procfs interface for the PCI bus.
6 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
9 #include <linux/types.h>
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/proc_fs.h>
13 #include <linux/init.h>
14 #include <linux/seq_file.h>
16 #include <asm/uaccess.h>
17 #include <asm/byteorder.h>
19 #define PCI_CFG_SPACE_SIZE 256
22 proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
31 new = file->f_pos + off;
34 new = PCI_CFG_SPACE_SIZE + off;
39 if (new < 0 || new > PCI_CFG_SPACE_SIZE)
41 return (file->f_pos = new);
45 proc_bus_pci_read(struct file *file, char *buf, size_t nbytes, loff_t *ppos)
47 const struct inode *ino = file->f_dentry->d_inode;
48 const struct proc_dir_entry *dp = ino->u.generic_ip;
49 struct pci_dev *dev = dp->data;
52 unsigned int cnt, size;
55 * Normal users can read only the standardized portion of the
56 * configuration space as several chips lock up when trying to read
57 * undefined locations (think of Intel PIIX4 as a typical example).
60 if (capable(CAP_SYS_ADMIN))
61 size = PCI_CFG_SPACE_SIZE;
62 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
67 if (pos != n || pos >= size)
71 if (pos + nbytes > size)
75 if (!access_ok(VERIFY_WRITE, buf, cnt))
78 if ((pos & 1) && cnt) {
80 pci_read_config_byte(dev, pos, &val);
87 if ((pos & 3) && cnt > 2) {
89 pci_read_config_word(dev, pos, &val);
90 __put_user(cpu_to_le16(val), (unsigned short *) buf);
98 pci_read_config_dword(dev, pos, &val);
99 __put_user(cpu_to_le32(val), (unsigned int *) buf);
107 pci_read_config_word(dev, pos, &val);
108 __put_user(cpu_to_le16(val), (unsigned short *) buf);
116 pci_read_config_byte(dev, pos, &val);
117 __put_user(val, buf);
128 proc_bus_pci_write(struct file *file, const char *buf, size_t nbytes, loff_t *ppos)
130 const struct inode *ino = file->f_dentry->d_inode;
131 const struct proc_dir_entry *dp = ino->u.generic_ip;
132 struct pci_dev *dev = dp->data;
137 if (pos != n || pos >= PCI_CFG_SPACE_SIZE)
139 if (nbytes >= PCI_CFG_SPACE_SIZE)
140 nbytes = PCI_CFG_SPACE_SIZE;
141 if (pos + nbytes > PCI_CFG_SPACE_SIZE)
142 nbytes = PCI_CFG_SPACE_SIZE - pos;
145 if (!access_ok(VERIFY_READ, buf, cnt))
148 if ((pos & 1) && cnt) {
150 __get_user(val, buf);
151 pci_write_config_byte(dev, pos, val);
157 if ((pos & 3) && cnt > 2) {
159 __get_user(val, (unsigned short *) buf);
160 pci_write_config_word(dev, pos, le16_to_cpu(val));
168 __get_user(val, (unsigned int *) buf);
169 pci_write_config_dword(dev, pos, le32_to_cpu(val));
177 __get_user(val, (unsigned short *) buf);
178 pci_write_config_word(dev, pos, le16_to_cpu(val));
186 __get_user(val, buf);
187 pci_write_config_byte(dev, pos, val);
197 struct pci_filp_private {
198 enum pci_mmap_state mmap_state;
202 static int proc_bus_pci_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
204 const struct proc_dir_entry *dp = inode->u.generic_ip;
205 struct pci_dev *dev = dp->data;
207 struct pci_filp_private *fpriv = file->private_data;
208 #endif /* HAVE_PCI_MMAP */
212 case PCIIOC_CONTROLLER:
213 ret = pci_controller_num(dev);
217 case PCIIOC_MMAP_IS_IO:
218 fpriv->mmap_state = pci_mmap_io;
221 case PCIIOC_MMAP_IS_MEM:
222 fpriv->mmap_state = pci_mmap_mem;
225 case PCIIOC_WRITE_COMBINE:
227 fpriv->write_combine = 1;
229 fpriv->write_combine = 0;
232 #endif /* HAVE_PCI_MMAP */
243 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
245 struct inode *inode = file->f_dentry->d_inode;
246 const struct proc_dir_entry *dp = inode->u.generic_ip;
247 struct pci_dev *dev = dp->data;
248 struct pci_filp_private *fpriv = file->private_data;
251 if (!capable(CAP_SYS_RAWIO))
254 ret = pci_mmap_page_range(dev, vma,
256 fpriv->write_combine);
263 static int proc_bus_pci_open(struct inode *inode, struct file *file)
265 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
270 fpriv->mmap_state = pci_mmap_io;
271 fpriv->write_combine = 0;
273 file->private_data = fpriv;
278 static int proc_bus_pci_release(struct inode *inode, struct file *file)
280 kfree(file->private_data);
281 file->private_data = NULL;
285 #endif /* HAVE_PCI_MMAP */
287 static struct file_operations proc_bus_pci_operations = {
288 llseek: proc_bus_pci_lseek,
289 read: proc_bus_pci_read,
290 write: proc_bus_pci_write,
291 ioctl: proc_bus_pci_ioctl,
293 open: proc_bus_pci_open,
294 release: proc_bus_pci_release,
295 mmap: proc_bus_pci_mmap,
296 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
297 get_unmapped_area: get_pci_unmapped_area,
298 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
299 #endif /* HAVE_PCI_MMAP */
302 #if BITS_PER_LONG == 32
303 #define LONG_FORMAT "\t%08lx"
305 #define LONG_FORMAT "\t%16lx"
309 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
311 struct list_head *p = &pci_devices;
314 /* XXX: surely we need some locking for traversing the list? */
317 if (p == &pci_devices)
322 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
324 struct list_head *p = v;
326 return p->next != &pci_devices ? p->next : NULL;
328 static void pci_seq_stop(struct seq_file *m, void *v)
330 /* release whatever locks we need */
333 static int show_device(struct seq_file *m, void *v)
335 struct list_head *p = v;
336 const struct pci_dev *dev;
337 const struct pci_driver *drv;
340 if (p == &pci_devices)
344 drv = pci_dev_driver(dev);
345 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
351 /* Here should be 7 and not PCI_NUM_RESOURCES as we need to preserve compatibility */
353 seq_printf(m, LONG_FORMAT,
354 dev->resource[i].start |
355 (dev->resource[i].flags & PCI_REGION_FLAG_MASK));
357 seq_printf(m, LONG_FORMAT,
358 dev->resource[i].start < dev->resource[i].end ?
359 dev->resource[i].end - dev->resource[i].start + 1 : 0);
362 seq_printf(m, "%s", drv->name);
367 static struct seq_operations proc_bus_pci_devices_op = {
368 start: pci_seq_start,
374 struct proc_dir_entry *proc_bus_pci_dir;
376 int pci_proc_attach_device(struct pci_dev *dev)
378 struct pci_bus *bus = dev->bus;
379 struct proc_dir_entry *de, *e;
382 if (!(de = bus->procdir)) {
383 sprintf(name, "%02x", bus->number);
384 de = bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
388 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
389 e = dev->procent = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUSR, de);
392 e->proc_fops = &proc_bus_pci_operations;
394 e->size = PCI_CFG_SPACE_SIZE;
398 int pci_proc_detach_device(struct pci_dev *dev)
400 struct proc_dir_entry *e;
402 if ((e = dev->procent)) {
403 if (atomic_read(&e->count))
405 remove_proc_entry(e->name, dev->bus->procdir);
411 int pci_proc_attach_bus(struct pci_bus* bus)
413 struct proc_dir_entry *de = bus->procdir;
417 sprintf(name, "%02x", bus->number);
418 de = bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
425 int pci_proc_detach_bus(struct pci_bus* bus)
427 struct proc_dir_entry *de = bus->procdir;
429 remove_proc_entry(de->name, proc_bus_pci_dir);
435 * Backward compatible /proc/pci interface.
439 * Convert some of the configuration space registers of the device at
440 * address (bus,devfn) into a string (possibly several lines each).
441 * The configuration string is stored starting at buf[len]. If the
442 * string would exceed the size of the buffer (SIZE), 0 is returned.
444 static int show_dev_config(struct seq_file *m, void *v)
446 struct list_head *p = v;
448 struct pci_driver *drv;
450 unsigned char latency, min_gnt, max_lat, *class;
453 if (p == &pci_devices) {
454 seq_puts(m, "PCI devices found:\n");
459 drv = pci_dev_driver(dev);
461 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
462 pci_read_config_byte (dev, PCI_LATENCY_TIMER, &latency);
463 pci_read_config_byte (dev, PCI_MIN_GNT, &min_gnt);
464 pci_read_config_byte (dev, PCI_MAX_LAT, &max_lat);
465 seq_printf(m, " Bus %2d, device %3d, function %2d:\n",
466 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
467 class = pci_class_name(class_rev >> 16);
469 seq_printf(m, " %s", class);
471 seq_printf(m, " Class %04x", class_rev >> 16);
472 seq_printf(m, ": %s (rev %d).\n", dev->name, class_rev & 0xff);
474 //if (dev->irq) //+Bing modified 01122005
475 seq_printf(m, " IRQ %d.\n", dev->irq);
477 if (latency || min_gnt || max_lat) {
478 seq_printf(m, " Master Capable. ");
480 seq_printf(m, "Latency=%d. ", latency);
482 seq_puts(m, "No bursts. ");
484 seq_printf(m, "Min Gnt=%d.", min_gnt);
486 seq_printf(m, "Max Lat=%d.", max_lat);
490 for (reg = 0; reg < 6; reg++) {
491 struct resource *res = dev->resource + reg;
492 unsigned long base, end, flags;
500 if (flags & PCI_BASE_ADDRESS_SPACE_IO) {
501 seq_printf(m, " I/O at 0x%lx [0x%lx].\n",
504 const char *pref, *type = "unknown";
506 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
510 switch (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
511 case PCI_BASE_ADDRESS_MEM_TYPE_32:
512 type = "32 bit"; break;
513 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
514 type = "20 bit"; break;
515 case PCI_BASE_ADDRESS_MEM_TYPE_64:
516 type = "64 bit"; break;
518 seq_printf(m, " %srefetchable %s memory at "
519 "0x%lx [0x%lx].\n", pref, type,
527 static struct seq_operations proc_pci_op = {
528 start: pci_seq_start,
531 show: show_dev_config
534 static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
536 return seq_open(file, &proc_bus_pci_devices_op);
538 static struct file_operations proc_bus_pci_dev_operations = {
539 open: proc_bus_pci_dev_open,
542 release: seq_release,
544 static int proc_pci_open(struct inode *inode, struct file *file)
546 return seq_open(file, &proc_pci_op);
548 static struct file_operations proc_pci_operations = {
552 release: seq_release,
555 static int __init pci_proc_init(void)
558 struct proc_dir_entry *entry;
560 proc_bus_pci_dir = proc_mkdir("pci", proc_bus);
561 entry = create_proc_entry("devices", 0, proc_bus_pci_dir);
563 entry->proc_fops = &proc_bus_pci_dev_operations;
564 pci_for_each_dev(dev) {
565 pci_proc_attach_device(dev);
567 entry = create_proc_entry("pci", 0, NULL);
569 entry->proc_fops = &proc_pci_operations;
574 __initcall(pci_proc_init);