2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
4 * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
5 * (C) 2001-2002 Montavista Software, Inc.
8 * "The ExCA standard specifies that socket controllers should provide
9 * two IO and five memory windows per socket, which can be independently
10 * configured and positioned in the host address space and mapped to
11 * arbitrary segments of card address space. " - David A Hinds. 1999
13 * This controller does _not_ meet the ExCA standard.
15 * m8xx pcmcia controller brief info:
16 * + 8 windows (attrib, mem, i/o)
17 * + up to two slots (SLOT_A and SLOT_B)
18 * + inputpins, outputpins, event and mask registers.
19 * - no offset register. sigh.
21 * Because of the lacking offset register we must map the whole card.
22 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
23 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
24 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
25 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
26 * They are maximum 64KByte each...
29 #include <linux/module.h>
30 #include <linux/init.h>
31 #include <linux/types.h>
32 #include <linux/fcntl.h>
33 #include <linux/string.h>
36 #include <asm/bitops.h>
37 #include <asm/segment.h>
38 #include <asm/system.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/sched.h>
43 #include <linux/slab.h>
44 #include <linux/timer.h>
45 #include <linux/ioport.h>
46 #include <linux/delay.h>
48 #include <asm/mpc8xx.h>
49 #include <asm/8xx_immap.h>
52 #include <pcmcia/version.h>
53 #include <pcmcia/cs_types.h>
54 #include <pcmcia/cs.h>
55 #include <pcmcia/ss.h>
58 static int pc_debug = PCMCIA_DEBUG;
59 MODULE_PARM(pc_debug, "i");
60 #define DEBUG(n, args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
62 #define DEBUG(n, args...)
65 #define PCMCIA_INFO(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
66 #define PCMCIA_ERROR(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
68 static const char *version = "Version 0.05, 14-Apr-2002";
69 MODULE_LICENSE("Dual MPL/GPL");
71 /* The RPX series use SLOT_B */
73 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
74 #define CONFIG_PCMCIA_SLOT_B
77 /* The MBX board use SLOT_A */
80 #define CONFIG_PCMCIA_SLOT_A
83 /* The FADS860T board use SLOT_A */
86 #define CONFIG_PCMCIA_SLOT_A
89 /* ------------------------------------------------------------------------- */
91 #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
92 #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
93 #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
95 #define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */
97 /* ------------------------------------------------------------------------- */
99 #define PCMCIA_SOCKETS_NO 1
101 #define PCMCIA_MEM_WIN_NO 5
102 #define PCMCIA_IO_WIN_NO 2
104 /* define _slot_ to be able to optimize macros */
106 #ifdef CONFIG_PCMCIA_SLOT_A
108 #define PCMCIA_SLOT_MSG "SLOT_A"
111 #define PCMCIA_SLOT_MSG "SLOT_B"
114 #define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq))
116 static int pcmcia_schlvl = PCMCIA_SCHLVL;
118 /* ------------------------------------------------------------------------- */
120 #define PCMCIA_SOCKET_KEY_5V 1
121 #define PCMCIA_SOCKET_KEY_LV 2
124 /* look up table for pgcrx registers */
126 static u_int *m8xx_pgcrx[2] = {
127 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra,
128 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb
132 * This structure is used to address each window in the PCMCIA controller.
134 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
135 * after pcmcia_win_t[n]...
144 * For some reason the hardware guys decided to make both slots share
147 * Could someone invent object oriented hardware ?
149 * The macros are used to get the right bit from the registers.
154 #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
155 #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
156 #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
157 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
159 #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
160 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
161 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
162 #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
163 #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
164 #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
165 #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
166 #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
167 #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
168 #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
169 #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
171 #define M8XX_PGCRX(slot) (*m8xx_pgcrx[slot])
173 #define M8XX_PGCRX_CXOE 0x00000080
174 #define M8XX_PGCRX_CXRESET 0x00000040
176 /* we keep one lookup table per socket to check flags */
178 #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
185 typedef struct socket_info_t {
186 void (*handler)(void *info, u_int events);
191 socket_state_t state;
192 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
193 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
194 event_table_t events[PCMCIA_EVENTS_MAX];
197 static socket_info_t socket[PCMCIA_SOCKETS_NO];
199 static socket_cap_t capabilities = {
200 SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP, /* features -
202 memory windows must be
204 0x000, /* irq_mask - SIU_LEVEL 7 -> 0 */
205 0x1000, /* map_size - 4K minimum window size */
208 0 /* No PCI or CardBus support */
212 * Search this table to see if the windowsize is
216 #define M8XX_SIZES_NO 32
218 static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
219 { 0x00000001, 0x00000002, 0x00000008, 0x00000004,
220 0x00000080, 0x00000040, 0x00000010, 0x00000020,
221 0x00008000, 0x00004000, 0x00001000, 0x00002000,
222 0x00000100, 0x00000200, 0x00000800, 0x00000400,
224 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
225 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
226 0x00010000, 0x00020000, 0x00080000, 0x00040000,
227 0x00800000, 0x00400000, 0x00100000, 0x00200000 };
230 /* ------------------------------------------------------------------------- */
232 static void m8xx_interrupt(int irq, void *dev, struct pt_regs *regs);
234 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
236 /* ------------------------------------------------------------------------- */
237 /* board specific stuff: */
238 /* voltage_set(), hardware_enable() and hardware_disable() */
239 /* ------------------------------------------------------------------------- */
240 /* RPX Boards from Embedded Planet */
242 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
244 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
245 * SYPCR is write once only, therefore must the slowest memory be faster
246 * than the bus monitor or we will get a machine check due to the bus timeout.
249 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
251 #undef PCMCIA_BMT_LIMIT
252 #define PCMCIA_BMT_LIMIT (6*8)
254 static int voltage_set(int slot, int vcc, int vpp)
260 case 33: reg |= BCSR1_PCVCTL4; break;
261 case 50: reg |= BCSR1_PCVCTL5; break;
270 reg |= BCSR1_PCVCTL6;
275 reg |= BCSR1_PCVCTL7;
279 if(!((vcc == 50) || (vcc == 0)))
282 /* first, turn off all power */
284 *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5
285 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7);
287 /* enable new powersettings */
289 *((uint *)RPX_CSR_ADDR) |= reg;
294 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
295 #define hardware_enable(_slot_) /* No hardware to enable */
296 #define hardware_disable(_slot_) /* No hardware to disable */
298 #endif /* CONFIG_RPXCLASSIC */
300 /* ------------------------------------------------------------------------- */
301 /* FADS Boards from Motorola */
303 #if defined(CONFIG_FADS)
305 #define PCMCIA_BOARD_MSG "FADS"
307 static int voltage_set(int slot, int vcc, int vpp)
313 case 33: reg |= BCSR1_PCCVCC0; break;
314 case 50: reg |= BCSR1_PCCVCC1; break;
323 reg |= BCSR1_PCCVPP1;
328 if ((vcc == 33) || (vcc == 50))
329 reg |= BCSR1_PCCVPP0;
335 /* first, turn off all power */
336 *((uint *)BCSR1) &= ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK);
338 /* enable new powersettings */
339 *((uint *)BCSR1) |= reg;
344 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
346 static void hardware_enable(int slot)
348 *((uint *)BCSR1) &= ~BCSR1_PCCEN;
351 static void hardware_disable(int slot)
353 *((uint *)BCSR1) |= BCSR1_PCCEN;
358 /* ------------------------------------------------------------------------- */
359 /* Motorola MBX860 */
361 #if defined(CONFIG_MBX)
363 #define PCMCIA_BOARD_MSG "MBX"
365 static int voltage_set(int slot, int vcc, int vpp)
367 unsigned char reg = 0;
371 case 33: reg |= CSR2_VCC_33; break;
372 case 50: reg |= CSR2_VCC_50; break;
386 if ((vcc == 33) || (vcc == 50))
393 /* first, turn off all power */
394 *((unsigned char *)MBX_CSR2_ADDR) &= ~(CSR2_VCC_MASK | CSR2_VPP_MASK);
396 /* enable new powersettings */
397 *((unsigned char *)MBX_CSR2_ADDR) |= reg;
402 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
403 #define hardware_enable(_slot_) /* No hardware to enable */
404 #define hardware_disable(_slot_) /* No hardware to disable */
406 #endif /* CONFIG_MBX */
408 /* ------------------------------------------------------------------------- */
410 static void m8xx_shutdown(void)
416 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
419 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr =
420 M8XX_PCMCIA_MASK(_slot_);
421 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
422 &= ~M8XX_PCMCIA_MASK(_slot_);
424 /* turn off interrupt and disable CxOE */
426 M8XX_PGCRX(_slot_) = M8XX_PGCRX_CXOE;
428 /* turn off memory windows */
430 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
431 w->or = 0; /* set to not valid */
435 /* turn off voltage */
437 voltage_set(_slot_, 0, 0);
439 /* disable external hardware */
441 hardware_disable(_slot_);
443 free_irq(pcmcia_schlvl, NULL);
447 /* ------------------------------------------------------------------------- */
449 /* ------------------------------------------------------------------------- */
451 static u_int pending_events[PCMCIA_SOCKETS_NO];
452 static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED;
454 static void m8xx_pcmcia_bh(void *dummy)
459 for (i=0; i < PCMCIA_SOCKETS_NO; i++) {
460 spin_lock_irq(&pending_event_lock);
461 events = pending_events[i];
462 pending_events[i] = 0;
463 spin_unlock_irq(&pending_event_lock);
465 SS_DETECT events need a small delay here. The reason for this is that
466 the "is there a card" electronics need time to see the card after the
467 "we have a card coming in" electronics have seen it.
469 if (events & SS_DETECT)
471 if (socket[i].handler)
472 socket[i].handler(socket[i].info, events);
476 static struct tq_struct m8xx_pcmcia_task = {
477 routine: m8xx_pcmcia_bh
481 static void m8xx_interrupt(int irq, void *dev, struct pt_regs *regs)
485 u_int events, pscr, pipr;
487 DEBUG(3,"Interrupt!\n");
489 /* get interrupt sources */
491 pscr = ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr;
492 pipr = ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr;
503 events |= e->eventbit;
509 * report only if both card detect signals are the same
511 * we depend on that CD2 is the bit to the left of CD1...
514 if(events & SS_DETECT)
515 if(((pipr & M8XX_PCMCIA_CD2(_slot_)) >> 1)
516 ^ (pipr & M8XX_PCMCIA_CD1(_slot_)))
517 events &= ~SS_DETECT;
519 #ifdef PCMCIA_GLITCHY_CD
522 * I've experienced CD problems with my ADS board.
523 * We make an extra check to see if there was a
524 * real change of Card detection.
527 if((events & SS_DETECT) &&
529 (M8XX_PCMCIA_CD2(_slot_) | M8XX_PCMCIA_CD1(_slot_)))
530 == 0) && (s->state.Vcc | s->state.Vpp)) {
531 events &= ~SS_DETECT;
532 printk( "CD glitch workaround - CD = 0x%08x!\n",
533 (pipr & (M8XX_PCMCIA_CD2(_slot_)
534 | M8XX_PCMCIA_CD1(_slot_))));
538 /* call the handler */
540 DEBUG(3,"slot %u: events = 0x%02x, pscr = 0x%08x, "
542 _slot_, events, pscr, pipr);
545 spin_lock(&pending_event_lock);
546 pending_events[0] |= events;
547 spin_unlock(&pending_event_lock);
548 schedule_task(&m8xx_pcmcia_task);
554 /* clear the interrupt sources */
556 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr = pscr;
558 DEBUG(3,"Interrupt done.\n");
562 /* ------------------------------------------------------------------------- */
564 static u_int m8xx_get_graycode(u_int size)
568 for(k = 0; k < M8XX_SIZES_NO; k++)
569 if(m8xx_size_to_gray[k] == size)
572 if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
578 /* ------------------------------------------------------------------------- */
580 static u_int m8xx_get_speed(u_int ns, u_int is_io)
582 u_int reg, clocks, psst, psl, psht;
587 * We get called with IO maps setup to 0ns
588 * if not specified by the user.
589 * They should be 255ns.
595 ns = 100; /* fast memory if 0 */
599 * In PSST, PSL, PSHT fields we tell the controller
600 * timing parameters in CLKOUT clock cycles.
601 * CLKOUT is the same as GCLK2_50.
604 /* how we want to adjust the timing - in percent */
606 #define ADJ 180 /* 80 % longer accesstime - to be sure */
609 clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
610 clocks = (clocks * ADJ) / (100*1000);
611 if(clocks >= PCMCIA_BMT_LIMIT) {
612 printk( "Max access time limit reached\n");
613 clocks = PCMCIA_BMT_LIMIT-1;
616 psst = clocks / 7; /* setup time */
617 psht = clocks / 7; /* hold time */
618 psl = (clocks * 5) / 7; /* strobe length */
620 psst += clocks - (psst + psht + psl);
629 /* ------------------------------------------------------------------------- */
631 static int m8xx_register_callback(unsigned int sock, void (*handler)(void *, unsigned int), void * info)
633 socket[sock].handler = handler;
634 socket[sock].info = info;
635 if (handler == NULL) {
644 /* ------------------------------------------------------------------------- */
646 static int m8xx_get_status(unsigned int lsock, u_int *value)
648 socket_info_t *s = &socket[lsock];
652 pipr = ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr;
654 *value = ((pipr & (M8XX_PCMCIA_CD1(_slot_)
655 | M8XX_PCMCIA_CD2(_slot_))) == 0) ? SS_DETECT : 0;
656 *value |= (pipr & M8XX_PCMCIA_WP(_slot_)) ? SS_WRPROT : 0;
658 if (s->state.flags & SS_IOCARD)
659 *value |= (pipr & M8XX_PCMCIA_BVD1(_slot_)) ? SS_STSCHG : 0;
661 *value |= (pipr & M8XX_PCMCIA_RDY(_slot_)) ? SS_READY : 0;
662 *value |= (pipr & M8XX_PCMCIA_BVD1(_slot_)) ? SS_BATDEAD : 0;
663 *value |= (pipr & M8XX_PCMCIA_BVD2(_slot_)) ? SS_BATWARN : 0;
666 if (s->state.Vcc | s->state.Vpp)
667 *value |= SS_POWERON;
671 * This driver only supports 16-Bit pc-cards.
672 * Cardbus is not handled here.
674 * To determine what voltage to use we must read the VS1 and VS2 pin.
675 * Depending on what socket type is present,
676 * different combinations mean different things.
678 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
680 * 5V 5V, LV* NC NC 5V only 5V (if available)
682 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
684 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
686 * LV* 5V - - shall not fit into socket
688 * LV* LV* GND NC 3.3V only 3.3V
690 * LV* LV* NC GND x.xV x.xV (if avail.)
692 * LV* LV* GND GND 3.3 or x.xV as low as possible
694 * *LV means Low Voltage
697 * That gives us the following table:
699 * Socket VS1 VS2 Voltage
702 * 5V NC GND none (should not be possible)
706 * LV NC NC 5V (if available)
707 * LV NC GND x.xV (if available)
711 * So, how do I determine if I have a 5V or a LV
712 * socket on my board? Look at the socket!
715 * Socket with 5V key:
716 * ++--------------------------------------------+
721 * +---------------------------------------------+
723 * Socket with LV key:
724 * ++--------------------------------------------+
729 * +---------------------------------------------+
732 * With other words - LV only cards does not fit
733 * into the 5V socket!
736 /* read out VS1 and VS2 */
738 reg = (pipr & M8XX_PCMCIA_VS_MASK(_slot_))
739 >> M8XX_PCMCIA_VS_SHIFT(_slot_);
741 if(socket_get(_slot_) == PCMCIA_SOCKET_KEY_LV) {
743 case 1: *value |= SS_3VCARD; break; /* GND, NC - 3.3V only */
744 case 2: *value |= SS_XVCARD; break; /* NC. GND - x.xV only */
748 DEBUG(3,"GetStatus(%d) = %#2.2x\n", lsock, *value);
752 /* ------------------------------------------------------------------------- */
754 static int m8xx_inquire_socket(unsigned int lsock, socket_cap_t *cap)
761 /* ------------------------------------------------------------------------- */
763 static int m8xx_get_socket(unsigned int lsock, socket_state_t *state)
765 *state = socket[lsock].state; /* copy the whole structure */
767 DEBUG(3,"GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
768 "io_irq %d, csc_mask %#2.2x\n", lsock, state->flags,
769 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
773 /* ------------------------------------------------------------------------- */
775 static int m8xx_set_socket(unsigned int lsock, socket_state_t *state)
777 socket_info_t *s = &socket[lsock];
782 DEBUG(3, "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
783 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
784 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
786 /* First, set voltage - bail out if invalid */
788 if(voltage_set(_slot_, state->Vcc, state->Vpp))
792 /* Take care of reset... */
794 if(state->flags & SS_RESET)
795 M8XX_PGCRX(_slot_) |= M8XX_PGCRX_CXRESET; /* active high */
797 M8XX_PGCRX(_slot_) &= ~M8XX_PGCRX_CXRESET;
799 /* ... and output enable. */
801 /* The CxOE signal is connected to a 74541 on the ADS.
802 I guess most other boards used the ADS as a reference.
803 I tried to control the CxOE signal with SS_OUTPUT_ENA,
804 but the reset signal seems connected via the 541.
805 If the CxOE is left high are some signals tristated and
806 no pullups are present -> the cards act wierd.
807 So right now the buffers are enabled if the power is on. */
809 if(state->Vcc || state->Vpp)
810 M8XX_PGCRX(_slot_) &= ~M8XX_PGCRX_CXOE; /* active low */
812 M8XX_PGCRX(_slot_) |= M8XX_PGCRX_CXOE;
815 * We'd better turn off interrupts before
816 * we mess with the events-table..
823 * Play around with the interrupt mask to be able to
824 * give the events the generic pcmcia driver wants us to.
830 if(state->csc_mask & SS_DETECT) {
831 e->eventbit = SS_DETECT;
832 reg |= e->regbit = (M8XX_PCMCIA_CD2(_slot_)
833 | M8XX_PCMCIA_CD1(_slot_));
837 if(state->flags & SS_IOCARD) {
843 if(state->csc_mask & SS_STSCHG) {
844 e->eventbit = SS_STSCHG;
845 reg |= e->regbit = M8XX_PCMCIA_BVD1(_slot_);
851 * If io_irq is non-zero we should enable irq.
855 M8XX_PGCRX(_slot_) |=
856 mk_int_int_mask(state->io_irq) << 24;
859 * Strange thing here:
860 * The manual does not tell us which interrupt
861 * the sources generate.
862 * Anyhow, I found out that RDY_L generates IREQLVL.
864 * We use level triggerd interrupts, and they don't
865 * have to be cleared in PSCR in the interrupt handler.
868 reg |= M8XX_PCMCIA_RDY_L(_slot_);
871 M8XX_PGCRX(_slot_) &= 0x00ffffff;
880 if(state->csc_mask & SS_BATDEAD) {
881 e->eventbit = SS_BATDEAD;
882 reg |= e->regbit = M8XX_PCMCIA_BVD1(_slot_);
886 if(state->csc_mask & SS_BATWARN) {
887 e->eventbit = SS_BATWARN;
888 reg |= e->regbit = M8XX_PCMCIA_BVD2(_slot_);
892 /* What should I trigger on - low/high,raise,fall? */
893 if(state->csc_mask & SS_READY) {
894 e->eventbit = SS_READY;
895 reg |= e->regbit = 0; //??
900 e->regbit = 0; /* terminate list */
903 * Clear the status changed .
904 * Port A and Port B share the same port.
905 * Writing ones will clear the bits.
908 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr = reg;
912 * Port A and Port B share the same port.
913 * Need for read-modify-write.
914 * Ones will enable the interrupt.
917 reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
918 & M8XX_PCMCIA_MASK(_slot_);
920 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per = reg;
922 restore_flags(flags);
924 /* copy the struct and modify the copy */
931 /* ------------------------------------------------------------------------- */
933 static int m8xx_get_io_map(unsigned int lsock, struct pccard_io_map *io)
935 if(io->map >= PCMCIA_IO_WIN_NO)
938 *io = socket[lsock].io_win[io->map]; /* copy the struct */
940 DEBUG(3,"GetIOMap(%d, %d) = %#2.2x, %d ns, "
941 "%#4.4x-%#4.4x\n", lsock, io->map, io->flags,
942 io->speed, io->start, io->stop);
946 /* ------------------------------------------------------------------------- */
948 static int m8xx_set_io_map(unsigned int lsock, struct pccard_io_map *io)
950 socket_info_t *s = &socket[lsock];
955 #define M8XX_SIZE (io->stop - io->start + 1)
956 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
958 DEBUG(3, "SetIOMap(%d, %d, %#2.2x, %d ns, "
959 "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
960 io->speed, io->start, io->stop);
962 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
963 || (io->stop > 0xffff) || (io->stop < io->start))
966 if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
969 if(io->flags & MAP_ACTIVE) {
971 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
972 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
974 /* setup registers */
976 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
979 w->or = 0; /* turn off window first */
983 reg |= 0x00018 + (_slot_ << 2);
985 reg |= m8xx_get_speed(io->speed, 1);
987 if(io->flags & MAP_WRPROT)
990 if(io->flags & (MAP_16BIT | MAP_AUTOSZ))
993 if(io->flags & MAP_ACTIVE)
998 DEBUG(3,"Socket %u: Mapped io window %u at %#8.8x, "
999 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1003 /* copy the struct and modify the copy */
1005 s->io_win[io->map] = *io;
1006 s->io_win[io->map].flags &= (MAP_WRPROT
1012 /* ------------------------------------------------------------------------- */
1014 static int m8xx_get_mem_map(unsigned int lsock, struct pccard_mem_map *mem)
1016 if(mem->map >= PCMCIA_MEM_WIN_NO)
1019 *mem = socket[lsock].mem_win[mem->map]; /* copy the struct */
1021 DEBUG(3, "GetMemMap(%d, %d) = %#2.2x, %d ns, "
1022 "%#5.5lx-%#5.5lx, %#5.5x\n", lsock, mem->map, mem->flags,
1023 mem->speed, mem->sys_start, mem->sys_stop, mem->card_start);
1027 /* ------------------------------------------------------------------------- */
1029 static int m8xx_set_mem_map(unsigned int lsock, struct pccard_mem_map *mem)
1031 socket_info_t *s = &socket[lsock];
1033 struct pccard_mem_map *old;
1036 DEBUG(3, "SetMemMap(%d, %d, %#2.2x, %d ns, "
1037 "%#5.5lx-%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1038 mem->speed, mem->sys_start, mem->sys_stop, mem->card_start);
1040 if ((mem->map >= PCMCIA_MEM_WIN_NO) || (mem->sys_start > mem->sys_stop)
1041 || ((mem->sys_stop - mem->sys_start) >= PCMCIA_MEM_WIN_SIZE)
1042 || (mem->card_start >= 0x04000000)
1043 || (mem->sys_start & 0xfff) /* 4KByte resolution */
1044 || (mem->card_start & 0xfff))
1047 if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1048 printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1052 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1054 /* Setup the window in the pcmcia controller */
1056 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1062 reg |= m8xx_get_speed(mem->speed, 0);
1064 if(mem->flags & MAP_ATTRIB)
1067 if(mem->flags & MAP_WRPROT)
1070 if(mem->flags & MAP_16BIT)
1073 if(mem->flags & MAP_ACTIVE)
1078 DEBUG(3, "Socket %u: Mapped memory window %u at %#8.8x, "
1079 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1081 if(mem->flags & MAP_ACTIVE) {
1083 mem->sys_stop -= mem->sys_start;
1085 /* get the new base address */
1087 mem->sys_start = PCMCIA_MEM_WIN_BASE +
1088 (PCMCIA_MEM_WIN_SIZE * winnr)
1091 mem->sys_stop += mem->sys_start;
1094 DEBUG(3, "SetMemMap(%d, %d, %#2.2x, %d ns, "
1095 "%#5.5lx-%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1096 mem->speed, mem->sys_start, mem->sys_stop, mem->card_start);
1098 /* copy the struct and modify the copy */
1100 old = &s->mem_win[mem->map];
1103 old->flags &= (MAP_ATTRIB
1111 static int m8xx_sock_init(unsigned int s)
1114 pccard_io_map io = { 0, 0, 0, 0, 1 };
1115 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1117 DEBUG(3, "sock_init(%d)\n", s);
1119 mem.sys_stop = 0x1000;
1120 m8xx_set_socket(s, &dead_socket);
1121 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1123 m8xx_set_io_map(s, &io);
1125 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1127 m8xx_set_mem_map(s, &mem);
1134 static int m8xx_suspend(unsigned int s)
1136 return(m8xx_set_socket(s, &dead_socket));
1138 static void m8xx_proc_setup(unsigned int sock, struct proc_dir_entry *base)
1141 /* ------------------------------------------------------------------------- */
1143 static struct pccard_operations m8xx_services = {
1146 &m8xx_register_callback,
1147 &m8xx_inquire_socket,
1158 static int __init m8xx_init(void)
1164 PCMCIA_INFO("%s\n", version);
1165 CardServices(GetCardServicesInfo, &serv);
1166 if (serv.Revision != CS_RELEASE_CODE) {
1167 PCMCIA_ERROR("Card Services release does not match!\n");
1171 PCMCIA_INFO(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1172 " with IRQ %u.\n", pcmcia_schlvl);
1174 /* Configure Status change interrupt */
1176 if(request_8xxirq(pcmcia_schlvl, m8xx_interrupt, 0,
1177 "m8xx_pcmcia", NULL)) {
1178 PCMCIA_ERROR("Cannot allocate IRQ %u for SCHLVL!\n",
1184 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1186 socket[0].slot = _slot_;
1188 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr =
1189 M8XX_PCMCIA_MASK(_slot_);
1190 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
1191 &= ~M8XX_PCMCIA_MASK(_slot_);
1193 /* connect interrupt and disable CxOE */
1195 M8XX_PGCRX(_slot_) = M8XX_PGCRX_CXOE |
1196 (mk_int_int_mask(pcmcia_schlvl) << 16);
1198 /* intialize the fixed memory windows */
1200 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1201 w->br = PCMCIA_MEM_WIN_BASE +
1202 (PCMCIA_MEM_WIN_SIZE
1203 * (m + 0 * PCMCIA_MEM_WIN_NO));
1205 w->or = 0; /* set to not valid */
1207 DEBUG(3,"Socket %u: MemWin %u: Base 0x%08x.\n",
1213 /* turn off voltage */
1214 voltage_set(_slot_, 0, 0);
1216 /* Enable external hardware */
1217 hardware_enable(_slot_);
1219 if(register_ss_entry(PCMCIA_SOCKETS_NO, &m8xx_services) != 0) {
1220 PCMCIA_ERROR("register_ss_entry() failed.\n");
1228 static void __exit m8xx_exit(void)
1230 unregister_ss_entry(&m8xx_services);
1235 module_init(m8xx_init);
1236 module_exit(m8xx_exit);