2 * ti113x.h 1.16 1999/10/25 20:03:34
4 * The contents of this file are subject to the Mozilla Public License
5 * Version 1.1 (the "License"); you may not use this file except in
6 * compliance with the License. You may obtain a copy of the License
7 * at http://www.mozilla.org/MPL/
9 * Software distributed under the License is distributed on an "AS IS"
10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
11 * the License for the specific language governing rights and
12 * limitations under the License.
14 * The initial developer of the original code is David A. Hinds
15 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
16 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
18 * Alternatively, the contents of this file may be used under the
19 * terms of the GNU General Public License version 2 (the "GPL"), in which
20 * case the provisions of the GPL are applicable instead of the
21 * above. If you wish to allow the use of your version of this file
22 * only under the terms of the GPL and not to allow others to use
23 * your version of this file under the MPL, indicate your decision by
24 * deleting the provisions above and replace them with the notice and
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26 * provisions above, a recipient may use your version of this file
27 * under either the MPL or the GPL.
30 #ifndef _LINUX_TI113X_H
31 #define _LINUX_TI113X_H
33 #include <linux/config.h>
35 /* Register definitions for TI 113X PCI-to-CardBus bridges */
37 /* System Control Register */
38 #define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */
39 #define TI113X_SCR_SMIROUTE 0x04000000
40 #define TI113X_SCR_SMISTATUS 0x02000000
41 #define TI113X_SCR_SMIENB 0x01000000
42 #define TI113X_SCR_VCCPROT 0x00200000
43 #define TI113X_SCR_REDUCEZV 0x00100000
44 #define TI113X_SCR_CDREQEN 0x00080000
45 #define TI113X_SCR_CDMACHAN 0x00070000
46 #define TI113X_SCR_SOCACTIVE 0x00002000
47 #define TI113X_SCR_PWRSTREAM 0x00000800
48 #define TI113X_SCR_DELAYUP 0x00000400
49 #define TI113X_SCR_DELAYDOWN 0x00000200
50 #define TI113X_SCR_INTERROGATE 0x00000100
51 #define TI113X_SCR_CLKRUN_SEL 0x00000080
52 #define TI113X_SCR_PWRSAVINGS 0x00000040
53 #define TI113X_SCR_SUBSYSRW 0x00000020
54 #define TI113X_SCR_CB_DPAR 0x00000010
55 #define TI113X_SCR_CDMA_EN 0x00000008
56 #define TI113X_SCR_ASYNC_IRQ 0x00000004
57 #define TI113X_SCR_KEEPCLK 0x00000002
58 #define TI113X_SCR_CLKRUN_ENA 0x00000001
60 #define TI122X_SCR_SER_STEP 0xc0000000
61 #define TI122X_SCR_INTRTIE 0x20000000
62 #define TI122X_SCR_CBRSVD 0x00400000
63 #define TI122X_SCR_MRBURSTDN 0x00008000
64 #define TI122X_SCR_MRBURSTUP 0x00004000
65 #define TI122X_SCR_RIMUX 0x00000001
67 /* Multimedia Control Register */
68 #define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */
69 #define TI1250_MMC_ZVOUTEN 0x80
70 #define TI1250_MMC_PORTSEL 0x40
71 #define TI1250_MMC_ZVEN1 0x02
72 #define TI1250_MMC_ZVEN0 0x01
74 #define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */
75 #define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */
76 #define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */
77 #define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */
78 #define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */
79 #define TI122X_IRQMUX 0x008c /* 32 bit */
81 /* Retry Status Register */
82 #define TI113X_RETRY_STATUS 0x0090 /* 8 bit */
83 #define TI113X_RSR_PCIRETRY 0x80
84 #define TI113X_RSR_CBRETRY 0x40
85 #define TI113X_RSR_TEXP_CBB 0x20
86 #define TI113X_RSR_MEXP_CBB 0x10
87 #define TI113X_RSR_TEXP_CBA 0x08
88 #define TI113X_RSR_MEXP_CBA 0x04
89 #define TI113X_RSR_TEXP_PCI 0x02
90 #define TI113X_RSR_MEXP_PCI 0x01
92 /* Card Control Register */
93 #define TI113X_CARD_CONTROL 0x0091 /* 8 bit */
94 #define TI113X_CCR_RIENB 0x80
95 #define TI113X_CCR_ZVENABLE 0x40
96 #define TI113X_CCR_PCI_IRQ_ENA 0x20
97 #define TI113X_CCR_PCI_IREQ 0x10
98 #define TI113X_CCR_PCI_CSC 0x08
99 #define TI113X_CCR_SPKROUTEN 0x02
100 #define TI113X_CCR_IFG 0x01
102 #define TI1220_CCR_PORT_SEL 0x20
103 #define TI122X_CCR_AUD2MUX 0x04
105 /* Device Control Register */
106 #define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */
107 #define TI113X_DCR_5V_FORCE 0x40
108 #define TI113X_DCR_3V_FORCE 0x20
109 #define TI113X_DCR_IMODE_MASK 0x06
110 #define TI113X_DCR_IMODE_ISA 0x02
111 #define TI113X_DCR_IMODE_SERIAL 0x04
113 #define TI12XX_DCR_IMODE_PCI_ONLY 0x00
114 #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
116 /* Buffer Control Register */
117 #define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */
118 #define TI113X_BCR_CB_READ_DEPTH 0x08
119 #define TI113X_BCR_CB_WRITE_DEPTH 0x04
120 #define TI113X_BCR_PCI_READ_DEPTH 0x02
121 #define TI113X_BCR_PCI_WRITE_DEPTH 0x01
123 /* Diagnostic Register */
124 #define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */
125 #define TI1250_DIAG_TRUE_VALUE 0x80
126 #define TI1250_DIAG_PCI_IREQ 0x40
127 #define TI1250_DIAG_PCI_CSC 0x20
128 #define TI1250_DIAG_ASYNC_CSC 0x01
131 #define TI113X_DMA_0 0x0094 /* 32 bit */
132 #define TI113X_DMA_1 0x0098 /* 32 bit */
134 /* ExCA IO offset registers */
135 #define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
137 /* EnE test register */
138 #define ENE_TEST_C9 0xc9 /* 8bit */
139 #define ENE_TEST_C9_TLTENABLE 0x02
141 #ifdef CONFIG_CARDBUS
144 * Generic TI init - TI has an extension for the
145 * INTCTL register that sets the PCI CSC interrupt.
146 * Make sure we set it correctly at open and init
148 * - open: disable the PCI CSC interrupt. This makes
149 * it possible to use the CSC interrupt to probe the
151 * - init: set the interrupt to match our PCI state.
152 * This makes us correctly get PCI CSC interrupt
155 static int ti_open(pci_socket_t *socket)
157 u8 new, reg = exca_readb(socket, I365_INTCTL);
159 new = reg & ~I365_INTR_ENA;
161 exca_writeb(socket, I365_INTCTL, new);
164 * for EnE bridges only: clear testbit TLTEnable. this makes the
165 * RME Hammerfall DSP sound card working.
167 if (socket->dev->vendor == PCI_VENDOR_ID_ENE) {
168 u8 test_c9 = config_readb(socket, ENE_TEST_C9);
169 test_c9 &= ~ENE_TEST_C9_TLTENABLE;
170 config_writeb(socket, ENE_TEST_C9, test_c9);
176 static int ti_intctl(pci_socket_t *socket)
178 u8 new, reg = exca_readb(socket, I365_INTCTL);
180 new = reg & ~I365_INTR_ENA;
182 new |= I365_INTR_ENA;
184 exca_writeb(socket, I365_INTCTL, new);
187 * If ISA interrupts don't work, then fall back to routing card
188 * interrupts to the PCI interrupt of the socket.
190 * Tweaking this when we are using serial PCI IRQs causes hangs
193 if (!socket->cap.irq_mask) {
196 devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
197 if ((devctl & TI113X_DCR_IMODE_MASK) != TI12XX_DCR_IMODE_ALL_SERIAL) {
198 printk (KERN_INFO "ti113x: Routing card interrupts to PCI\n");
200 devctl &= ~TI113X_DCR_IMODE_MASK;
202 irqmux = config_readl(socket, TI122X_IRQMUX);
203 irqmux = (irqmux & ~0x0f) | 0x02; /* route INTA */
204 irqmux = (irqmux & ~0xf0) | 0x20; /* route INTB */
206 config_writel(socket, TI122X_IRQMUX, irqmux);
207 config_writeb(socket, TI113X_DEVICE_CONTROL, devctl);
215 * Zoom video control for TI122x/113x chips
218 static void ti_zoom_video(pci_socket_t *socket, int onoff)
222 /* If we don't have a Zoom Video switch this is harmless,
223 we just tristate the unused (ZV) lines */
224 reg = config_readb(socket, TI113X_CARD_CONTROL);
226 /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
227 reg |= TI113X_CCR_ZVENABLE;
229 reg &= ~TI113X_CCR_ZVENABLE;
230 config_writeb(socket, TI113X_CARD_CONTROL, reg);
234 * The 145x series can also use this. They have an additional
235 * ZV autodetect mode we don't use but don't actually need.
236 * FIXME: manual says its in func0 and func1 but disagrees with
237 * itself about this - do we need to force func0, if so we need
238 * to know a lot more about socket pairings in pci_socket than we
242 static void ti1250_zoom_video(pci_socket_t *socket, int onoff)
247 ti_zoom_video(socket, onoff);
249 reg = config_readb(socket, 0x84);
250 reg |= (1<<7); /* ZV bus enable */
252 if(PCI_FUNC(socket->dev->devfn)==1)
257 reg &= ~(1<<6); /* Clear select bit */
258 reg |= shift<<6; /* Favour our socket */
259 reg |= 1<<shift; /* Socket zoom video on */
263 reg &= ~(1<<6); /* Clear select bit */
264 reg |= (1^shift)<<6; /* Favour other socket */
265 reg &= ~(1<<shift); /* Socket zoon video off */
268 config_writeb(socket, 0x84, reg);
271 static void ti_set_zv(pci_socket_t *socket)
273 if(socket->dev->vendor == PCI_VENDOR_ID_TI)
275 switch(socket->dev->device)
277 /* There may be more .. */
278 case PCI_DEVICE_ID_TI_1220:
279 case PCI_DEVICE_ID_TI_1221:
280 case PCI_DEVICE_ID_TI_1225:
281 socket->zoom_video = ti_zoom_video;
283 case PCI_DEVICE_ID_TI_1250:
284 case PCI_DEVICE_ID_TI_1251A:
285 case PCI_DEVICE_ID_TI_1251B:
286 case PCI_DEVICE_ID_TI_1450:
287 socket->zoom_video = ti1250_zoom_video;
292 static int ti_init(pci_socket_t *socket)
300 static struct pci_socket_ops ti_ops = {
315 #define ti_sysctl(socket) ((socket)->private[0])
316 #define ti_cardctl(socket) ((socket)->private[1])
317 #define ti_devctl(socket) ((socket)->private[2])
319 static int ti113x_open(pci_socket_t *socket)
321 ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL);
322 ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL);
323 ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL);
325 ti_cardctl(socket) &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
327 ti_cardctl(socket) |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ;
332 static int ti113x_init(pci_socket_t *socket)
336 config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket));
337 config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket));
338 config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket));
343 static struct pci_socket_ops ti113x_ops = {
358 #define ti_diag(socket) ((socket)->private[0])
360 static int ti1250_open(pci_socket_t *socket)
362 ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC);
364 ti_diag(socket) &= ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ);
366 ti_diag(socket) |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
371 static int ti1250_init(pci_socket_t *socket)
375 config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket));
380 static struct pci_socket_ops ti1250_ops = {
395 #endif /* CONFIG_CARDBUS */
397 #endif /* _LINUX_TI113X_H */