1 /* $Id: dbri.c,v 1.27 2001/10/08 22:19:50 davem Exp $
2 * drivers/sbus/audio/dbri.c
4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
5 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
7 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
8 * on Sun SPARCstation 10, 20, LX and Voyager models.
10 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
11 * data time multiplexer with ISDN support (aka T7259)
12 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
13 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
15 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
16 * Sparc Technology Business (courtesy of Sun Support)
17 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
18 * available from the Lucent (formarly AT&T microelectronics) home
20 * - http://www.freesoft.org/Linux/DBRI/
21 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
22 * Interfaces: CHI, Audio In & Out, 2 bits parallel
23 * Documentation: from the Crystal Semiconductor home page.
25 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
26 * memory and a serial device (long pipes, nr 0-15) or between two serial
27 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
28 * device (short pipes).
29 * A timeslot defines the bit-offset and nr of bits read from a serial device.
30 * The timeslots are linked to 6 circular lists, one for each direction for
31 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
32 * (the second one is a monitor/tee pipe, valid only for serial input).
34 * The mmcodec is connected via the CHI bus and needs the data & some
35 * parameters (volume, balance, output selection) timemultiplexed in 8 byte
36 * chunks. It also has a control mode, which serves for audio format setting.
38 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
39 * the same CHI bus, so I thought perhaps it is possible to use the onboard
40 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
41 * audio devices. But the SUN HW group decided against it, at least on my
42 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
46 #include <linux/module.h>
47 #include <linux/kernel.h>
48 #include <linux/sched.h>
49 #include <linux/errno.h>
50 #include <linux/interrupt.h>
51 #include <linux/slab.h>
52 #include <linux/version.h>
53 #include <linux/delay.h>
54 #include <linux/soundcard.h>
55 #include <asm/openprom.h>
56 #include <asm/oplib.h>
57 #include <asm/system.h>
61 #include <asm/pgtable.h>
63 #include <asm/audioio.h>
66 #if defined(DBRI_ISDN)
67 #include "../../isdn/hisax/hisax.h"
68 #include "../../isdn/hisax/isdnl1.h"
69 #include "../../isdn/hisax/foreign.h"
76 #define dprintk(a, x) if(dbri_debug & a) printk x
84 static int dbri_debug = 0;
85 MODULE_PARM(dbri_debug, "i");
87 static int dbri_trace = 0;
88 MODULE_PARM(dbri_trace, "i");
89 #define tprintk(x) if(dbri_trace) printk x
91 static char *cmds[] = {
92 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
93 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
96 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (1 << 27) | value)
100 #define dprintk(a, x)
101 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (intr << 27) | value)
103 #endif /* DBRI_DEBUG */
107 #define MAX_DRIVERS 2 /* Increase this if need more than 2 DBRI's */
109 static struct sparcaudio_driver drivers[MAX_DRIVERS];
110 static int num_drivers = 0;
114 ****************************************************************************
115 ************** DBRI initialization and command synchronization *************
116 ****************************************************************************
118 Commands are sent to the DBRI by building a list of them in memory,
119 then writing the address of the first list item to DBRI register 8.
120 The list is terminated with a WAIT command, which can generate a
121 CPU interrupt if required.
123 Since the DBRI can run in parallel with the CPU, several means of
124 synchronization present themselves. The original scheme (Rudolf's)
125 was to set a flag when we "cmdlock"ed the DBRI, clear the flag when
126 an interrupt signaled completion, and wait on a wait_queue if a routine
127 attempted to cmdlock while the flag was set. The problems arose when
128 we tried to cmdlock from inside an interrupt handler, which might
129 cause scheduling in an interrupt (if we waited), etc, etc
131 A more sophisticated scheme might involve a circular command buffer
132 or an array of command buffers. A routine could fill one with
133 commands and link it onto a list. When a interrupt signaled
134 completion of the current command buffer, look on the list for
137 I've decided to implement something much simpler - after each command,
138 the CPU waits for the DBRI to finish the command by polling the P bit
139 in DBRI register 0. I've tried to implement this in such a way
140 that might make implementing a more sophisticated scheme easier.
142 Every time a routine wants to write commands to the DBRI, it must
143 first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
144 in return. After the commands have been writen, dbri_cmdsend() is
145 called with the final pointer value.
147 Something a little more clever is required if this code is ever run
152 static int dbri_locked = 0;
154 static volatile s32 *dbri_cmdlock(struct dbri *dbri)
157 printk("DBRI: Command buffer locked! (bug in driver)\n");
160 return &dbri->dma->cmd[0];
163 static void dbri_process_interrupt_buffer(struct dbri *);
165 static void dbri_cmdsend(struct dbri *dbri, volatile s32 *cmd, int pause)
167 int MAXLOOPS = 1000000;
168 int maxloops = MAXLOOPS;
172 for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
173 dprintk(D_CMD, ("DBRI cmd: %lx:%08x\n",
174 (unsigned long) ptr, *ptr));
180 if (dbri_locked != 0) {
181 printk("DBRI: Command buffer improperly locked! (bug in driver)\n");
182 } else if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS-1) {
183 printk("DBRI: Command buffer overflow! (bug in driver)\n");
186 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
187 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
189 sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
191 while ((--maxloops) > 0 &&
192 (sbus_readl(dbri->regs + REG0) & D_P))
195 printk("DBRI: Chip never completed command buffer\n");
197 while ((--maxloops) > 0 && (! dbri->wait_seen))
198 dbri_process_interrupt_buffer(dbri);
200 printk("DBRI: Chip never acked WAIT\n");
202 dprintk(D_INT, ("DBRI: Chip completed command "
204 MAXLOOPS - maxloops));
208 dprintk(D_INT, ("DBRI: NO PAUSE\n"));
212 restore_flags(flags);
215 static void dbri_reset(struct dbri *dbri)
219 dprintk(D_GEN, ("DBRI: reset 0:%x 2:%x 8:%x 9:%x\n",
220 sbus_readl(dbri->regs + REG0),
221 sbus_readl(dbri->regs + REG2),
222 sbus_readl(dbri->regs + REG8),
223 sbus_readl(dbri->regs + REG9)));
225 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
226 for(i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
230 static void dbri_detach(struct dbri *dbri)
233 free_irq(dbri->irq, dbri);
234 sbus_iounmap(dbri->regs, dbri->regs_size);
235 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
236 (void *)dbri->dma, dbri->dma_dvma);
240 static void dbri_initialize(struct dbri *dbri)
248 dprintk(D_GEN, ("DBRI: init: cmd: %p, int: %p\n",
249 &dbri->dma->cmd[0], &dbri->dma->intr[0]));
252 * Initialize the interrupt ringbuffer.
254 for(n = 0; n < DBRI_NO_INTS-1; n++) {
255 dma_addr = dbri->dma_dvma;
256 dma_addr += dbri_dma_off(intr, ((n+1) & DBRI_INT_BLK));
257 dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
259 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
260 dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
263 /* We should query the openprom to see what burst sizes this
264 * SBus supports. For now, just disable all SBus bursts */
265 tmp = sbus_readl(dbri->regs + REG0);
266 /* A brute approach - DBRI falls back to working burst size by itself
267 * On SS20 D_S does not work, so do not try so high. */
270 sbus_writel(tmp, dbri->regs + REG0);
273 * Set up the interrupt queue
275 cmd = dbri_cmdlock(dbri);
276 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
277 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
280 dbri_cmdsend(dbri, cmd, 1);
285 ****************************************************************************
286 *************************** DBRI interrupt handler *************************
287 ****************************************************************************
289 The DBRI communicates with the CPU mainly via a circular interrupt
290 buffer. When an interrupt is signaled, the CPU walks through the
291 buffer and calls dbri_process_one_interrupt() for each interrupt word.
292 Complicated interrupts are handled by dedicated functions (which
293 appear first in this file). Any pending interrupts can be serviced by
294 calling dbri_process_interrupt_buffer(), which works even if the CPU's
295 interrupts are disabled. This function is used by dbri_cmdsend()
296 to make sure we're synced up with the chip after each command sequence,
297 even if we're running cli'ed.
303 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
304 * So we have to reverse the bits. Note: not all bit lengths are supported
306 static __u32 reverse_bytes(__u32 b, int len)
310 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
312 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
314 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
316 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
318 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
323 printk("DBRI reverse_bytes: unsupported length\n");
329 /* transmission_complete_intr()
331 * Called by main interrupt handler when DBRI signals transmission complete
332 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
334 * Walks through the pipe's list of transmit buffer descriptors, releasing
335 * each one's DMA buffer (if present), flagging the descriptor available,
336 * and signaling its callback routine (if present), before proceeding
337 * to the next one. Stops when the first descriptor is found without
338 * TBC (Transmit Buffer Complete) set, or we've run through them all.
341 static void transmission_complete_intr(struct dbri *dbri, int pipe)
346 void (*callback)(void *, int);
349 td = dbri->pipes[pipe].desc;
352 if (td >= DBRI_NO_DESCS) {
353 printk("DBRI: invalid td on pipe %d\n", pipe);
357 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
359 if (! (status & DBRI_TD_TBC)) {
363 dprintk(D_INT, ("DBRI: TD %d, status 0x%02x\n", td, status));
365 buffer = dbri->descs[td].buffer;
367 sbus_unmap_single(dbri->sdev,
368 dbri->descs[td].buffer_dvma,
372 callback = dbri->descs[td].output_callback;
373 callback_arg = dbri->descs[td].output_callback_arg;
375 dbri->descs[td].inuse = 0;
377 td = dbri->descs[td].next;
378 dbri->pipes[pipe].desc = td;
380 if (callback != NULL)
381 callback(callback_arg, status & 0xe);
385 static void reception_complete_intr(struct dbri *dbri, int pipe)
387 int rd = dbri->pipes[pipe].desc;
390 void (*callback)(void *, int, unsigned int);
392 if (rd < 0 || rd >= DBRI_NO_DESCS) {
393 printk("DBRI: invalid rd on pipe %d\n", pipe);
397 dbri->descs[rd].inuse = 0;
398 dbri->pipes[pipe].desc = dbri->descs[rd].next;
399 status = dbri->dma->desc[rd].word1;
401 buffer = dbri->descs[rd].buffer;
403 sbus_unmap_single(dbri->sdev,
404 dbri->descs[rd].buffer_dvma,
406 SBUS_DMA_FROMDEVICE);
408 callback = dbri->descs[rd].input_callback;
409 if (callback != NULL)
410 callback(dbri->descs[rd].input_callback_arg,
411 DBRI_RD_STATUS(status),
412 DBRI_RD_CNT(status)-2);
414 dprintk(D_INT, ("DBRI: Recv RD %d, status 0x%02x, len %d\n",
415 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)));
418 static void dbri_process_one_interrupt(struct dbri *dbri, int x)
420 int val = D_INTR_GETVAL(x);
421 int channel = D_INTR_GETCHAN(x);
422 int command = D_INTR_GETCMD(x);
423 int code = D_INTR_GETCODE(x);
424 int rval = D_INTR_GETRVAL(x);
426 if (channel == D_INTR_CMD) {
427 dprintk(D_INT,("DBRI: INTR: Command: %-5s Value:%d\n",
428 cmds[command], val));
430 dprintk(D_INT,("DBRI: INTR: Chan:%d Code:%d Val:%#x\n",
431 channel, code, rval));
434 if (channel == D_INTR_CMD && command == D_WAIT)
437 if (code == D_INTR_SBRI) {
438 /* SBRI - BRI status change */
439 const int liu_states[] = {1, 0, 8, 3, 4, 5, 6, 7};
441 dbri->liu_state = liu_states[val & 0x7];
442 if (dbri->liu_callback)
443 dbri->liu_callback(dbri->liu_callback_arg);
446 if (code == D_INTR_BRDY)
447 reception_complete_intr(dbri, channel);
449 if (code == D_INTR_XCMP)
450 transmission_complete_intr(dbri, channel);
452 if (code == D_INTR_UNDR) {
453 /* UNDR - Transmission underrun
454 * resend SDP command with clear pipe bit (C) set
458 int td = dbri->pipes[pipe].desc;
460 dbri->dma->desc[td].word4 = 0;
462 cmd = dbri_cmdlock(dbri);
463 *(cmd++) = DBRI_CMD(D_SDP, 0,
464 dbri->pipes[pipe].sdp
465 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
466 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
467 dbri_cmdsend(dbri, cmd, 1);
470 if (code == D_INTR_FXDT) {
471 /* FXDT - Fixed data change */
472 if (dbri->pipes[channel].sdp & D_SDP_MSB)
473 val = reverse_bytes(val, dbri->pipes[channel].length);
475 if (dbri->pipes[channel].recv_fixed_ptr)
476 *(dbri->pipes[channel].recv_fixed_ptr) = val;
480 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
481 * buffer until it finds a zero word (indicating nothing more to do
482 * right now). Non-zero words require processing and are handed off
483 * to dbri_process_one_interrupt AFTER advancing the pointer. This
484 * order is important since we might recurse back into this function
485 * and need to make sure the pointer has been advanced first.
487 static void dbri_process_interrupt_buffer(struct dbri *dbri)
491 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
492 dbri->dma->intr[dbri->dbri_irqp] = 0;
494 if (dbri->dbri_irqp == (DBRI_NO_INTS * DBRI_INT_BLK))
496 else if ((dbri->dbri_irqp & (DBRI_INT_BLK-1)) == 0)
499 tprintk(("dbri->dbri_irqp == %d\n", dbri->dbri_irqp));
500 dbri_process_one_interrupt(dbri, x);
504 static void dbri_intr(int irq, void *opaque, struct pt_regs *regs)
506 struct dbri *dbri = (struct dbri *) opaque;
510 * Read it, so the interrupt goes away.
512 x = sbus_readl(dbri->regs + REG1);
514 dprintk(D_INT, ("DBRI: Interrupt! (reg1=0x%08x)\n", x));
516 if (x & (D_MRR|D_MLE|D_LBG|D_MBE)) {
519 if(x & D_MRR) printk("DBRI: Multiple Error Ack on SBus\n");
520 if(x & D_MLE) printk("DBRI: Multiple Late Error on SBus\n");
521 if(x & D_LBG) printk("DBRI: Lost Bus Grant on SBus\n");
522 if(x & D_MBE) printk("DBRI: Burst Error on SBus\n");
524 /* Some of these SBus errors cause the chip's SBus circuitry
525 * to be disabled, so just re-enable and try to keep going.
527 * The only one I've seen is MRR, which will be triggered
528 * if you let a transmit pipe underrun, then try to CDP it.
530 * If these things persist, we should probably reset
531 * and re-init the chip.
533 tmp = sbus_readl(dbri->regs + REG0);
535 sbus_writel(tmp, dbri->regs + REG0);
539 if (!(x & D_IR)) /* Not for us */
543 dbri_process_interrupt_buffer(dbri);
548 ****************************************************************************
549 ************************** DBRI data pipe management ***********************
550 ****************************************************************************
552 While DBRI control functions use the command and interrupt buffers, the
553 main data path takes the form of data pipes, which can be short (command
554 and interrupt driven), or long (attached to DMA buffers). These functions
555 provide a rudimentary means of setting up and managing the DBRI's pipes,
556 but the calling functions have to make sure they respect the pipes' linked
557 list ordering, among other things. The transmit and receive functions
558 here interface closely with the transmit and receive interrupt code.
561 static int pipe_active(struct dbri *dbri, int pipe)
563 return (dbri->pipes[pipe].desc != -1);
567 /* reset_pipe(dbri, pipe)
569 * Called on an in-use pipe to clear anything being transmitted or received
571 static void reset_pipe(struct dbri *dbri, int pipe)
577 if (pipe < 0 || pipe > 31) {
578 printk("DBRI: reset_pipe called with illegal pipe number\n");
582 sdp = dbri->pipes[pipe].sdp;
584 printk("DBRI: reset_pipe called on uninitialized pipe\n");
588 cmd = dbri_cmdlock(dbri);
589 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
591 dbri_cmdsend(dbri, cmd, 1);
593 desc = dbri->pipes[pipe].desc;
595 void *buffer = dbri->descs[desc].buffer;
596 void (*output_callback) (void *, int)
597 = dbri->descs[desc].output_callback;
598 void *output_callback_arg
599 = dbri->descs[desc].output_callback_arg;
600 void (*input_callback) (void *, int, unsigned int)
601 = dbri->descs[desc].input_callback;
602 void *input_callback_arg
603 = dbri->descs[desc].input_callback_arg;
606 sbus_unmap_single(dbri->sdev,
607 dbri->descs[desc].buffer_dvma,
608 dbri->descs[desc].len,
609 output_callback != NULL ? SBUS_DMA_TODEVICE
610 : SBUS_DMA_FROMDEVICE);
612 dbri->descs[desc].inuse = 0;
613 desc = dbri->descs[desc].next;
616 output_callback(output_callback_arg, -1);
619 input_callback(input_callback_arg, -1, 0);
622 dbri->pipes[pipe].desc = -1;
625 static void setup_pipe(struct dbri *dbri, int pipe, int sdp)
627 if (pipe < 0 || pipe > 31) {
628 printk("DBRI: setup_pipe called with illegal pipe number\n");
632 if ((sdp & 0xf800) != sdp) {
633 printk("DBRI: setup_pipe called with strange SDP value\n");
637 /* If this is a fixed receive pipe, arrange for an interrupt
638 * every time its data changes
640 if (D_SDP_MODE(sdp) == D_SDP_FIXED && ! (sdp & D_SDP_TO_SER))
644 dbri->pipes[pipe].sdp = sdp;
645 dbri->pipes[pipe].desc = -1;
647 reset_pipe(dbri, pipe);
650 static void link_time_slot(struct dbri *dbri, int pipe,
651 enum in_or_out direction, int basepipe,
652 int length, int cycle)
659 if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) {
660 printk("DBRI: link_time_slot called with illegal pipe number\n");
664 if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
665 printk("DBRI: link_time_slot called on uninitialized pipe\n");
669 /* Deal with CHI special case:
670 * "If transmission on edges 0 or 1 is desired, then cycle n
671 * (where n = # of bit times per frame...) must be used."
672 * - DBRI data sheet, page 11
674 if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
675 cycle = dbri->chi_bpf;
677 if (basepipe == pipe) {
681 /* We're not initializing a new linked list (basepipe != pipe),
682 * so run through the linked list and find where this pipe
683 * should be sloted in, based on its cycle. CHI confuses
684 * things a bit, since it has a single anchor for both its
685 * transmit and receive lists.
687 if (basepipe == 16) {
688 if (direction == PIPEinput) {
689 prevpipe = dbri->chi_in_pipe;
691 prevpipe = dbri->chi_out_pipe;
697 nextpipe = dbri->pipes[prevpipe].nextpipe;
699 while (dbri->pipes[nextpipe].cycle < cycle
700 && dbri->pipes[nextpipe].nextpipe != basepipe) {
702 nextpipe = dbri->pipes[nextpipe].nextpipe;
706 if (prevpipe == 16) {
707 if (direction == PIPEinput) {
708 dbri->chi_in_pipe = pipe;
710 dbri->chi_out_pipe = pipe;
713 dbri->pipes[prevpipe].nextpipe = pipe;
716 dbri->pipes[pipe].nextpipe = nextpipe;
717 dbri->pipes[pipe].cycle = cycle;
718 dbri->pipes[pipe].length = length;
720 cmd = dbri_cmdlock(dbri);
722 if (direction == PIPEinput) {
723 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
724 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
725 *(cmd++) = D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
728 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
729 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
731 *(cmd++) = D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
734 dbri_cmdsend(dbri, cmd, 1);
737 /* I don't use this function, so it's basically untested. */
738 static void unlink_time_slot(struct dbri *dbri, int pipe,
739 enum in_or_out direction, int prevpipe,
745 if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) {
746 printk("DBRI: unlink_time_slot called with illegal pipe number\n");
750 cmd = dbri_cmdlock(dbri);
752 if (direction == PIPEinput) {
753 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
754 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
755 *(cmd++) = D_TS_NEXT(nextpipe);
758 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
759 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
761 *(cmd++) = D_TS_NEXT(nextpipe);
764 dbri_cmdsend(dbri, cmd, 1);
767 /* xmit_fixed() / recv_fixed()
769 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
770 * expected to change much, and which we don't need to buffer.
771 * The DBRI only interrupts us when the data changes (receive pipes),
772 * or only changes the data when this function is called (transmit pipes).
773 * Only short pipes (numbers 16-31) can be used in fixed data mode.
775 * These function operate on a 32-bit field, no matter how large
776 * the actual time slot is. The interrupt handler takes care of bit
777 * ordering and alignment. An 8-bit time slot will always end up
778 * in the low-order 8 bits, filled either MSB-first or LSB-first,
779 * depending on the settings passed to setup_pipe()
781 static void xmit_fixed(struct dbri *dbri, int pipe, unsigned int data)
785 if (pipe < 16 || pipe > 31) {
786 printk("DBRI: xmit_fixed: Illegal pipe number\n");
790 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
791 printk("DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
795 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
796 printk("DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
800 if (! (dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
801 printk("DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
805 /* DBRI short pipes always transmit LSB first */
807 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
808 data = reverse_bytes(data, dbri->pipes[pipe].length);
810 cmd = dbri_cmdlock(dbri);
812 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
815 dbri_cmdsend(dbri, cmd, 1);
818 static void recv_fixed(struct dbri *dbri, int pipe, volatile __u32 *ptr)
820 if (pipe < 16 || pipe > 31) {
821 printk("DBRI: recv_fixed called with illegal pipe number\n");
825 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
826 printk("DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
830 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
831 printk("DBRI: recv_fixed called on transmit pipe %d\n", pipe);
835 dbri->pipes[pipe].recv_fixed_ptr = ptr;
839 /* xmit_on_pipe() / recv_on_pipe()
841 * Transmit/receive data on a "long" pipe - i.e, one associated
844 * Only pipe numbers 0-15 can be used in this mode.
846 * Both functions take pointer/len arguments pointing to a data buffer,
847 * and both provide callback functions (may be NULL) to notify higher
848 * level code when transmission/reception is complete.
850 * Both work by building chains of descriptors which identify the
851 * data buffers. Buffers too large for a single descriptor will
852 * be spread across multiple descriptors.
854 static void xmit_on_pipe(struct dbri *dbri, int pipe,
855 void * buffer, unsigned int len,
856 void (*callback)(void *, int), void * callback_arg)
863 __u32 dvma_buffer, dvma_buffer_base;
865 if (pipe < 0 || pipe > 15) {
866 printk("DBRI: xmit_on_pipe: Illegal pipe number\n");
870 if (dbri->pipes[pipe].sdp == 0) {
871 printk("DBRI: xmit_on_pipe: Uninitialized pipe %d\n", pipe);
875 if (! (dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
876 printk("DBRI: xmit_on_pipe: Called on receive pipe %d\n",
881 dvma_buffer_base = dvma_buffer = sbus_map_single(dbri->sdev, buffer, len,
886 for (; td < DBRI_NO_DESCS; td ++) {
887 if (! dbri->descs[td].inuse)
890 if (td == DBRI_NO_DESCS) {
891 printk("DBRI: xmit_on_pipe: No descriptors\n");
895 if (len > ((1 << 13) - 1)) {
896 /* One should not leave a buffer shorter than */
897 /* a single sample. Otherwise bad things happens.*/
898 mylen = (1 << 13) - 4;
903 dbri->descs[td].inuse = 1;
904 dbri->descs[td].next = -1;
905 dbri->descs[td].buffer = NULL;
906 dbri->descs[td].output_callback = NULL;
907 dbri->descs[td].input_callback = NULL;
909 dbri->dma->desc[td].word1 = DBRI_TD_CNT(mylen);
910 dbri->dma->desc[td].ba = dvma_buffer;
911 dbri->dma->desc[td].nda = 0;
912 dbri->dma->desc[td].word4 = 0;
914 if (first_td == -1) {
917 dbri->descs[last_td].next = td;
918 dbri->dma->desc[last_td].nda =
919 dbri->dma_dvma + dbri_dma_off(desc, td);
923 dvma_buffer += mylen;
927 if (first_td == -1 || last_td == -1) {
928 sbus_unmap_single(dbri->sdev, dvma_buffer_base,
929 dvma_buffer - dvma_buffer_base + len,
934 dbri->dma->desc[last_td].word1 |= DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
936 dbri->descs[last_td].buffer = buffer;
937 dbri->descs[last_td].buffer_dvma = dvma_buffer_base;
938 dbri->descs[last_td].len = dvma_buffer - dvma_buffer_base + len;
939 dbri->descs[last_td].output_callback = callback;
940 dbri->descs[last_td].output_callback_arg = callback_arg;
942 for (td=first_td; td != -1; td = dbri->descs[td].next) {
943 dprintk(D_DESC, ("DBRI TD %d: %08x %08x %08x %08x\n",
945 dbri->dma->desc[td].word1,
946 dbri->dma->desc[td].ba,
947 dbri->dma->desc[td].nda,
948 dbri->dma->desc[td].word4));
953 if (pipe_active(dbri, pipe)) {
954 /* Pipe is already active - find last TD in use
955 * and link our first TD onto its end. Then issue
956 * a CDP command to let the DBRI know there's more data.
958 last_td = dbri->pipes[pipe].desc;
959 while (dbri->descs[last_td].next != -1)
960 last_td = dbri->descs[last_td].next;
962 dbri->descs[last_td].next = first_td;
963 dbri->dma->desc[last_td].nda =
964 dbri->dma_dvma + dbri_dma_off(desc, first_td);
966 cmd = dbri_cmdlock(dbri);
967 *(cmd++) = DBRI_CMD(D_CDP, 0, pipe);
968 dbri_cmdsend(dbri,cmd, 0);
970 /* Pipe isn't active - issue an SDP command to start
971 * our chain of TDs running.
973 dbri->pipes[pipe].desc = first_td;
974 cmd = dbri_cmdlock(dbri);
975 *(cmd++) = DBRI_CMD(D_SDP, 0,
976 dbri->pipes[pipe].sdp
977 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
978 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
979 dbri_cmdsend(dbri, cmd, 0);
982 restore_flags(flags);
985 static void recv_on_pipe(struct dbri *dbri, int pipe,
986 void * buffer, unsigned int len,
987 void (*callback)(void *, int, unsigned int),
994 __u32 bus_buffer, bus_buffer_base;
996 if (pipe < 0 || pipe > 15) {
997 printk("DBRI: recv_on_pipe: Illegal pipe number\n");
1001 if (dbri->pipes[pipe].sdp == 0) {
1002 printk("DBRI: recv_on_pipe: Uninitialized pipe %d\n", pipe);
1006 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1007 printk("DBRI: recv_on_pipe: Called on transmit pipe %d\n",
1013 * Should be able to queue multiple buffers to receive on a pipe
1015 if (dbri->pipes[pipe].desc != -1) {
1016 printk("DBRI: recv_on_pipe: Called on active pipe %d\n", pipe);
1020 /* Make sure buffer size is multiple of four */
1023 bus_buffer_base = bus_buffer = sbus_map_single(dbri->sdev, buffer, len,
1024 SBUS_DMA_FROMDEVICE);
1029 if (len > ((1 << 13) - 4)) {
1030 mylen = (1 << 13) - 4;
1035 for (rd = 0; rd < DBRI_NO_DESCS; rd ++) {
1036 if (! dbri->descs[rd].inuse)
1039 if (rd == DBRI_NO_DESCS) {
1040 printk("DBRI recv_on_pipe: No descriptors\n");
1044 dbri->dma->desc[rd].word1 = 0;
1045 dbri->dma->desc[rd].ba = bus_buffer;
1046 dbri->dma->desc[rd].nda = 0;
1047 dbri->dma->desc[rd].word4 = DBRI_RD_B | DBRI_RD_BCNT(mylen);
1049 dbri->descs[rd].buffer = NULL;
1050 dbri->descs[rd].len = 0;
1051 dbri->descs[rd].input_callback = NULL;
1052 dbri->descs[rd].output_callback = NULL;
1053 dbri->descs[rd].next = -1;
1054 dbri->descs[rd].inuse = 1;
1056 if (first_rd == -1) first_rd = rd;
1057 if (last_rd != -1) {
1058 dbri->dma->desc[last_rd].nda =
1059 dbri->dma_dvma + dbri_dma_off(desc, rd);
1060 dbri->descs[last_rd].next = rd;
1064 bus_buffer += mylen;
1068 if (last_rd == -1 || first_rd == -1) {
1069 sbus_unmap_single(dbri->sdev, bus_buffer_base,
1070 bus_buffer - bus_buffer_base + len,
1071 SBUS_DMA_FROMDEVICE);
1075 for (rd=first_rd; rd != -1; rd = dbri->descs[rd].next) {
1076 dprintk(D_DESC, ("DBRI RD %d: %08x %08x %08x %08x\n",
1078 dbri->dma->desc[rd].word1,
1079 dbri->dma->desc[rd].ba,
1080 dbri->dma->desc[rd].nda,
1081 dbri->dma->desc[rd].word4));
1084 dbri->descs[last_rd].buffer = buffer;
1085 dbri->descs[last_rd].buffer_dvma = bus_buffer_base;
1086 dbri->descs[last_rd].len = bus_buffer - bus_buffer_base + len;
1087 dbri->descs[last_rd].input_callback = callback;
1088 dbri->descs[last_rd].input_callback_arg = callback_arg;
1090 dbri->pipes[pipe].desc = first_rd;
1092 cmd = dbri_cmdlock(dbri);
1094 *(cmd++) = DBRI_CMD(D_SDP, 0, dbri->pipes[pipe].sdp | D_SDP_P | D_SDP_C);
1095 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_rd);
1097 dbri_cmdsend(dbri, cmd, 1);
1102 ****************************************************************************
1103 ************************** DBRI - CHI interface ****************************
1104 ****************************************************************************
1106 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1107 multiplexed serial interface which the DBRI can operate in either master
1108 (give clock/frame sync) or slave (take clock/frame sync) mode.
1112 enum master_or_slave { CHImaster, CHIslave };
1114 static void reset_chi(struct dbri *dbri, enum master_or_slave master_or_slave,
1119 static int chi_initialized = 0;
1121 if (!chi_initialized) {
1123 cmd = dbri_cmdlock(dbri);
1125 /* Set CHI Anchor: Pipe 16 */
1127 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16);
1128 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1129 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1132 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16);
1133 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1135 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1137 dbri->pipes[16].sdp = 1;
1138 dbri->pipes[16].nextpipe = 16;
1139 dbri->chi_in_pipe = 16;
1140 dbri->chi_out_pipe = 16;
1148 for (pipe = dbri->chi_in_pipe;
1150 pipe = dbri->pipes[pipe].nextpipe) {
1151 unlink_time_slot(dbri, pipe, PIPEinput,
1152 16, dbri->pipes[pipe].nextpipe);
1154 for (pipe = dbri->chi_out_pipe;
1156 pipe = dbri->pipes[pipe].nextpipe) {
1157 unlink_time_slot(dbri, pipe, PIPEoutput,
1158 16, dbri->pipes[pipe].nextpipe);
1161 dbri->chi_in_pipe = 16;
1162 dbri->chi_out_pipe = 16;
1164 cmd = dbri_cmdlock(dbri);
1167 if (master_or_slave == CHIslave) {
1168 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1170 * CHICM = 0 (slave mode, 8 kHz frame rate)
1171 * IR = give immediate CHI status interrupt
1172 * EN = give CHI status interrupt upon change
1174 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1176 /* Setup DBRI for CHI Master - generate clock, FS
1178 * BPF = bits per 8 kHz frame
1179 * 12.288 MHz / CHICM_divisor = clock rate
1180 * FD = 1 - drive CHIFS on rising edge of CHICK
1182 int clockrate = bits_per_frame * 8;
1183 int divisor = 12288 / clockrate;
1185 if (divisor > 255 || divisor * clockrate != 12288)
1186 printk("DBRI: illegal bits_per_frame in setup_chi\n");
1188 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1189 | D_CHI_BPF(bits_per_frame));
1192 dbri->chi_bpf = bits_per_frame;
1196 * RCE = 0 - receive on falling edge of CHICK
1197 * XCE = 1 - transmit on rising edge of CHICK
1198 * XEN = 1 - enable transmitter
1199 * REN = 1 - enable receiver
1202 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1203 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE|D_CDM_XEN|D_CDM_REN);
1205 dbri_cmdsend(dbri, cmd, 1);
1209 ****************************************************************************
1210 *********************** CS4215 audio codec management **********************
1211 ****************************************************************************
1213 In the standard SPARC audio configuration, the CS4215 codec is attached
1214 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1217 static void mmcodec_default(struct cs4215 *mm)
1220 * No action, memory resetting only.
1222 * Data Time Slot 5-8
1223 * Speaker,Line and Headphone enable. Gain set to the half.
1226 mm->data[0] = CS4215_LO(0x20) | CS4215_HE|CS4215_LE;
1227 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1228 mm->data[2] = CS4215_LG( 0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1229 mm->data[3] = CS4215_RG( 0x8) | CS4215_MA(0xf);
1232 * Control Time Slot 1-4
1233 * 0: Default I/O voltage scale
1234 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1235 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1238 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1239 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1240 mm->ctrl[2] = CS4215_XCLK |
1241 CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1245 static void mmcodec_setup_pipes(struct dbri *dbri)
1249 * Pipe 4: Send timeslots 1-4 (audio data)
1250 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1251 * Pipe 6: Receive timeslots 1-4 (audio data)
1252 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1253 * interrupt, and the rest of the data (slot 5 and 8) is
1254 * not relevant for us (only for doublechecking).
1257 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1258 * Pipe 18: Receive timeslot 1 (clb).
1259 * Pipe 19: Receive timeslot 7 (version).
1262 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1263 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1264 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1265 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1267 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1268 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1269 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1271 dbri->mm.status = 0;
1273 recv_fixed(dbri, 18, & dbri->mm.status);
1274 recv_fixed(dbri, 19, & dbri->mm.version);
1277 static void mmcodec_setgain(struct dbri *dbri, int muted)
1279 if (muted || dbri->perchip_info.output_muted) {
1280 dbri->mm.data[0] = 63;
1281 dbri->mm.data[1] = 63;
1283 int left_gain = (dbri->perchip_info.play.gain / 4) % 64;
1284 int right_gain = (dbri->perchip_info.play.gain / 4) % 64;
1285 int outport = dbri->perchip_info.play.port;
1287 if (dbri->perchip_info.play.balance < AUDIO_MID_BALANCE) {
1288 right_gain *= dbri->perchip_info.play.balance;
1289 right_gain /= AUDIO_MID_BALANCE;
1291 left_gain *= AUDIO_RIGHT_BALANCE
1292 - dbri->perchip_info.play.balance;
1293 left_gain /= AUDIO_MID_BALANCE;
1296 dprintk(D_MM, ("DBRI: Setting codec gain left: %d right: %d\n",
1297 left_gain, right_gain));
1299 dbri->mm.data[0] = (63 - left_gain);
1300 if (outport & AUDIO_HEADPHONE) dbri->mm.data[0] |= CS4215_HE;
1301 if (outport & AUDIO_LINE_OUT) dbri->mm.data[0] |= CS4215_LE;
1302 dbri->mm.data[1] = (63 - right_gain);
1303 if (outport & AUDIO_SPEAKER) dbri->mm.data[1] |= CS4215_SE;
1306 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1309 static void mmcodec_init_data(struct dbri *dbri)
1316 * Pipe 4: Send timeslots 1-4 (audio data)
1317 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1318 * Pipe 6: Receive timeslots 1-4 (audio data)
1319 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1320 * interrupt, and the rest of the data (slot 5 and 8) is
1321 * not relevant for us (only for doublechecking).
1323 * Just like in control mode, the time slots are all offset by eight
1324 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1325 * even if it's the CHI master. Don't ask me...
1327 tmp = sbus_readl(dbri->regs + REG0);
1328 tmp &= ~(D_C); /* Disable CHI */
1329 sbus_writel(tmp, dbri->regs + REG0);
1331 /* Switch CS4215 to data mode - set PIO3 to 1 */
1332 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1333 (dbri->mm.onboard ? D_PIO0 : D_PIO2),
1336 reset_chi(dbri, CHIslave, 128);
1338 /* Note: this next doesn't work for 8-bit stereo, because the two
1339 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1340 * (See CS4215 datasheet Fig 15)
1342 * DBRI non-contiguous mode would be required to make this work.
1345 data_width = dbri->perchip_info.play.channels
1346 * dbri->perchip_info.play.precision;
1348 link_time_slot(dbri, 20, PIPEoutput, 16,
1349 32, dbri->mm.offset + 32);
1350 link_time_slot(dbri, 4, PIPEoutput, 16,
1351 data_width, dbri->mm.offset);
1352 link_time_slot(dbri, 6, PIPEinput, 16,
1353 data_width, dbri->mm.offset);
1354 link_time_slot(dbri, 21, PIPEinput, 16,
1355 16, dbri->mm.offset + 40);
1357 mmcodec_setgain(dbri, 0);
1359 tmp = sbus_readl(dbri->regs + REG0);
1360 tmp |= D_C; /* Enable CHI */
1361 sbus_writel(tmp, dbri->regs + REG0);
1365 * Send the control information (i.e. audio format)
1367 static int mmcodec_setctrl(struct dbri *dbri)
1372 /* XXX - let the CPU do something useful during these delays */
1374 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1375 * to make sure this takes. This avoids clicking noises.
1378 mmcodec_setgain(dbri, 1);
1382 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1383 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1385 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1386 sbus_writel(val, dbri->regs + REG2);
1389 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1390 * operate as CHI master, supplying clocking and frame synchronization.
1392 * In Data mode, however, the CS4215 must be CHI master to insure
1393 * that its data stream is synchronous with its codec.
1395 * The upshot of all this? We start by putting the DBRI into master
1396 * mode, program the CS4215 in Control mode, then switch the CS4215
1397 * into Data mode and put the DBRI into slave mode. Various timing
1398 * requirements must be observed along the way.
1400 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1401 * others?), the addressing of the CS4215's time slots is
1402 * offset by eight bits, so we add eight to all the "cycle"
1403 * values in the Define Time Slot (DTS) commands. This is
1404 * done in hardware by a TI 248 that delays the DBRI->4215
1405 * frame sync signal by eight clock cycles. Anybody know why?
1407 tmp = sbus_readl(dbri->regs + REG0);
1408 tmp &= ~D_C; /* Disable CHI */
1409 sbus_writel(tmp, dbri->regs + REG0);
1411 reset_chi(dbri, CHImaster, 128);
1415 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1416 * Pipe 18: Receive timeslot 1 (clb).
1417 * Pipe 19: Receive timeslot 7 (version).
1420 link_time_slot(dbri, 17, PIPEoutput, 16,
1421 32, dbri->mm.offset);
1422 link_time_slot(dbri, 18, PIPEinput, 16,
1423 8, dbri->mm.offset);
1424 link_time_slot(dbri, 19, PIPEinput, 16,
1425 8, dbri->mm.offset + 48);
1427 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1429 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1430 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1432 tmp = sbus_readl(dbri->regs + REG0);
1433 tmp |= D_C; /* Enable CHI */
1434 sbus_writel(tmp, dbri->regs + REG0);
1437 while (((dbri->mm.status & 0xe4) != 0x20) && --i)
1440 dprintk(D_MM, ("DBRI: CS4215 didn't respond to CLB (0x%02x)\n",
1445 /* Terminate CS4215 control mode - data sheet says
1446 * "Set CLB=1 and send two more frames of valid control info"
1448 dbri->mm.ctrl[0] |= CS4215_CLB;
1449 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1451 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1454 mmcodec_setgain(dbri, 0);
1459 static int mmcodec_init(struct sparcaudio_driver *drv)
1461 struct dbri *dbri = (struct dbri *) drv->private;
1462 u32 reg2 = sbus_readl(dbri->regs + REG2);
1464 /* Look for the cs4215 chips */
1466 dprintk(D_MM, ("DBRI: Onboard CS4215 detected\n"));
1467 dbri->mm.onboard = 1;
1470 dprintk(D_MM, ("DBRI: Speakerbox detected\n"));
1471 dbri->mm.onboard = 0;
1475 /* Using the Speakerbox, if both are attached. */
1476 if((reg2 & D_PIO2) && (reg2 & D_PIO0)) {
1477 printk("DBRI: Using speakerbox / ignoring onboard mmcodec.\n");
1478 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1479 dbri->mm.onboard = 0;
1482 if(!(reg2 & (D_PIO0|D_PIO2))) {
1483 printk("DBRI: no mmcodec found.\n");
1488 mmcodec_setup_pipes(dbri);
1490 mmcodec_default(&dbri->mm);
1492 dbri->mm.version = 0xff;
1493 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1494 if (mmcodec_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1495 dprintk(D_MM, ("DBRI: CS4215 failed probe at offset %d\n",
1500 dprintk(D_MM, ("DBRI: Found CS4215 at offset %d\n", dbri->mm.offset));
1502 dbri->perchip_info.play.channels = 1;
1503 dbri->perchip_info.play.precision = 8;
1504 dbri->perchip_info.play.gain = (AUDIO_MAX_GAIN * 7 / 10); /* 70% */
1505 dbri->perchip_info.play.balance = AUDIO_MID_BALANCE;
1506 dbri->perchip_info.play.port = dbri->perchip_info.play.avail_ports =
1507 AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
1508 dbri->perchip_info.record.port = AUDIO_MICROPHONE;
1509 dbri->perchip_info.record.avail_ports =
1510 AUDIO_MICROPHONE | AUDIO_LINE_IN;
1512 mmcodec_init_data(dbri);
1519 ****************************************************************************
1520 ******************** Interface with sparcaudio midlevel ********************
1521 ****************************************************************************
1523 The sparcaudio midlevel is contained in the file audio.c. It interfaces
1524 to the user process and performs buffering, intercepts SunOS-style ioctl's,
1525 etc. It interfaces to a abstract audio device via a struct sparcaudio_driver.
1526 This code presents such an interface for the DBRI with an attached CS4215.
1527 All our routines are defined, and then comes our struct sparcaudio_driver.
1531 /******************* sparcaudio midlevel - audio output *******************/
1532 static void dbri_audio_output_callback(void * callback_arg, int status)
1534 struct sparcaudio_driver *drv = callback_arg;
1537 sparcaudio_output_done(drv, 1);
1540 static void dbri_start_output(struct sparcaudio_driver *drv,
1541 __u8 * buffer, unsigned long count)
1543 struct dbri *dbri = (struct dbri *) drv->private;
1545 dprintk(D_USR, ("DBRI: start audio output buf=%p/%ld\n",
1548 /* Pipe 4 is audio transmit */
1549 xmit_on_pipe(dbri, 4, buffer, count,
1550 &dbri_audio_output_callback, drv);
1552 /* Notify midlevel that we're a DMA-capable driver that
1553 * can accept another buffer immediately. We should probably
1554 * check that we've got enough resources (i.e, descriptors)
1555 * available before doing this, but the default midlevel
1556 * settings only buffer 64KB, which we can handle with 16
1557 * of our DBRI_NO_DESCS (64) descriptors.
1559 * This code is #ifdef'ed out because it's caused me more
1560 * problems than it solved. It'd be nice to provide the
1561 * DBRI with a chain of buffers, but the midlevel code is
1562 * so tricky that I really don't want to deal with it.
1565 * This must be enabled otherwise the output is noisy
1566 * as return to user space is done when all buffers
1567 * are already played, so user space player has no time
1568 * to prepare next ones without a period of silence. - Krzysztof Helt
1571 sparcaudio_output_done(drv, 2);
1574 static void dbri_stop_output(struct sparcaudio_driver *drv)
1576 struct dbri *dbri = (struct dbri *) drv->private;
1578 reset_pipe(dbri, 4);
1581 /******************* sparcaudio midlevel - audio input ********************/
1583 static void dbri_audio_input_callback(void * callback_arg, int status,
1586 struct sparcaudio_driver * drv =
1587 (struct sparcaudio_driver *) callback_arg;
1590 sparcaudio_input_done(drv, 3);
1593 static void dbri_start_input(struct sparcaudio_driver *drv,
1594 __u8 * buffer, unsigned long len)
1596 struct dbri *dbri = (struct dbri *) drv->private;
1598 /* Pipe 6 is audio receive */
1599 recv_on_pipe(dbri, 6, buffer, len,
1600 &dbri_audio_input_callback, (void *)drv);
1601 dprintk(D_USR, ("DBRI: start audio input buf=%p/%ld\n",
1605 static void dbri_stop_input(struct sparcaudio_driver *drv)
1607 struct dbri *dbri = (struct dbri *) drv->private;
1609 reset_pipe(dbri, 6);
1612 /******************* sparcaudio midlevel - volume & balance ***************/
1614 static int dbri_set_output_volume(struct sparcaudio_driver *drv, int volume)
1616 struct dbri *dbri = (struct dbri *) drv->private;
1618 dbri->perchip_info.play.gain = volume;
1619 mmcodec_setgain(dbri, 0);
1624 static int dbri_get_output_volume(struct sparcaudio_driver *drv)
1626 struct dbri *dbri = (struct dbri *) drv->private;
1628 return dbri->perchip_info.play.gain;
1631 static int dbri_set_input_volume(struct sparcaudio_driver *drv, int volume)
1636 static int dbri_get_input_volume(struct sparcaudio_driver *drv)
1641 static int dbri_set_monitor_volume(struct sparcaudio_driver *drv, int volume)
1646 static int dbri_get_monitor_volume(struct sparcaudio_driver *drv)
1651 static int dbri_set_output_balance(struct sparcaudio_driver *drv, int balance)
1653 struct dbri *dbri = (struct dbri *) drv->private;
1655 dbri->perchip_info.play.balance = balance;
1656 mmcodec_setgain(dbri, 0);
1661 static int dbri_get_output_balance(struct sparcaudio_driver *drv)
1663 struct dbri *dbri = (struct dbri *) drv->private;
1665 return dbri->perchip_info.play.balance;
1668 static int dbri_set_input_balance(struct sparcaudio_driver *drv, int balance)
1673 static int dbri_get_input_balance(struct sparcaudio_driver *drv)
1678 static int dbri_set_output_muted(struct sparcaudio_driver *drv, int mute)
1680 struct dbri *dbri = (struct dbri *) drv->private;
1682 dbri->perchip_info.output_muted = mute;
1687 static int dbri_get_output_muted(struct sparcaudio_driver *drv)
1689 struct dbri *dbri = (struct dbri *) drv->private;
1691 return dbri->perchip_info.output_muted;
1694 /******************* sparcaudio midlevel - encoding format ****************/
1696 static int dbri_set_output_channels(struct sparcaudio_driver *drv, int chan)
1698 struct dbri *dbri = (struct dbri *) drv->private;
1704 dbri->mm.ctrl[1] &= ~CS4215_DFR_STEREO;
1707 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1713 dbri->perchip_info.play.channels = chan;
1714 mmcodec_setctrl(dbri);
1715 mmcodec_init_data(dbri);
1719 static int dbri_get_output_channels(struct sparcaudio_driver *drv)
1721 struct dbri *dbri = (struct dbri *) drv->private;
1723 return dbri->perchip_info.play.channels;
1726 static int dbri_set_input_channels(struct sparcaudio_driver *drv, int chan)
1728 return dbri_set_output_channels(drv, chan);
1731 static int dbri_get_input_channels(struct sparcaudio_driver *drv)
1733 return dbri_get_output_channels(drv);
1736 static int dbri_set_output_precision(struct sparcaudio_driver *drv, int prec)
1741 static int dbri_get_output_precision(struct sparcaudio_driver *drv)
1743 struct dbri *dbri = (struct dbri *) drv->private;
1745 return dbri->perchip_info.play.precision;
1748 static int dbri_set_input_precision(struct sparcaudio_driver *drv, int prec)
1753 static int dbri_get_input_precision(struct sparcaudio_driver *drv)
1755 struct dbri *dbri = (struct dbri *) drv->private;
1757 return dbri->perchip_info.play.precision;
1760 static int dbri_set_output_encoding(struct sparcaudio_driver *drv, int enc)
1762 struct dbri *dbri = (struct dbri *) drv->private;
1764 /* For ULAW and ALAW, audio.c enforces precision = 8,
1765 * for LINEAR, precision must be 16
1769 case AUDIO_ENCODING_NONE:
1771 case AUDIO_ENCODING_ULAW:
1772 dbri->mm.ctrl[1] &= ~3;
1773 dbri->mm.ctrl[1] |= CS4215_DFR_ULAW;
1774 dbri->perchip_info.play.encoding = enc;
1775 dbri->perchip_info.play.precision = 8;
1777 case AUDIO_ENCODING_ALAW:
1778 dbri->mm.ctrl[1] &= ~3;
1779 dbri->mm.ctrl[1] |= CS4215_DFR_ALAW;
1780 dbri->perchip_info.play.encoding = enc;
1781 dbri->perchip_info.play.precision = 8;
1783 case AUDIO_ENCODING_LINEAR:
1784 dbri->mm.ctrl[1] &= ~3;
1785 dbri->mm.ctrl[1] |= CS4215_DFR_LINEAR16;
1786 dbri->perchip_info.play.encoding = enc;
1787 dbri->perchip_info.play.precision = 16;
1793 mmcodec_setctrl(dbri);
1794 mmcodec_init_data(dbri);
1798 static int dbri_get_output_encoding(struct sparcaudio_driver *drv)
1800 struct dbri *dbri = (struct dbri *) drv->private;
1802 return dbri->perchip_info.play.encoding;
1805 static int dbri_set_input_encoding(struct sparcaudio_driver *drv, int enc)
1807 return dbri_set_output_encoding(drv, enc);
1810 static int dbri_get_input_encoding(struct sparcaudio_driver *drv)
1812 return dbri_get_output_encoding(drv);
1815 static int dbri_set_output_rate(struct sparcaudio_driver *drv, int rate)
1817 struct dbri *dbri = (struct dbri *) drv->private;
1823 for (i=0; CS4215_FREQ[i].freq; i++) {
1824 if (CS4215_FREQ[i].freq == rate)
1828 if (CS4215_FREQ[i].freq == 0)
1831 dbri->mm.ctrl[1] &= ~ 0x38;
1832 dbri->mm.ctrl[1] |= CS4215_FREQ[i].csval;
1833 dbri->mm.ctrl[2] &= ~ 0x70;
1834 dbri->mm.ctrl[2] |= CS4215_FREQ[i].xtal;
1836 dbri->perchip_info.play.sample_rate = rate;
1838 mmcodec_setctrl(dbri);
1839 mmcodec_init_data(dbri);
1843 static int dbri_get_output_rate(struct sparcaudio_driver *drv)
1845 struct dbri *dbri = (struct dbri *) drv->private;
1847 return dbri->perchip_info.play.sample_rate;
1850 static int dbri_set_input_rate(struct sparcaudio_driver *drv, int rate)
1852 return dbri_set_output_rate(drv, rate);
1855 static int dbri_get_input_rate(struct sparcaudio_driver *drv)
1857 return dbri_get_output_rate(drv);
1860 static int dbri_get_formats(struct sparcaudio_driver *drv)
1862 /* 8-bit format is not working */
1863 return (AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE);
1866 /******************* sparcaudio midlevel - ports ***********************/
1868 static int dbri_set_output_port(struct sparcaudio_driver *drv, int port)
1870 struct dbri *dbri = (struct dbri *) drv->private;
1872 port &= dbri->perchip_info.play.avail_ports;
1873 dbri->perchip_info.play.port = port;
1874 mmcodec_setgain(dbri, 0);
1879 static int dbri_get_output_port(struct sparcaudio_driver *drv)
1881 struct dbri *dbri = (struct dbri *) drv->private;
1883 return dbri->perchip_info.play.port;
1886 static int dbri_set_input_port(struct sparcaudio_driver *drv, int port)
1888 struct dbri *dbri = (struct dbri *) drv->private;
1890 port &= dbri->perchip_info.record.avail_ports;
1891 dbri->perchip_info.record.port = port;
1892 mmcodec_setgain(dbri, 0);
1897 static int dbri_get_input_port(struct sparcaudio_driver *drv)
1899 struct dbri *dbri = (struct dbri *) drv->private;
1901 return dbri->perchip_info.record.port;
1904 static int dbri_get_output_ports(struct sparcaudio_driver *drv)
1906 struct dbri *dbri = (struct dbri *) drv->private;
1908 return dbri->perchip_info.play.avail_ports;
1911 static int dbri_get_input_ports(struct sparcaudio_driver *drv)
1913 struct dbri *dbri = (struct dbri *) drv->private;
1915 return dbri->perchip_info.record.avail_ports;
1918 /******************* sparcaudio midlevel - driver ID ********************/
1920 static void dbri_audio_getdev(struct sparcaudio_driver *drv,
1921 audio_device_t *audinfo)
1923 struct dbri *dbri = (struct dbri *) drv->private;
1925 strncpy(audinfo->name, "SUNW,DBRI", sizeof(audinfo->name) - 1);
1927 audinfo->version[0] = dbri->dbri_version;
1928 audinfo->version[1] = '\0';
1930 strncpy(audinfo->config, "onboard1", sizeof(audinfo->config) - 1);
1933 static int dbri_sunaudio_getdev_sunos(struct sparcaudio_driver *drv)
1935 return AUDIO_DEV_CODEC;
1938 /******************* sparcaudio midlevel - open & close ******************/
1940 static int dbri_open(struct inode * inode, struct file * file,
1941 struct sparcaudio_driver *drv)
1948 static void dbri_release(struct inode * inode, struct file * file,
1949 struct sparcaudio_driver *drv)
1954 static int dbri_ioctl(struct inode * inode, struct file * file,
1955 unsigned int x, unsigned long y,
1956 struct sparcaudio_driver *drv)
1961 /*********** sparcaudio midlevel - struct sparcaudio_driver ************/
1963 static struct sparcaudio_operations dbri_ops = {
1972 dbri_set_output_volume,
1973 dbri_get_output_volume,
1974 dbri_set_input_volume,
1975 dbri_get_input_volume,
1976 dbri_set_monitor_volume,
1977 dbri_get_monitor_volume,
1978 dbri_set_output_balance,
1979 dbri_get_output_balance,
1980 dbri_set_input_balance,
1981 dbri_get_input_balance,
1982 dbri_set_output_channels,
1983 dbri_get_output_channels,
1984 dbri_set_input_channels,
1985 dbri_get_input_channels,
1986 dbri_set_output_precision,
1987 dbri_get_output_precision,
1988 dbri_set_input_precision,
1989 dbri_get_input_precision,
1990 dbri_set_output_port,
1991 dbri_get_output_port,
1992 dbri_set_input_port,
1993 dbri_get_input_port,
1994 dbri_set_output_encoding,
1995 dbri_get_output_encoding,
1996 dbri_set_input_encoding,
1997 dbri_get_input_encoding,
1998 dbri_set_output_rate,
1999 dbri_get_output_rate,
2000 dbri_set_input_rate,
2001 dbri_get_input_rate,
2002 dbri_sunaudio_getdev_sunos,
2003 dbri_get_output_ports,
2004 dbri_get_input_ports,
2005 dbri_set_output_muted,
2006 dbri_get_output_muted,
2007 NULL, /* dbri_set_output_pause, */
2008 NULL, /* dbri_get_output_pause, */
2009 NULL, /* dbri_set_input_pause, */
2010 NULL, /* dbri_get_input_pause, */
2011 NULL, /* dbri_set_output_samples, */
2012 NULL, /* dbri_get_output_samples, */
2013 NULL, /* dbri_set_input_samples, */
2014 NULL, /* dbri_get_input_samples, */
2015 NULL, /* dbri_set_output_error, */
2016 NULL, /* dbri_get_output_error, */
2017 NULL, /* dbri_set_input_error, */
2018 NULL, /* dbri_get_input_error, */
2024 ****************************************************************************
2025 ************************** ISDN (Hisax) Interface **************************
2026 ****************************************************************************
2028 void dbri_isdn_init(struct dbri *dbri)
2030 /* Pipe 0: Receive D channel
2031 * Pipe 8: Receive B1 channel
2032 * Pipe 9: Receive B2 channel
2033 * Pipe 1: Transmit D channel
2034 * Pipe 10: Transmit B1 channel
2035 * Pipe 11: Transmit B2 channel
2038 setup_pipe(dbri, 0, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
2039 setup_pipe(dbri, 8, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
2040 setup_pipe(dbri, 9, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
2042 setup_pipe(dbri, 1, D_SDP_HDLC_D | D_SDP_TO_SER | D_SDP_LSB);
2043 setup_pipe(dbri,10, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
2044 setup_pipe(dbri,11, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
2046 link_time_slot(dbri, 0, PIPEinput, 0, 2, 17);
2047 link_time_slot(dbri, 8, PIPEinput, 0, 8, 0);
2048 link_time_slot(dbri, 9, PIPEinput, 8, 8, 8);
2050 link_time_slot(dbri, 1, PIPEoutput, 1, 2, 17);
2051 link_time_slot(dbri, 10, PIPEoutput, 1, 8, 0);
2052 link_time_slot(dbri, 11, PIPEoutput, 10, 8, 8);
2055 int dbri_get_irqnum(int dev)
2059 if (dev >= num_drivers)
2062 dbri = (struct dbri *) drivers[dev].private;
2064 tprintk(("dbri_get_irqnum()\n"));
2066 /* On the sparc, the cpu's irq number is only part of the "irq" */
2067 return (dbri->irq & NR_IRQS);
2070 int dbri_get_liu_state(int dev)
2074 if (dev >= num_drivers)
2077 dbri = (struct dbri *) drivers[dev].private;
2079 tprintk(("dbri_get_liu_state() returns %d\n", dbri->liu_state));
2081 return dbri->liu_state;
2084 void dbri_liu_activate(int dev, int priority);
2086 void dbri_liu_init(int dev, void (*callback)(void *), void *callback_arg)
2090 if (dev >= num_drivers)
2093 dbri = (struct dbri *) drivers[dev].private;
2095 tprintk(("dbri_liu_init()\n"));
2097 /* Set callback for LIU state change */
2098 dbri->liu_callback = callback;
2099 dbri->liu_callback_arg = callback_arg;
2101 dbri_isdn_init(dbri);
2102 dbri_liu_activate(dev, 0);
2105 void dbri_liu_activate(int dev, int priority)
2111 if (dev >= num_drivers)
2114 dbri = (struct dbri *) drivers[dev].private;
2116 tprintk(("dbri_liu_activate()\n"));
2118 if (dbri->liu_state <= 3) {
2121 cmd = dbri_cmdlock(dbri);
2123 /* Turn on the ISDN TE interface and request activation */
2124 val = D_NT_IRM_IMM | D_NT_IRM_EN | D_NT_ACT;
2128 *(cmd++) = DBRI_CMD(D_TE, 0, val);
2130 dbri_cmdsend(dbri, cmd, 1);
2132 /* Activate the interface */
2133 tmp = sbus_readl(dbri->regs + REG0);
2135 sbus_writel(tmp, dbri->regs + REG0);
2139 void dbri_liu_deactivate(int dev)
2146 if (dev >= num_drivers)
2149 dbri = (struct dbri *) drivers[dev].private;
2151 tprintk(("dbri_liu_deactivate()\n"));
2154 /* Turn off the ISDN TE interface */
2155 tmp = sbus_readl(dbri->regs + REG0);
2157 sbus_writel(tmp, dbri->regs + REG0);
2159 dbri->liu_state = 0;
2163 void dbri_dxmit(int dev, __u8 *buffer, unsigned int count,
2164 void (*callback)(void *, int), void *callback_arg)
2168 if (dev >= num_drivers)
2171 dbri = (struct dbri *) drivers[dev].private;
2173 /* Pipe 1 is D channel transmit */
2174 xmit_on_pipe(dbri, 1, buffer, count, callback, callback_arg);
2177 void dbri_drecv(int dev, __u8 *buffer, unsigned int size,
2178 void (*callback)(void *, int, unsigned int),
2183 if (dev >= num_drivers)
2186 dbri = (struct dbri *) drivers[dev].private;
2188 /* Pipe 0 is D channel receive */
2189 recv_on_pipe(dbri, 0, buffer, size, callback, callback_arg);
2192 int dbri_bopen(int dev, unsigned int chan,
2193 int hdlcmode, u_char xmit_idle_char)
2197 if (dev >= num_drivers || chan > 1)
2200 dbri = (struct dbri *) drivers[dev].private;
2205 /* Pipe 8/9: receive B1/B2 channel */
2206 setup_pipe(dbri, 8+chan, D_SDP_HDLC | D_SDP_FROM_SER|D_SDP_LSB);
2208 /* Pipe 10/11: transmit B1/B2 channel */
2209 setup_pipe(dbri,10+chan, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
2210 } else { /* !hdlcmode means transparent */
2211 /* Pipe 8/9: receive B1/B2 channel */
2212 setup_pipe(dbri, 8+chan, D_SDP_MEM | D_SDP_FROM_SER|D_SDP_LSB);
2214 /* Pipe 10/11: transmit B1/B2 channel */
2215 setup_pipe(dbri,10+chan, D_SDP_MEM | D_SDP_TO_SER | D_SDP_LSB);
2220 void dbri_bclose(int dev, unsigned int chan)
2224 if (dev >= num_drivers || chan > 1)
2227 dbri = (struct dbri *) drivers[dev].private;
2229 reset_pipe(dbri, 8+chan);
2230 reset_pipe(dbri, 10+chan);
2233 void dbri_bxmit(int dev, unsigned int chan,
2234 __u8 *buffer, unsigned long count,
2235 void (*callback)(void *, int),
2240 if (dev >= num_drivers || chan > 1)
2243 dbri = (struct dbri *) drivers[dev].private;
2245 /* Pipe 10/11 is B1/B2 channel transmit */
2246 xmit_on_pipe(dbri, 10+chan, buffer, count, callback, callback_arg);
2249 void dbri_brecv(int dev, unsigned int chan,
2250 __u8 *buffer, unsigned long size,
2251 void (*callback)(void *, int, unsigned int),
2256 if (dev >= num_drivers || chan > 1)
2259 dbri = (struct dbri *) drivers[dev].private;
2261 /* Pipe 8/9 is B1/B2 channel receive */
2262 recv_on_pipe(dbri, 8+chan, buffer, size, callback, callback_arg);
2265 #if defined(DBRI_ISDN)
2266 struct foreign_interface dbri_foreign_interface = {
2271 dbri_liu_deactivate,
2279 EXPORT_SYMBOL(dbri_foreign_interface);
2283 ****************************************************************************
2284 **************************** Initialization ********************************
2285 ****************************************************************************
2288 static int dbri_attach(struct sparcaudio_driver *drv,
2289 struct sbus_dev *sdev)
2292 struct linux_prom_irqs irq;
2295 if (sdev->prom_name[9] < 'e') {
2296 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2297 sdev->prom_name[9]);
2301 drv->ops = &dbri_ops;
2302 drv->private = kmalloc(sizeof(struct dbri), GFP_KERNEL);
2303 if (drv->private == NULL)
2306 dbri = (struct dbri *) drv->private;
2307 memset(dbri, 0, sizeof(*dbri));
2309 dbri->dma = sbus_alloc_consistent(sdev,
2310 sizeof(struct dbri_dma),
2313 memset((void *) dbri->dma, 0, sizeof(struct dbri_dma));
2315 dprintk(D_GEN, ("DBRI: DMA Cmd Block 0x%p (0x%08x)\n",
2316 dbri->dma, dbri->dma_dvma));
2318 dbri->dbri_version = sdev->prom_name[9];
2321 /* Map the registers into memory. */
2322 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2323 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2324 sdev->reg_addrs[0].reg_size,
2327 printk(KERN_ERR "DBRI: could not allocate registers\n");
2328 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2329 (void *)dbri->dma, dbri->dma_dvma);
2330 kfree(drv->private);
2334 prom_getproperty(sdev->prom_node, "intr", (char *)&irq, sizeof(irq));
2335 dbri->irq = irq.pri;
2337 err = request_irq(dbri->irq, dbri_intr, SA_SHIRQ,
2338 "DBRI audio/ISDN", dbri);
2340 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2341 sbus_iounmap(dbri->regs, dbri->regs_size);
2342 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2343 (void *)dbri->dma, dbri->dma_dvma);
2344 kfree(drv->private);
2348 dbri_initialize(dbri);
2349 err = mmcodec_init(drv);
2355 /* Register ourselves with the midlevel audio driver. */
2356 err = register_sparcaudio_driver(drv,1);
2358 printk(KERN_ERR "DBRI: unable to register audio\n");
2363 dbri->perchip_info.play.active = dbri->perchip_info.play.pause = 0;
2364 dbri->perchip_info.record.active = dbri->perchip_info.record.pause = 0;
2366 printk(KERN_INFO "audio%d at 0x%lx (irq %d) is DBRI(%c)+CS4215(%d)\n",
2367 num_drivers, dbri->regs,
2368 dbri->irq, dbri->dbri_version, dbri->mm.version);
2373 /* Probe for the dbri chip and then attach the driver. */
2374 static int __init dbri_init(void)
2376 struct sbus_bus *sbus;
2377 struct sbus_dev *sdev;
2381 /* Probe each SBUS for the DBRI chip(s). */
2382 for_all_sbusdev(sdev, sbus) {
2384 * The version is coded in the last character
2386 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2387 dprintk(D_GEN, ("DBRI: Found %s in SBUS slot %d\n",
2388 sdev->prom_name, sdev->slot));
2389 if (num_drivers >= MAX_DRIVERS) {
2390 printk("DBRI: Ignoring slot %d\n", sdev->slot);
2394 if (dbri_attach(&drivers[num_drivers], sdev) == 0)
2399 return (num_drivers > 0) ? 0 : -EIO;
2402 static void __exit dbri_exit(void)
2406 for (i = 0; i < num_drivers; i++) {
2407 dbri_detach((struct dbri *) drivers[i].private);
2408 unregister_sparcaudio_driver(& drivers[i], 1);
2413 module_init(dbri_init);
2414 module_exit(dbri_exit);
2415 MODULE_LICENSE("GPL");
2418 * Overrides for Emacs so that we follow Linus's tabbing style.
2419 * Emacs will notice this stuff at the end of the file and automatically
2420 * adjust the settings for this buffer only. This must remain at the end
2422 * ---------------------------------------------------------------------------
2425 * c-brace-imaginary-offset: 0
2426 * c-brace-offset: -8
2427 * c-argdecl-indent: 8
2428 * c-label-offset: -8
2429 * c-continued-statement-offset: 8
2430 * c-continued-brace-offset: 0
2431 * indent-tabs-mode: nil