2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
4 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
6 * $Id: tgafb.c,v 1.12.2.3 2000/04/04 06:44:56 mato Exp $
8 * This driver is partly based on the original TGA framebuffer device, which
9 * was partly based on the original TGA console driver, which are
11 * Copyright (C) 1997 Geert Uytterhoeven
12 * Copyright (C) 1995 Jay Estabrook
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file COPYING in the main directory of this archive for
19 /* KNOWN PROBLEMS/TO DO ===================================================== *
21 * - How to set a single color register on 24-plane cards?
23 * - Hardware cursor/other text acceleration methods
25 * - Some redraws can stall kernel for several seconds
26 * [This should now be solved by the fast memmove() patch in 2.3.6]
28 * KNOWN PROBLEMS/TO DO ==================================================== */
30 #include <linux/module.h>
31 #include <linux/sched.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
36 #include <linux/tty.h>
37 #include <linux/slab.h>
38 #include <linux/vmalloc.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
44 #include <linux/selection.h>
45 #include <linux/console.h>
48 #include <video/fbcon.h>
49 #include <video/fbcon-cfb8.h>
50 #include <video/fbcon-cfb32.h>
58 static struct tgafb_info fb_info;
59 static struct tgafb_par current_par;
60 static int current_par_valid = 0;
61 static struct display disp;
63 static char default_fontname[40] __initdata = { 0 };
64 static struct fb_var_screeninfo default_var;
65 static int default_var_valid = 0;
67 static int currcon = 0;
69 static struct { u_char red, green, blue, pad; } palette[256];
70 #ifdef FBCON_HAS_CFB32
71 static u32 fbcon_cfb32_cmap[16];
79 static unsigned int fb_offset_presets[4] = {
81 TGA_24PLANE_FB_OFFSET,
86 static unsigned int deep_presets[4] = {
93 static unsigned int rasterop_presets[4] = {
100 static unsigned int mode_presets[4] = {
107 static unsigned int base_addr_presets[4] = {
116 * Predefined video modes
117 * This is a subset of the standard VESA modes, recalculated from XFree86.
119 * XXX Should we store these in terms of the encoded par structs? Even better,
120 * fbcon should provide a general mechanism for doing something like this.
125 struct fb_var_screeninfo var;
126 } tgafb_predefined[] __initdata = {
128 640, 480, 640, 480, 0, 0, 0, 0,
129 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
130 0, 0, -1, -1, FB_ACCELF_TEXT, 39722, 40, 24, 32, 11, 96, 2,
132 FB_VMODE_NONINTERLACED
135 800, 600, 800, 600, 0, 0, 0, 0,
136 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
137 0, 0, -1, -1, FB_ACCELF_TEXT, 27777, 128, 24, 22, 1, 72, 2,
139 FB_VMODE_NONINTERLACED
142 640, 480, 640, 480, 0, 0, 0, 0,
143 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
144 0, 0, -1, -1, FB_ACCELF_TEXT, 31746, 144, 40, 30, 8, 40, 3,
146 FB_VMODE_NONINTERLACED
149 800, 600, 800, 600, 0, 0, 0, 0,
150 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
151 0, 0, -1, -1, FB_ACCELF_TEXT, 25000, 88, 40, 23, 1, 128, 4,
152 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
153 FB_VMODE_NONINTERLACED
156 800, 600, 800, 600, 0, 0, 0, 0,
157 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
158 0, 0, -1, -1, FB_ACCELF_TEXT, 20000, 64, 56, 23, 37, 120, 6,
159 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
160 FB_VMODE_NONINTERLACED
163 1024, 768, 1024, 768, 0, 0, 0, 0,
164 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
165 0, 0, -1, -1, FB_ACCELF_TEXT, 15384, 168, 8, 29, 3, 144, 6,
167 FB_VMODE_NONINTERLACED
170 1152, 864, 1152, 864, 0, 0, 0, 0,
171 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
172 0, 0, -1, -1, FB_ACCELF_TEXT, 11123, 208, 64, 16, 4, 256, 8,
174 FB_VMODE_NONINTERLACED
177 1024, 768, 1024, 768, 0, 0, 0, 0,
178 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
179 0, 0, -1, -1, FB_ACCELF_TEXT, 13333, 144, 24, 29, 3, 136, 6,
181 FB_VMODE_NONINTERLACED
184 1024, 768, 1024, 768, 0, 0, 0, 0,
185 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
186 0, 0, -1, -1, FB_ACCELF_TEXT, 11764, 208, 8, 36, 16, 120, 3,
188 FB_VMODE_NONINTERLACED
191 1152, 864, 1152, 864, 0, 0, 0, 0,
192 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
193 0, 0, -1, -1, FB_ACCELF_TEXT, 10869, 106, 56, 20, 1, 160, 10,
195 FB_VMODE_NONINTERLACED
198 1280, 1024, 1280, 1024, 0, 0, 0, 0,
199 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
200 0, 0, -1, -1, FB_ACCELF_TEXT, 9090, 200, 48, 26, 1, 184, 3,
202 FB_VMODE_NONINTERLACED
205 1024, 768, 1024, 768, 0, 0, 0, 0,
206 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
207 0, 0, -1, -1, FB_ACCELF_TEXT, 10111, 192, 32, 34, 14, 160, 6,
209 FB_VMODE_NONINTERLACED
212 1280, 1024, 1280, 1024, 0, 0, 0, 0,
213 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
214 0, 0, -1, -1, FB_ACCELF_TEXT, 7905, 224, 32, 28, 8, 160, 8,
216 FB_VMODE_NONINTERLACED
219 1152, 864, 1152, 864, 0, 0, 0, 0,
220 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
221 0, 0, -1, -1, FB_ACCELF_TEXT, 7407, 184, 312, 32, 0, 128, 12,
223 FB_VMODE_NONINTERLACED
226 1280, 1024, 1280, 1024, 0, 0, 0, 0,
227 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
228 0, 0, -1, -1, FB_ACCELF_TEXT, 7407, 248, 32, 34, 3, 104, 3,
230 FB_VMODE_NONINTERLACED
233 1280, 1024, 1280, 1024, 0, 0, 0, 0,
234 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
235 0, 0, -1, -1, FB_ACCELF_TEXT, 6349, 224, 64, 44, 1, 160, 3,
237 FB_VMODE_NONINTERLACED
240 /* These are modes used by the two fixed-frequency monitors I have at home.
241 * You may or may not find these useful.
244 { "WYSE1", { /* 1280x1024 @ 72 Hz, 130 Mhz clock */
245 1280, 1024, 1280, 1024, 0, 0, 0, 0,
246 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
247 0, 0, -1, -1, FB_ACCELF_TEXT, 7692, 192, 32, 47, 0, 192, 5,
248 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
249 FB_VMODE_NONINTERLACED
251 { "IBM3", { /* 1280x1024 @ 70 Hz, 120 Mhz clock */
252 1280, 1024, 1280, 1024, 0, 0, 0, 0,
253 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
254 0, 0, -1, -1, FB_ACCELF_TEXT, 8333, 192, 32, 47, 0, 192, 5,
256 FB_VMODE_NONINTERLACED
260 #define NUM_TOTAL_MODES ARRAY_SIZE(tgafb_predefined)
264 * Interface used by the world
267 static void tgafb_detect(void);
268 static int tgafb_encode_fix(struct fb_fix_screeninfo *fix, const void *fb_par,
269 struct fb_info_gen *info);
270 static int tgafb_decode_var(const struct fb_var_screeninfo *var, void *fb_par,
271 struct fb_info_gen *info);
272 static int tgafb_encode_var(struct fb_var_screeninfo *var, const void *fb_par,
273 struct fb_info_gen *info);
274 static void tgafb_get_par(void *fb_par, struct fb_info_gen *info);
275 static void tgafb_set_par(const void *fb_par, struct fb_info_gen *info);
276 static int tgafb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
277 u_int *transp, struct fb_info *info);
278 static int tgafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
279 u_int transp, struct fb_info *info);
280 static int tgafb_blank(int blank, struct fb_info_gen *info);
281 static void tgafb_set_disp(const void *fb_par, struct display *disp,
282 struct fb_info_gen *info);
285 int tgafb_setup(char*);
288 static void tgafb_set_pll(int f);
290 static int tgafb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
291 struct fb_info *info);
292 static void tgafb_update_palette(void);
297 * Chipset specific functions
301 static void tgafb_detect(void)
307 static int tgafb_encode_fix(struct fb_fix_screeninfo *fix, const void *fb_par,
308 struct fb_info_gen *info)
310 struct tgafb_par *par = (struct tgafb_par *)fb_par;
312 strcpy(fix->id, fb_info.gen.info.modename);
314 fix->type = FB_TYPE_PACKED_PIXELS;
316 if (fb_info.tga_type == TGA_TYPE_8PLANE) {
317 fix->visual = FB_VISUAL_PSEUDOCOLOR;
319 fix->visual = FB_VISUAL_TRUECOLOR;
322 fix->line_length = par->xres * (par->bits_per_pixel >> 3);
323 fix->smem_start = fb_info.tga_fb_base;
324 fix->smem_len = fix->line_length * par->yres;
325 fix->mmio_start = fb_info.tga_regs_base;
326 fix->mmio_len = 0x1000; /* Is this sufficient? */
327 fix->xpanstep = fix->ypanstep = fix->ywrapstep = 0;
328 fix->accel = FB_ACCEL_DEC_TGA;
334 static int tgafb_decode_var(const struct fb_var_screeninfo *var, void *fb_par,
335 struct fb_info_gen *info)
337 struct tgafb_par *par = (struct tgafb_par *)fb_par;
340 if (fb_info.tga_type == TGA_TYPE_8PLANE) {
341 if (var->bits_per_pixel > 8) {
344 par->bits_per_pixel = 8;
346 if (var->bits_per_pixel > 32) {
349 par->bits_per_pixel = 32;
352 /* check the values for sanity */
353 if (var->xres_virtual != var->xres ||
354 var->yres_virtual != var->yres ||
355 var->nonstd || (1000000000/var->pixclock) > TGA_PLL_MAX_FREQ ||
356 (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED
357 #if 0 /* fbmon not done. uncomment for 2.5.x -brad */
358 || !fbmon_valid_timings(var->pixclock, var->htotal, var->vtotal, info))
364 /* encode video timings */
365 par->htimings = ((var->xres/4) & TGA_HORIZ_ACT_LSB) |
366 (((var->xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB);
367 par->vtimings = (var->yres & TGA_VERT_ACTIVE);
368 par->htimings |= ((var->right_margin/4) << 9) & TGA_HORIZ_FP;
369 par->vtimings |= (var->lower_margin << 11) & TGA_VERT_FP;
370 par->htimings |= ((var->hsync_len/4) << 14) & TGA_HORIZ_SYNC;
371 par->vtimings |= (var->vsync_len << 16) & TGA_VERT_SYNC;
372 par->htimings |= ((var->left_margin/4) << 21) & TGA_HORIZ_BP;
373 par->vtimings |= (var->upper_margin << 22) & TGA_VERT_BP;
375 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
376 par->htimings |= TGA_HORIZ_POLARITY;
377 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
378 par->vtimings |= TGA_VERT_POLARITY;
379 if (var->sync & FB_SYNC_ON_GREEN) {
380 par->sync_on_green = 1;
382 par->sync_on_green = 0;
385 /* store other useful values in par */
386 par->xres = var->xres;
387 par->yres = var->yres;
388 par->pll_freq = 1000000000/var->pixclock;
389 par->bits_per_pixel = var->bits_per_pixel;
395 static int tgafb_encode_var(struct fb_var_screeninfo *var, const void *fb_par,
396 struct fb_info_gen *info)
398 struct tgafb_par *par = (struct tgafb_par *)fb_par;
400 /* decode video timings */
401 var->xres = ((par->htimings & TGA_HORIZ_ACT_LSB) | ((par->htimings & TGA_HORIZ_ACT_MSB) >> 19)) * 4;
402 var->yres = (par->vtimings & TGA_VERT_ACTIVE);
403 var->right_margin = ((par->htimings & TGA_HORIZ_FP) >> 9) * 4;
404 var->lower_margin = ((par->vtimings & TGA_VERT_FP) >> 11);
405 var->hsync_len = ((par->htimings & TGA_HORIZ_SYNC) >> 14) * 4;
406 var->vsync_len = ((par->vtimings & TGA_VERT_SYNC) >> 16);
407 var->left_margin = ((par->htimings & TGA_HORIZ_BP) >> 21) * 4;
408 var->upper_margin = ((par->vtimings & TGA_VERT_BP) >> 22);
410 if (par->htimings & TGA_HORIZ_POLARITY)
411 var->sync |= FB_SYNC_HOR_HIGH_ACT;
412 if (par->vtimings & TGA_VERT_POLARITY)
413 var->sync |= FB_SYNC_VERT_HIGH_ACT;
414 if (par->sync_on_green == 1)
415 var->sync |= FB_SYNC_ON_GREEN;
417 var->xres_virtual = var->xres;
418 var->yres_virtual = var->yres;
419 var->xoffset = var->yoffset = 0;
422 if (fb_info.tga_type == TGA_TYPE_8PLANE) {
424 var->green.offset = 0;
425 var->blue.offset = 0;
427 var->red.offset = 16;
428 var->green.offset = 8;
429 var->blue.offset = 0;
431 var->bits_per_pixel = par->bits_per_pixel;
433 var->red.length = var->green.length = var->blue.length = 8;
434 var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
435 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
438 var->xoffset = var->yoffset = 0;
439 var->pixclock = 1000000000/par->pll_freq;
442 var->height = var->width = -1;
443 var->accel_flags = 0;
449 static void tgafb_get_par(void *fb_par, struct fb_info_gen *info)
451 struct tgafb_par *par = (struct tgafb_par *)fb_par;
453 if (current_par_valid)
456 if (fb_info.tga_type == TGA_TYPE_8PLANE)
457 default_var.bits_per_pixel = 8;
459 default_var.bits_per_pixel = 32;
461 tgafb_decode_var(&default_var, par, info);
466 static void tgafb_set_par(const void *fb_par, struct fb_info_gen *info)
469 struct tgafb_par *par = (struct tgafb_par *)fb_par;
472 /* XXX this will break console switching with X11, maybe I need to test KD_GRAPHICS? */
473 /* if current_par is valid, check to see if we need to change anything */
474 if (current_par_valid) {
475 if (!memcmp(par, ¤t_par, sizeof current_par)) {
481 current_par_valid = 1;
483 /* first, disable video */
484 TGA_WRITE_REG(TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
486 /* write the DEEP register */
487 while (TGA_READ_REG(TGA_CMD_STAT_REG) & 1) /* wait for not busy */
491 TGA_WRITE_REG(deep_presets[fb_info.tga_type], TGA_DEEP_REG);
492 while (TGA_READ_REG(TGA_CMD_STAT_REG) & 1) /* wait for not busy */
496 /* write some more registers */
497 TGA_WRITE_REG(rasterop_presets[fb_info.tga_type], TGA_RASTEROP_REG);
498 TGA_WRITE_REG(mode_presets[fb_info.tga_type], TGA_MODE_REG);
499 TGA_WRITE_REG(base_addr_presets[fb_info.tga_type], TGA_BASE_ADDR_REG);
501 /* calculate & write the PLL */
502 tgafb_set_pll(par->pll_freq);
504 /* write some more registers */
505 TGA_WRITE_REG(0xffffffff, TGA_PLANEMASK_REG);
506 TGA_WRITE_REG(0xffffffff, TGA_PIXELMASK_REG);
507 TGA_WRITE_REG(0x12345678, TGA_BLOCK_COLOR0_REG);
508 TGA_WRITE_REG(0x12345678, TGA_BLOCK_COLOR1_REG);
510 /* init video timing regs */
511 TGA_WRITE_REG(par->htimings, TGA_HORIZ_REG);
512 TGA_WRITE_REG(par->vtimings, TGA_VERT_REG);
514 /* initalise RAMDAC */
515 if (fb_info.tga_type == TGA_TYPE_8PLANE) {
517 /* init BT485 RAMDAC registers */
518 BT485_WRITE(0xa2 | (par->sync_on_green ? 0x8 : 0x0), BT485_CMD_0);
519 BT485_WRITE(0x01, BT485_ADDR_PAL_WRITE);
520 BT485_WRITE(0x14, BT485_CMD_3); /* cursor 64x64 */
521 BT485_WRITE(0x40, BT485_CMD_1);
522 BT485_WRITE(0x20, BT485_CMD_2); /* cursor off, for now */
523 BT485_WRITE(0xff, BT485_PIXEL_MASK);
525 /* fill palette registers */
526 BT485_WRITE(0x00, BT485_ADDR_PAL_WRITE);
527 TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
529 for (i = 0; i < 16; i++) {
531 TGA_WRITE_REG(default_red[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
532 TGA_WRITE_REG(default_grn[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
533 TGA_WRITE_REG(default_blu[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
534 palette[i].red=default_red[j];
535 palette[i].green=default_grn[j];
536 palette[i].blue=default_blu[j];
538 for (i = 0; i < 240*3; i += 4) {
539 TGA_WRITE_REG(0x55|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
540 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
541 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
542 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
545 } else { /* 24-plane or 24plusZ */
547 /* init BT463 registers */
548 BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
549 BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
550 BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_2,
551 (par->sync_on_green ? 0x80 : 0x40));
553 BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
554 BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
555 BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
556 BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
558 BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
559 BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
560 BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
561 BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
563 /* fill the palette */
564 BT463_LOAD_ADDR(0x0000);
565 TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG);
567 for (i = 0; i < 16; i++) {
569 TGA_WRITE_REG(default_red[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
570 TGA_WRITE_REG(default_grn[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
571 TGA_WRITE_REG(default_blu[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
573 for (i = 0; i < 512*3; i += 4) {
574 TGA_WRITE_REG(0x55|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
575 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
576 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
577 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
580 /* fill window type table after start of vertical retrace */
581 while (!(TGA_READ_REG(TGA_INTR_STAT_REG) & 0x01))
583 TGA_WRITE_REG(0x01, TGA_INTR_STAT_REG);
585 while (!(TGA_READ_REG(TGA_INTR_STAT_REG) & 0x01))
587 TGA_WRITE_REG(0x01, TGA_INTR_STAT_REG);
589 BT463_LOAD_ADDR(BT463_WINDOW_TYPE_BASE);
590 TGA_WRITE_REG((BT463_REG_ACC<<2), TGA_RAMDAC_SETUP_REG);
592 for (i = 0; i < 16; i++) {
593 TGA_WRITE_REG(0x00|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
594 TGA_WRITE_REG(0x01|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
595 TGA_WRITE_REG(0x80|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
600 /* finally, enable video scan
601 (and pray for the monitor... :-) */
602 TGA_WRITE_REG(TGA_VALID_VIDEO, TGA_VALID_REG);
606 #define DIFFCHECK(x) { if( m <= 0x3f ) { \
607 int delta = f - (TGA_PLL_BASE_FREQ * (x)) / (r << shift); \
608 if (delta < 0) delta = -delta; \
609 if (delta < min_diff) min_diff = delta, vm = m, va = a, vr = r; } }
611 static void tgafb_set_pll(int f)
613 int n, shift, base, min_diff, target;
614 int r,a,m,vm = 34, va = 1, vr = 30;
616 for( r = 0 ; r < 12 ; r++ )
617 TGA_WRITE_REG(!r, TGA_CLOCK_REG);
619 if (f > TGA_PLL_MAX_FREQ)
620 f = TGA_PLL_MAX_FREQ;
622 if (f >= TGA_PLL_MAX_FREQ / 2)
624 else if (f >= TGA_PLL_MAX_FREQ / 4)
629 TGA_WRITE_REG(shift & 1, TGA_CLOCK_REG);
630 TGA_WRITE_REG(shift >> 1, TGA_CLOCK_REG);
632 for( r = 0 ; r < 10 ; r++ ) {
633 TGA_WRITE_REG(0, TGA_CLOCK_REG);
637 TGA_WRITE_REG(0, TGA_CLOCK_REG);
638 TGA_WRITE_REG(0, TGA_CLOCK_REG);
640 else if (f <= 200000) {
641 TGA_WRITE_REG(1, TGA_CLOCK_REG);
642 TGA_WRITE_REG(0, TGA_CLOCK_REG);
645 TGA_WRITE_REG(0, TGA_CLOCK_REG);
646 TGA_WRITE_REG(1, TGA_CLOCK_REG);
649 TGA_WRITE_REG(1, TGA_CLOCK_REG);
650 TGA_WRITE_REG(0, TGA_CLOCK_REG);
651 TGA_WRITE_REG(0, TGA_CLOCK_REG);
652 TGA_WRITE_REG(1, TGA_CLOCK_REG);
653 TGA_WRITE_REG(0, TGA_CLOCK_REG);
654 TGA_WRITE_REG(1, TGA_CLOCK_REG);
656 target = (f << shift) / TGA_PLL_BASE_FREQ;
657 min_diff = TGA_PLL_MAX_FREQ;
665 for (n = base < 7 ? 7 : base ; n < base + target && n < 449; n++) {
666 m = ((n + 3) / 7) - 1;
668 DIFFCHECK((m + 1) * 7);
670 DIFFCHECK((m + 1) * 7);
681 for( r=0; r<8 ; r++) {
682 TGA_WRITE_REG((vm >> r) & 1, TGA_CLOCK_REG);
684 for( r=0; r<8 ; r++) {
685 TGA_WRITE_REG((va >> r) & 1, TGA_CLOCK_REG);
687 for( r=0; r<7 ; r++) {
688 TGA_WRITE_REG((vr >> r) & 1, TGA_CLOCK_REG);
690 TGA_WRITE_REG(((vr >> 7) & 1)|2, TGA_CLOCK_REG);
694 static int tgafb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
695 u_int *transp, struct fb_info *info)
699 *red = (palette[regno].red<<8) | palette[regno].red;
700 *green = (palette[regno].green<<8) | palette[regno].green;
701 *blue = (palette[regno].blue<<8) | palette[regno].blue;
707 static int tgafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
708 u_int transp, struct fb_info *info)
715 palette[regno].red = red;
716 palette[regno].green = green;
717 palette[regno].blue = blue;
719 #ifdef FBCON_HAS_CFB32
720 if (regno < 16 && fb_info.tga_type != TGA_TYPE_8PLANE)
721 fbcon_cfb32_cmap[regno] = (red << 16) | (green << 8) | blue;
724 if (fb_info.tga_type == TGA_TYPE_8PLANE) {
725 BT485_WRITE(regno, BT485_ADDR_PAL_WRITE);
726 TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
727 TGA_WRITE_REG(red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
728 TGA_WRITE_REG(green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
729 TGA_WRITE_REG(blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
731 /* How to set a single color register on 24-plane cards?? */
738 * FIXME: since I don't know how to set a single arbitrary color register
739 * on 24-plane cards, all color palette registers have to be updated
742 static int tgafb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
743 struct fb_info *info)
747 if (!fb_display[con].cmap.len) { /* no colormap allocated? */
748 if ((err = fb_alloc_cmap(&fb_display[con].cmap, 256, 0)))
751 if (con == currcon) { /* current console? */
752 err = fb_set_cmap(cmap, kspc, tgafb_setcolreg, info);
754 if (fb_info.tga_type != TGA_TYPE_8PLANE)
755 tgafb_update_palette();
759 fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
763 static void tgafb_update_palette(void)
767 BT463_LOAD_ADDR(0x0000);
768 TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG);
770 for (i = 0; i < 256; i++) {
771 TGA_WRITE_REG(palette[i].red|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
772 TGA_WRITE_REG(palette[i].green|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
773 TGA_WRITE_REG(palette[i].blue|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
779 static int tgafb_blank(int blank, struct fb_info_gen *info)
781 static int tga_vesa_blanked = 0;
782 u32 vhcr, vvcr, vvvr;
788 vhcr = TGA_READ_REG(TGA_HORIZ_REG);
789 vvcr = TGA_READ_REG(TGA_VERT_REG);
790 vvvr = TGA_READ_REG(TGA_VALID_REG) & ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
793 case 0: /* Unblanking */
794 if (tga_vesa_blanked) {
795 TGA_WRITE_REG(vhcr & 0xbfffffff, TGA_HORIZ_REG);
796 TGA_WRITE_REG(vvcr & 0xbfffffff, TGA_VERT_REG);
797 tga_vesa_blanked = 0;
799 TGA_WRITE_REG(vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
802 case 1: /* Normal blanking */
803 TGA_WRITE_REG(vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
806 case 2: /* VESA blank (vsync off) */
807 TGA_WRITE_REG(vvcr | 0x40000000, TGA_VERT_REG);
808 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
809 tga_vesa_blanked = 1;
812 case 3: /* VESA blank (hsync off) */
813 TGA_WRITE_REG(vhcr | 0x40000000, TGA_HORIZ_REG);
814 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
815 tga_vesa_blanked = 1;
818 case 4: /* Poweroff */
819 TGA_WRITE_REG(vhcr | 0x40000000, TGA_HORIZ_REG);
820 TGA_WRITE_REG(vvcr | 0x40000000, TGA_VERT_REG);
821 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
822 tga_vesa_blanked = 1;
826 restore_flags(flags);
831 static void tgafb_set_disp(const void *fb_par, struct display *disp,
832 struct fb_info_gen *info)
834 disp->screen_base = (char *)fb_info.tga_fb_base;
835 switch (fb_info.tga_type) {
836 #ifdef FBCON_HAS_CFB8
837 case TGA_TYPE_8PLANE:
838 disp->dispsw = &fbcon_cfb8;
841 #ifdef FBCON_HAS_CFB32
842 case TGA_TYPE_24PLANE:
843 case TGA_TYPE_24PLUSZ:
844 disp->dispsw = &fbcon_cfb32;
845 disp->dispsw_data = &fbcon_cfb32_cmap;
849 disp->dispsw = &fbcon_dummy;
852 disp->scrollmode = SCROLL_YREDRAW;
856 struct fbgen_hwswitch tgafb_hwswitch = {
857 tgafb_detect, tgafb_encode_fix, tgafb_decode_var, tgafb_encode_var, tgafb_get_par,
858 tgafb_set_par, tgafb_getcolreg, tgafb_setcolreg, NULL, tgafb_blank,
864 * Hardware Independent functions
869 * Frame buffer operations
872 static struct fb_ops tgafb_ops = {
874 fb_get_fix: fbgen_get_fix,
875 fb_get_var: fbgen_get_var,
876 fb_set_var: fbgen_set_var,
877 fb_get_cmap: fbgen_get_cmap,
878 fb_set_cmap: tgafb_set_cmap,
887 int __init tgafb_setup(char *options) {
891 if (options && *options) {
892 while ((this_opt = strsep(&options, ",")) != NULL) {
893 if (!*this_opt) { continue; }
895 if (!strncmp(this_opt, "font:", 5)) {
896 strncpy(default_fontname, this_opt+5, sizeof default_fontname);
899 else if (!strncmp(this_opt, "mode:", 5)) {
900 for (i = 0; i < NUM_TOTAL_MODES; i++) {
901 if (!strcmp(this_opt+5, tgafb_predefined[i].name))
902 default_var = tgafb_predefined[i].var;
903 default_var_valid = 1;
908 printk(KERN_ERR "tgafb: unknown parameter %s\n", this_opt);
921 int __init tgafb_init(void)
923 struct pci_dev *pdev;
925 pdev = pci_find_device(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, NULL);
929 /* divine board type */
931 fb_info.tga_mem_base = (unsigned long)ioremap(pdev->resource[0].start, 0);
932 fb_info.tga_type = (readl(fb_info.tga_mem_base) >> 12) & 0x0f;
933 fb_info.tga_regs_base = fb_info.tga_mem_base + TGA_REGS_OFFSET;
934 fb_info.tga_fb_base = (fb_info.tga_mem_base
935 + fb_offset_presets[fb_info.tga_type]);
936 pci_read_config_byte(pdev, PCI_REVISION_ID, &fb_info.tga_chip_rev);
938 /* setup framebuffer */
940 fb_info.gen.info.node = -1;
941 fb_info.gen.info.flags = FBINFO_FLAG_DEFAULT;
942 fb_info.gen.info.fbops = &tgafb_ops;
943 fb_info.gen.info.disp = &disp;
944 fb_info.gen.info.changevar = NULL;
945 fb_info.gen.info.switch_con = &fbgen_switch;
946 fb_info.gen.info.updatevar = &fbgen_update_var;
947 fb_info.gen.info.blank = &fbgen_blank;
948 strcpy(fb_info.gen.info.fontname, default_fontname);
949 fb_info.gen.parsize = sizeof (struct tgafb_par);
950 fb_info.gen.fbhw = &tgafb_hwswitch;
951 fb_info.gen.fbhw->detect();
953 printk (KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n", fb_info.tga_chip_rev);
954 printk (KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
955 pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
957 switch (fb_info.tga_type)
959 case TGA_TYPE_8PLANE:
960 strcpy (fb_info.gen.info.modename,"Digital ZLXp-E1");
963 case TGA_TYPE_24PLANE:
964 strcpy (fb_info.gen.info.modename,"Digital ZLXp-E2");
967 case TGA_TYPE_24PLUSZ:
968 strcpy (fb_info.gen.info.modename,"Digital ZLXp-E3");
972 /* This should give a reasonable default video mode */
974 if (!default_var_valid) {
975 default_var = tgafb_predefined[0].var;
977 fbgen_get_var(&disp.var, -1, &fb_info.gen.info);
978 disp.var.activate = FB_ACTIVATE_NOW;
979 fbgen_do_set_var(&disp.var, 1, &fb_info.gen);
980 fbgen_set_disp(-1, &fb_info.gen);
981 fbgen_install_cmap(0, &fb_info.gen);
982 if (register_framebuffer(&fb_info.gen.info) < 0)
984 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
985 GET_FB_IDX(fb_info.gen.info.node), fb_info.gen.info.modename,
986 pdev->resource[0].start);
995 void __exit tgafb_cleanup(void)
997 unregister_framebuffer(&fb_info.gen.info);
1006 MODULE_LICENSE("GPL");
1007 module_init(tgafb_init);
1010 module_exit(tgafb_cleanup);