5 * Structure definitions for SMP machines following the
6 * Intel Multiprocessing Specification 1.1 and 1.4.
10 * This tag identifies where the SMP configuration
14 #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
17 * a maximum of 16 APICs with the current APIC ID architecture.
18 * xAPICs can have up to 256. SAPICs have 16 ID bits.
20 #ifdef CONFIG_X86_CLUSTERED_APIC
26 #define MAX_MPC_ENTRY 1024
28 struct intel_mp_floating
30 char mpf_signature[4]; /* "_MP_" */
31 unsigned long mpf_physptr; /* Configuration table address */
32 unsigned char mpf_length; /* Our length (paragraphs) */
33 unsigned char mpf_specification;/* Specification version */
34 unsigned char mpf_checksum; /* Checksum (makes sum 0) */
35 unsigned char mpf_feature1; /* Standard or configuration ? */
36 unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
37 unsigned char mpf_feature3; /* Unused (0) */
38 unsigned char mpf_feature4; /* Unused (0) */
39 unsigned char mpf_feature5; /* Unused (0) */
42 struct mp_config_table
44 char mpc_signature[4];
45 #define MPC_SIGNATURE "PCMP"
46 unsigned short mpc_length; /* Size of table */
47 char mpc_spec; /* 0x01 */
50 char mpc_productid[12];
51 unsigned long mpc_oemptr; /* 0 if not present */
52 unsigned short mpc_oemsize; /* 0 if not present */
53 unsigned short mpc_oemcount;
54 unsigned long mpc_lapic; /* APIC address */
55 unsigned long reserved;
58 /* Followed by entries */
60 #define MP_PROCESSOR 0
65 #define MP_TRANSLATION 192 /* Used by IBM NUMA-Q to describe node locality */
67 struct mpc_config_processor
69 unsigned char mpc_type;
70 unsigned char mpc_apicid; /* Local APIC number */
71 unsigned char mpc_apicver; /* Its versions */
72 unsigned char mpc_cpuflag;
73 #define CPU_ENABLED 1 /* Processor is available */
74 #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
75 unsigned long mpc_cpufeature;
76 #define CPU_STEPPING_MASK 0x0F
77 #define CPU_MODEL_MASK 0xF0
78 #define CPU_FAMILY_MASK 0xF00
79 unsigned long mpc_featureflag; /* CPUID feature value */
80 unsigned long mpc_reserved[2];
85 unsigned char mpc_type;
86 unsigned char mpc_busid;
87 unsigned char mpc_bustype[6];
90 /* List of Bus Type string values, Intel MP Spec. */
91 #define BUSTYPE_EISA "EISA"
92 #define BUSTYPE_ISA "ISA"
93 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */
94 #define BUSTYPE_MCA "MCA"
95 #define BUSTYPE_VL "VL" /* Local bus */
96 #define BUSTYPE_PCI "PCI"
97 #define BUSTYPE_PCMCIA "PCMCIA"
98 #define BUSTYPE_CBUS "CBUS"
99 #define BUSTYPE_CBUSII "CBUSII"
100 #define BUSTYPE_FUTURE "FUTURE"
101 #define BUSTYPE_MBI "MBI"
102 #define BUSTYPE_MBII "MBII"
103 #define BUSTYPE_MPI "MPI"
104 #define BUSTYPE_MPSA "MPSA"
105 #define BUSTYPE_NUBUS "NUBUS"
106 #define BUSTYPE_TC "TC"
107 #define BUSTYPE_VME "VME"
108 #define BUSTYPE_XPRESS "XPRESS"
110 struct mpc_config_ioapic
112 unsigned char mpc_type;
113 unsigned char mpc_apicid;
114 unsigned char mpc_apicver;
115 unsigned char mpc_flags;
116 #define MPC_APIC_USABLE 0x01
117 unsigned long mpc_apicaddr;
120 struct mpc_config_intsrc
122 unsigned char mpc_type;
123 unsigned char mpc_irqtype;
124 unsigned short mpc_irqflag;
125 unsigned char mpc_srcbus;
126 unsigned char mpc_srcbusirq;
127 unsigned char mpc_dstapic;
128 unsigned char mpc_dstirq;
131 enum mp_irq_source_types {
138 #define MP_IRQDIR_DEFAULT 0
139 #define MP_IRQDIR_HIGH 1
140 #define MP_IRQDIR_LOW 3
143 struct mpc_config_lintsrc
145 unsigned char mpc_type;
146 unsigned char mpc_irqtype;
147 unsigned short mpc_irqflag;
148 unsigned char mpc_srcbusid;
149 unsigned char mpc_srcbusirq;
150 unsigned char mpc_destapic;
151 #define MP_APIC_ALL 0xFF
152 unsigned char mpc_destapiclint;
155 struct mp_config_oemtable
157 char oem_signature[4];
158 #define MPC_OEM_SIGNATURE "_OEM"
159 unsigned short oem_length; /* Size of table */
160 char oem_rev; /* 0x01 */
165 struct mpc_config_translation
167 unsigned char mpc_type;
168 unsigned char trans_len;
169 unsigned char trans_type;
170 unsigned char trans_quad;
171 unsigned char trans_global;
172 unsigned char trans_local;
173 unsigned short trans_reserved;
177 * Default configurations
179 * 1 2 CPU ISA 82489DX
180 * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
181 * 3 2 CPU EISA 82489DX
182 * 4 2 CPU MCA 82489DX
188 #ifdef CONFIG_MULTIQUAD
189 #define MAX_IRQ_SOURCES 512
190 #else /* !CONFIG_MULTIQUAD */
191 #define MAX_IRQ_SOURCES 256
192 #endif /* CONFIG_MULTIQUAD */
194 #define MAX_MP_BUSSES 32
201 extern int *mp_bus_id_to_type;
202 extern int *mp_bus_id_to_node;
203 extern int *mp_bus_id_to_local;
204 extern int *mp_bus_id_to_pci_bus;
205 extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
207 extern unsigned int boot_cpu_physical_apicid;
208 extern unsigned long phys_cpu_present_map;
209 extern int smp_found_config;
210 extern void find_smp_config (void);
211 extern void get_smp_config (void);
212 extern int nr_ioapics;
213 extern int apic_version [MAX_APICS];
214 extern int mp_irq_entries;
215 extern struct mpc_config_intsrc *mp_irqs;
216 extern int mpc_default_type;
217 extern int mp_current_pci_id;
218 extern unsigned long mp_lapic_addr;
220 extern int using_apic_timer;
222 #ifdef CONFIG_ACPI_BOOT
223 extern void mp_register_lapic (u8 id, u8 enabled);
224 extern void mp_register_lapic_address (u64 address);
226 #ifdef CONFIG_X86_IO_APIC
227 extern void mp_register_ioapic (u8 id, u32 address, u32 irq_base);
228 extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 global_irq);
229 extern void mp_config_acpi_legacy_irqs (void);
230 extern void mp_parse_prt (void);
231 extern int mp_irqs_alloc(void);
232 #endif /*!CONFIG_X86_IO_APIC*/
234 #endif /*CONFIG_ACPI_BOOT*/