2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <linux/cache.h>
18 #include <linux/config.h>
19 #include <linux/threads.h>
22 * Default implementation of macro that returns current
23 * instruction pointer ("program counter").
25 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
28 * CPU type and hardware bug flags. Kept separately for each CPU.
29 * Members of this structure are referenced in head.S, so think twice
30 * before touching them. [mj]
34 __u8 x86; /* CPU family */
35 __u8 x86_vendor; /* CPU vendor */
38 char wp_works_ok; /* It doesn't on 386's */
39 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
42 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
43 __u32 x86_capability[NCAPINTS];
44 char x86_vendor_id[16];
45 char x86_model_id[64];
46 int x86_cache_size; /* in KB - valid for CPUS which support this
51 unsigned long loops_per_jiffy;
52 unsigned long *pgd_quick;
53 unsigned long *pmd_quick;
54 unsigned long *pte_quick;
55 unsigned long pgtable_cache_sz;
56 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
58 #define X86_VENDOR_INTEL 0
59 #define X86_VENDOR_CYRIX 1
60 #define X86_VENDOR_AMD 2
61 #define X86_VENDOR_UMC 3
62 #define X86_VENDOR_NEXGEN 4
63 #define X86_VENDOR_CENTAUR 5
64 #define X86_VENDOR_RISE 6
65 #define X86_VENDOR_TRANSMETA 7
66 #define X86_VENDOR_NSC 8
67 #define X86_VENDOR_SIS 9
68 #define X86_VENDOR_UNKNOWN 0xff
71 * capabilities of CPUs
74 extern struct cpuinfo_x86 boot_cpu_data;
77 extern struct cpuinfo_x86 cpu_data[];
78 #define current_cpu_data cpu_data[smp_processor_id()]
80 #define cpu_data (&boot_cpu_data)
81 #define current_cpu_data boot_cpu_data
84 extern char ignore_irq13;
86 extern void identify_cpu(struct cpuinfo_x86 *);
87 extern void print_cpu_info(struct cpuinfo_x86 *);
88 extern void dodgy_tsc(void);
93 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
94 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
95 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
96 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
97 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
98 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
99 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
100 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
101 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
102 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
103 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
104 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
105 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
106 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
107 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
108 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
109 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
112 * Generic CPUID function
114 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
125 * CPUID functions returning a single datum
127 static inline unsigned int cpuid_eax(unsigned int op)
137 static inline unsigned int cpuid_ebx(unsigned int op)
139 unsigned int eax, ebx;
142 : "=a" (eax), "=b" (ebx)
147 static inline unsigned int cpuid_ecx(unsigned int op)
149 unsigned int eax, ecx;
152 : "=a" (eax), "=c" (ecx)
157 static inline unsigned int cpuid_edx(unsigned int op)
159 unsigned int eax, edx;
162 : "=a" (eax), "=d" (edx)
169 * Intel CPU features in CR4
171 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
172 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
173 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
174 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
175 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
176 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
177 #define X86_CR4_MCE 0x0040 /* Machine check enable */
178 #define X86_CR4_PGE 0x0080 /* enable global pages */
179 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
180 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
181 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
183 #define load_cr3(pgdir) \
184 asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)));
187 * Save the cr4 feature set we're using (ie
188 * Pentium 4MB enable and PPro Global page
189 * enable), so that any CPU's that boot up
190 * after us can get the correct flags.
192 extern unsigned long mmu_cr4_features;
194 static inline void set_in_cr4 (unsigned long mask)
196 mmu_cr4_features |= mask;
197 __asm__("movl %%cr4,%%eax\n\t"
204 static inline void clear_in_cr4 (unsigned long mask)
206 mmu_cr4_features &= ~mask;
207 __asm__("movl %%cr4,%%eax\n\t"
215 * Cyrix CPU configuration register indexes
217 #define CX86_CCR0 0xc0
218 #define CX86_CCR1 0xc1
219 #define CX86_CCR2 0xc2
220 #define CX86_CCR3 0xc3
221 #define CX86_CCR4 0xe8
222 #define CX86_CCR5 0xe9
223 #define CX86_CCR6 0xea
224 #define CX86_CCR7 0xeb
225 #define CX86_DIR0 0xfe
226 #define CX86_DIR1 0xff
227 #define CX86_ARR_BASE 0xc4
228 #define CX86_RCR_BASE 0xdc
231 * Cyrix CPU indexed register access macros
234 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
236 #define setCx86(reg, data) do { \
238 outb((data), 0x23); \
242 * Bus types (default is ISA, but people can check others with these..)
251 /* from system description table in BIOS. Mostly for MCA use, but
252 others may find it useful. */
253 extern unsigned int machine_id;
254 extern unsigned int machine_submodel_id;
255 extern unsigned int BIOS_revision;
256 extern unsigned int mca_pentium_flag;
259 * User space process size: 3GB (default).
261 #define TASK_SIZE (PAGE_OFFSET)
263 /* This decides where the kernel will search for a free chunk of vm
264 * space during mmap's.
266 #define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
269 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
271 #define IO_BITMAP_SIZE 32
272 #define IO_BITMAP_BYTES (IO_BITMAP_SIZE * 4)
273 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
274 #define INVALID_IO_BITMAP_OFFSET 0x8000
276 struct i387_fsave_struct {
284 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
285 long status; /* software status information */
288 struct i387_fxsave_struct {
299 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
300 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
302 } __attribute__ ((aligned (16)));
304 struct i387_soft_struct {
312 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
313 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
315 unsigned long entry_eip;
319 struct i387_fsave_struct fsave;
320 struct i387_fxsave_struct fxsave;
321 struct i387_soft_struct soft;
329 unsigned short back_link,__blh;
331 unsigned short ss0,__ss0h;
333 unsigned short ss1,__ss1h;
335 unsigned short ss2,__ss2h;
338 unsigned long eflags;
339 unsigned long eax,ecx,edx,ebx;
344 unsigned short es, __esh;
345 unsigned short cs, __csh;
346 unsigned short ss, __ssh;
347 unsigned short ds, __dsh;
348 unsigned short fs, __fsh;
349 unsigned short gs, __gsh;
350 unsigned short ldt, __ldth;
351 unsigned short trace, bitmap;
352 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
354 * pads the TSS to be cacheline-aligned (size is 0x100)
356 unsigned long __cacheline_filler[5];
359 extern struct tss_struct init_tss[NR_CPUS];
361 struct thread_struct {
367 /* Hardware debugging registers */
368 unsigned long debugreg[8]; /* %%db0-7 debug registers */
370 unsigned long cr2, trap_no, error_code;
371 /* floating point info */
372 union i387_union i387;
373 /* virtual 86 mode info */
374 struct vm86_struct * vm86_info;
375 unsigned long screen_bitmap;
376 unsigned long v86flags, v86mask, saved_esp0;
379 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
382 #define INIT_THREAD { \
385 { [0 ... 7] = 0 }, /* debugging registers */ \
387 { { 0, }, }, /* 387 state */ \
389 0,{~0,} /* io permissions */ \
393 0,0, /* back_link, __blh */ \
394 sizeof(init_stack) + (long) &init_stack, /* esp0 */ \
395 __KERNEL_DS, 0, /* ss0 */ \
396 0,0,0,0,0,0, /* stack1, stack2 */ \
398 0,0, /* eip,eflags */ \
399 0,0,0,0, /* eax,ecx,edx,ebx */ \
400 0,0,0,0, /* esp,ebp,esi,edi */ \
401 0,0,0,0,0,0, /* es,cs,ss */ \
402 0,0,0,0,0,0, /* ds,fs,gs */ \
403 __LDT(0),0, /* ldt */ \
404 0, INVALID_IO_BITMAP_OFFSET, /* tace, bitmap */ \
405 {~0, } /* ioperm */ \
408 #define start_thread(regs, new_eip, new_esp) do { \
409 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
411 regs->xds = __USER_DS; \
412 regs->xes = __USER_DS; \
413 regs->xss = __USER_DS; \
414 regs->xcs = __USER_CS; \
415 regs->eip = new_eip; \
416 regs->esp = new_esp; \
419 /* Forward declaration, a strange C thing */
423 /* Free all resources held by a thread. */
424 extern void release_thread(struct task_struct *);
426 * create a kernel thread without removing it from tasklists
428 extern int arch_kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
430 /* Copy and release all segment info associated with a VM
431 * Unusable due to lack of error handling, use {init_new,destroy}_context
434 static inline void copy_segments(struct task_struct *p, struct mm_struct * mm) { }
435 static inline void release_segments(struct mm_struct * mm) { }
438 * Return saved PC of a blocked thread.
440 static inline unsigned long thread_saved_pc(struct thread_struct *t)
442 return ((unsigned long *)t->esp)[3];
445 unsigned long get_wchan(struct task_struct *p);
446 #define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
447 #define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
449 #define THREAD_SIZE (2*PAGE_SIZE)
450 #define alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
451 #define free_task_struct(p) free_pages((unsigned long) (p), 1)
452 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
454 #define init_task (init_task_union.task)
455 #define init_stack (init_task_union.stack)
457 struct microcode_header {
465 unsigned int datasize;
466 unsigned int totalsize;
467 unsigned int reserved[3];
471 struct microcode_header hdr;
472 unsigned int bits[0];
475 typedef struct microcode microcode_t;
476 typedef struct microcode_header microcode_header_t;
478 /* microcode format is extended from prescott processors */
479 struct extended_signature {
485 struct extended_sigtable {
488 unsigned int reserved[3];
489 struct extended_signature sigs[0];
491 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
492 #define MICROCODE_IOCFREE _IO('6',0)
494 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
495 static inline void rep_nop(void)
497 __asm__ __volatile__("rep;nop" ::: "memory");
500 #define cpu_relax() rep_nop()
502 /* Prefetch instructions for Pentium III and AMD Athlon */
503 #if defined(CONFIG_MPENTIUMIII) || defined (CONFIG_MPENTIUM4)
505 #define ARCH_HAS_PREFETCH
506 extern inline void prefetch(const void *x)
508 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
511 #elif CONFIG_X86_USE_3DNOW
513 #define ARCH_HAS_PREFETCH
514 #define ARCH_HAS_PREFETCHW
515 #define ARCH_HAS_SPINLOCK_PREFETCH
517 extern inline void prefetch(const void *x)
519 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
522 extern inline void prefetchw(const void *x)
524 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
526 #define spin_lock_prefetch(x) prefetchw(x)
530 #endif /* __ASM_I386_PROCESSOR_H */