1 #ifndef __PARISC_SYSTEM_H
2 #define __PARISC_SYSTEM_H
4 #include <linux/config.h>
6 #include <asm/system_irqsave.h>
9 #include <asm/spinlock_t.h>
12 /* The program status word as bitfields. */
44 #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
46 #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
51 extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
53 #define prepare_to_switch() do { } while(0)
54 #define switch_to(prev, next, last) do { \
55 (last) = _switch_to(prev, next); \
60 extern void __global_cli(void);
61 extern void __global_sti(void);
62 extern unsigned long __global_save_flags(void);
63 extern void __global_restore_flags(unsigned long);
65 #define cli() __global_cli()
66 #define sti() __global_sti()
67 #define save_flags(x) ((x)=__global_save_flags())
68 #define restore_flags(x) __global_restore_flags(x)
69 #define save_and_cli(x) do { save_flags(x); cli(); } while(0);
70 #define save_and_sti(x) do { save_flags(x); sti(); } while(0);
76 #define save_flags(x) __save_flags(x)
77 #define restore_flags(x) __restore_flags(x)
78 #define save_and_cli(x) __save_and_cli(x)
79 #define save_and_sti(x) __save_and_sti(x)
84 #define mfctl(reg) ({ \
86 __asm__ __volatile__( \
87 "mfctl " #reg ",%0" : \
93 #define mtctl(gr, cr) \
94 __asm__ __volatile__("mtctl %0,%1" \
98 /* these are here to de-mystefy the calling code, and to provide hooks */
99 /* which I needed for debugging EIEM problems -PB */
100 #define get_eiem() mfctl(15)
101 static inline void set_eiem(unsigned long val)
106 #define mfsp(reg) ({ \
108 __asm__ __volatile__( \
109 "mfsp " #reg ",%0" : \
115 #define mtsp(gr, cr) \
116 __asm__ __volatile__("mtsp %0,%1" \
118 : "r" (gr), "i" (cr))
122 ** This is simply the barrier() macro from linux/kernel.h but when serial.c
123 ** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
124 ** hasn't yet been included yet so it fails, thus repeating the macro here.
126 ** PA-RISC architecture allows for weakly ordered memory accesses although
127 ** none of the processors use it. There is a strong ordered bit that is
128 ** set in the O-bit of the page directory entry. Operating systems that
129 ** can not tolerate out of order accesses should set this bit when mapping
130 ** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
131 ** of the processor implemented the PSW O-bit). The PCX-W ERS states that
132 ** the TLB O-bit is not implemented so the page directory does not need to
133 ** have the O-bit set when mapping pages (section 3.1). This section also
134 ** states that the PSW Y, Z, G, and O bits are not implemented.
135 ** So it looks like nothing needs to be done for parisc-linux (yet).
136 ** (thanks to chada for the above comment -ggg)
138 ** The __asm__ op below simple prevents gcc/ld from reordering
139 ** instructions across the mb() "call".
141 #define mb() __asm__ __volatile__("":::"memory"); /* barrier() */
144 #define smp_mb() mb()
145 #define smp_wmb() mb()
147 #define set_mb(var, value) do { var = value; mb(); } while (0)