3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 //=============================================================================
22 // This control block contains the data that is shared between the
23 // hypervisor (PLIC) and the OS.
26 //----------------------------------------------------------------------------
28 #include <asm/types.h>
37 //=============================================================================
38 // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
39 // NOTE: The xDynXyz fields are fields that will be dynamically changed by
40 // PLIC when preparing to bring a processor online or when dispatching a
42 //=============================================================================
43 u32 xDesc; // Eye catcher 0xD397D781 x00-x03
44 u16 xSize; // Size of this struct x04-x05
45 u16 xRsvd1_0; // Reserved x06-x07
46 u16 xRsvd1_1:14; // Reserved x08-x09
47 u8 xSharedProc:1; // Shared processor indicator ...
48 u8 xSecondaryThread:1; // Secondary thread indicator ...
49 volatile u8 xDynProcStatus:8; // Dynamic Status of this proc x0A-x0A
50 u8 xSecondaryThreadCnt; // Secondary thread count x0B-x0B
51 volatile u16 xDynHvPhysicalProcIndex;// Dynamic HV Physical Proc Index0C-x0D
52 volatile u16 xDynHvLogicalProcIndex;// Dynamic HV Logical Proc Indexx0E-x0F
53 u32 xDecrVal; // Value for Decr programming x10-x13
54 u32 xPMCVal; // Value for PMC regs x14-x17
55 volatile u32 xDynHwNodeId; // Dynamic Hardware Node id x18-x1B
56 volatile u32 xDynHwProcId; // Dynamic Hardware Proc Id x1C-x1F
57 volatile u32 xDynPIR; // Dynamic ProcIdReg value x20-x23
58 u32 xDseiData; // DSEI data x24-x27
59 u64 xSPRG3; // SPRG3 value x28-x2F
60 u8 xRsvd1_3[80]; // Reserved x30-x7F
62 //=============================================================================
63 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
64 //=============================================================================
65 // This Dword contains a byte for each type of interrupt that can occur.
66 // The IPI is a count while the others are just a binary 1 or 0.
70 u16 xRsvd; // Reserved - cleared by #mpasmbl
71 u8 xXirrInt; // Indicates xXirrValue is valid or Immed IO
72 u8 xIpiCnt; // IPI Count
73 u8 xDecrInt; // DECR interrupt occurred
74 u8 xPdcInt; // PDC interrupt occurred
75 u8 xQuantumInt; // Interrupt quantum reached
76 u8 xOldPlicDeferredExtInt; // Old PLIC has a deferred XIRR pending
80 // Whenever any fields in this Dword are set then PLIC will defer the
81 // processing of external interrupts. Note that PLIC will store the
82 // XIRR directly into the xXirrValue field so that another XIRR will
83 // not be presented until this one clears. The layout of the low
84 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
85 // entire Dword is zero or not. A non-zero value in the low order
86 // 2-bytes will result in SLIC being granted the highest thread
87 // priority upon return. A 0 will return to SLIC as medium priority.
88 u64 xPlicDeferIntsArea; // Entire Dword
90 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
91 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
92 u64 xSavedSrr0; // Saved SRR0 x10-x17
93 u64 xSavedSrr1; // Saved SRR1 x18-x1F
95 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
96 u64 xSavedGpr3; // Saved GPR3 x20-x27
97 u64 xSavedGpr4; // Saved GPR4 x28-x2F
98 u64 xSavedGpr5; // Saved GPR5 x30-x37
100 u8 xRsvd2_1; // Reserved x38-x38
101 u8 xCpuCtlsTaskAttributes; // Task attributes for cpuctls x39-x39
102 u8 xFPRegsInUse; // FP regs in use x3A-x3A
103 u8 xPMCRegsInUse; // PMC regs in use x3B-x3B
104 volatile u32 xSavedDecr; // Saved Decr Value x3C-x3F
105 volatile u64 xEmulatedTimeBase;// Emulated TB for this thread x40-x47
106 volatile u64 xCurPLICLatency; // Unaccounted PLIC latency x48-x4F
107 u64 xTotPLICLatency; // Accumulated PLIC latency x50-x57
108 u64 xWaitStateCycles; // Wait cycles for this proc x58-x5F
109 u64 xEndOfQuantum; // TB at end of quantum x60-x67
110 u64 xPDCSavedSPRG1; // Saved SPRG1 for PMC int x68-x6F
111 u64 xPDCSavedSRR0; // Saved SRR0 for PMC int x70-x77
112 volatile u32 xVirtualDecr; // Virtual DECR for shared procsx78-x7B
113 u16 xSLBCount; // # of SLBs to maintain x7C-x7D
114 u8 xIdle; // Indicate OS is idle x7E
115 u8 xRsvd2_2; // Reserved x7F
118 //=============================================================================
119 // CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
120 //=============================================================================
121 // This is the xYieldCount. An "odd" value (low bit on) means that
122 // the processor is yielded (either because of an OS yield or a PLIC
123 // preempt). An even value implies that the processor is currently
125 // NOTE: This value will ALWAYS be zero for dedicated processors and
126 // will NEVER be zero for shared processors (ie, initialized to a 1).
127 volatile u32 xYieldCount; // PLIC increments each dispatchx00-x03
128 u8 xRsvd3_0[124]; // Reserved x04-x7F
130 //=============================================================================
131 // CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
132 //=============================================================================
133 u8 xPmcSaveArea[256]; // PMC interrupt Area x00-xFF
137 #endif // _ITLPPACA_H