include/asm-x86_64/mmu_context.h

   1 #ifndef __X86_64_MMU_CONTEXT_H
   2 #define __X86_64_MMU_CONTEXT_H
   3
   4 #include <linux/config.h>
   5 #include <asm/desc.h>
   6 #include <asm/atomic.h>
   7 #include <asm/pgalloc.h>
   8 #include <asm/pda.h>
   9 #include <asm/pgtable.h>
  10 #include <linux/spinlock.h>
  11
  12 /*
  13  * possibly do the LDT unload here?
  14  */
  15 #define destroy_context(mm)         do { } while(0)
  16 #define init_new_context(tsk,mm)    ({ rwlock_init(&(mm)->context.ldtlock); 0; })
  17
  18 #ifdef CONFIG_SMP
  19
  20 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
  21 {
  22         if(cpu_tlbstate[cpu].state == TLBSTATE_OK)
  23                 cpu_tlbstate[cpu].state = TLBSTATE_LAZY;
  24 }
  25 #else
  26 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
  27 {
  28 }
  29 #endif
  30
  31 #define activate_mm(prev, next) \
  32         switch_mm((prev),(next),NULL,smp_processor_id())
  33
  34
  35 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
  36                              struct task_struct *tsk, unsigned cpu)
  37 {
  38         if (prev != next) {
  39                 /* stop flush ipis for the previous mm */
  40                 clear_bit(cpu, &prev->cpu_vm_mask);
  41                 /*
  42                  * Re-load LDT if necessary
  43                  */
  44                 if (prev->context.segments != next->context.segments)
  45                         load_LDT(next);
  46 #ifdef CONFIG_SMP
  47                 cpu_tlbstate[cpu].state = TLBSTATE_OK;
  48                 cpu_tlbstate[cpu].active_mm = next;
  49 #endif
  50                 set_bit(cpu, &next->cpu_vm_mask);
  51                 set_bit(cpu, &next->context.cpuvalid);
  52                 /* Re-load page tables */
  53                 *read_pda(level4_pgt) = __pa(next->pgd) | _PAGE_TABLE;
  54                 __flush_tlb();
  55         }
  56 #ifdef CONFIG_SMP
  57         else {
  58                 cpu_tlbstate[cpu].state = TLBSTATE_OK;
  59                 if(cpu_tlbstate[cpu].active_mm != next)
  60                         out_of_line_bug();
  61                 if(!test_and_set_bit(cpu, &next->cpu_vm_mask)) {
  62                         /* We were in lazy tlb mode and leave_mm disabled
  63                          * tlb flush IPI delivery. We must reload the page
  64                          * table.
  65                          */
  66                         *read_pda(level4_pgt) = __pa(next->pgd) | _PAGE_TABLE;
  67                         __flush_tlb();
  68                 }
  69                 if (!test_and_set_bit(cpu, &next->context.cpuvalid))
  70                         load_LDT(next);
  71         }
  72 #endif
  73 }
  74
  75 #endif