1 # This is the ID for the *FPGA's* chip TAP. (note this ID is for 85F version
2 # of ULX3S -- if you have a different ECP5 size you can either enter the
3 # correct ID for your ECP5, or remove the -expected-id part). We are going to
4 # expose processor debug through a pair of custom DRs on this TAP.
8 jtag newtap lfe5u85 hazard3 -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
10 #jtag newtap lfe5u85 hazard3 -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5