cpu/ppc4xx/spd_sdram.c

   1 /*
   2  * (C) Copyright 2001
   3  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   4  *
   5  * Based on code by:
   6  *
   7  * Kenneth Johansson ,Ericsson AB.
   8  * kenneth.johansson@etx.ericsson.se
   9  *
  10  * hacked up by bill hunter. fixed so we could run before
  11  * serial_init and console_init. previous version avoided this by
  12  * running out of cache memory during serial/console init, then running
  13  * this code later.
  14  *
  15  * (C) Copyright 2002
  16  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  17  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  18  *
  19  * (C) Copyright 2005
  20  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  21  *
  22  * See file CREDITS for list of people who contributed to this
  23  * project.
  24  *
  25  * This program is free software; you can redistribute it and/or
  26  * modify it under the terms of the GNU General Public License as
  27  * published by the Free Software Foundation; either version 2 of
  28  * the License, or (at your option) any later version.
  29  *
  30  * This program is distributed in the hope that it will be useful,
  31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33  * GNU General Public License for more details.
  34  *
  35  * You should have received a copy of the GNU General Public License
  36  * along with this program; if not, write to the Free Software
  37  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  38  * MA 02111-1307 USA
  39  */
  40
  41 #include <common.h>
  42 #include <asm/processor.h>
  43 #include <i2c.h>
  44 #include <ppc4xx.h>
  45
  46 #ifdef CONFIG_SPD_EEPROM
  47
  48 /*
  49  * Set default values
  50  */
  51 #ifndef CFG_I2C_SPEED
  52 #define CFG_I2C_SPEED   50000
  53 #endif
  54
  55 #ifndef CFG_I2C_SLAVE
  56 #define CFG_I2C_SLAVE   0xFE
  57 #endif
  58
  59 #define ONE_BILLION     1000000000
  60
  61 #ifndef  CONFIG_440             /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
  62
  63 #define  SDRAM0_CFG_DCE         0x80000000
  64 #define  SDRAM0_CFG_SRE         0x40000000
  65 #define  SDRAM0_CFG_PME         0x20000000
  66 #define  SDRAM0_CFG_MEMCHK      0x10000000
  67 #define  SDRAM0_CFG_REGEN       0x08000000
  68 #define  SDRAM0_CFG_ECCDD       0x00400000
  69 #define  SDRAM0_CFG_EMDULR      0x00200000
  70 #define  SDRAM0_CFG_DRW_SHIFT   (31-6)
  71 #define  SDRAM0_CFG_BRPF_SHIFT  (31-8)
  72
  73 #define  SDRAM0_TR_CASL_SHIFT   (31-8)
  74 #define  SDRAM0_TR_PTA_SHIFT    (31-13)
  75 #define  SDRAM0_TR_CTP_SHIFT    (31-15)
  76 #define  SDRAM0_TR_LDF_SHIFT    (31-17)
  77 #define  SDRAM0_TR_RFTA_SHIFT   (31-29)
  78 #define  SDRAM0_TR_RCD_SHIFT    (31-31)
  79
  80 #define  SDRAM0_RTR_SHIFT       (31-15)
  81 #define  SDRAM0_ECCCFG_SHIFT    (31-11)
  82
  83 /* SDRAM0_CFG enable macro  */
  84 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
  85
  86 #define SDRAM0_BXCR_SZ_MASK     0x000e0000
  87 #define SDRAM0_BXCR_AM_MASK     0x0000e000
  88
  89 #define SDRAM0_BXCR_SZ_SHIFT    (31-14)
  90 #define SDRAM0_BXCR_AM_SHIFT    (31-18)
  91
  92 #define SDRAM0_BXCR_SZ(x)       ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
  93 #define SDRAM0_BXCR_AM(x)       ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
  94
  95 #ifdef CONFIG_SPDDRAM_SILENT
  96 # define SPD_ERR(x) do { return 0; } while (0)
  97 #else
  98 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
  99 #endif
 100
 101 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
 102
 103 /* function prototypes */
 104 int spd_read(uint addr);
 105
 106
 107 /*
 108  * This function is reading data from the DIMM module EEPROM over the SPD bus
 109  * and uses that to program the sdram controller.
 110  *
 111  * This works on boards that has the same schematics that the AMCC walnut has.
 112  *
 113  * Input: null for default I2C spd functions or a pointer to a custom function
 114  * returning spd_data.
 115  */
 116
 117 long int spd_sdram(int(read_spd)(uint addr))
 118 {
 119         int tmp,row,col;
 120         int total_size,bank_size,bank_code;
 121         int ecc_on;
 122         int mode;
 123         int bank_cnt;
 124
 125         int sdram0_pmit=0x07c00000;
 126 #ifndef CONFIG_405EP /* not on PPC405EP */
 127         int sdram0_besr0=-1;
 128         int sdram0_besr1=-1;
 129         int sdram0_eccesr=-1;
 130 #endif
 131         int sdram0_ecccfg;
 132
 133         int sdram0_rtr=0;
 134         int sdram0_tr=0;
 135
 136         int sdram0_b0cr;
 137         int sdram0_b1cr;
 138         int sdram0_b2cr;
 139         int sdram0_b3cr;
 140
 141         int sdram0_cfg=0;
 142
 143         int t_rp;
 144         int t_rcd;
 145         int t_ras;
 146         int t_rc;
 147         int min_cas;
 148
 149         PPC405_SYS_INFO sys_info;
 150         unsigned long bus_period_x_10;
 151
 152         /*
 153          * get the board info
 154          */
 155         get_sys_info(&sys_info);
 156         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 157
 158         if (read_spd == 0){
 159                 read_spd=spd_read;
 160                 /*
 161                  * Make sure I2C controller is initialized
 162                  * before continuing.
 163                  */
 164                 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 165         }
 166
 167         /* Make shure we are using SDRAM */
 168         if (read_spd(2) != 0x04) {
 169                 SPD_ERR("SDRAM - non SDRAM memory module found\n");
 170         }
 171
 172         /* ------------------------------------------------------------------
 173          * configure memory timing register
 174          *
 175          * data from DIMM:
 176          * 27   IN Row Precharge Time ( t RP)
 177          * 29   MIN RAS to CAS Delay ( t RCD)
 178          * 127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
 179          * -------------------------------------------------------------------*/
 180
 181         /*
 182          * first figure out which cas latency mode to use
 183          * use the min supported mode
 184          */
 185
 186         tmp = read_spd(127) & 0x6;
 187         if (tmp == 0x02) {              /* only cas = 2 supported */
 188                 min_cas = 2;
 189 /*              t_ck = read_spd(9); */
 190 /*              t_ac = read_spd(10); */
 191         } else if (tmp == 0x04) {       /* only cas = 3 supported */
 192                 min_cas = 3;
 193 /*              t_ck = read_spd(9); */
 194 /*              t_ac = read_spd(10); */
 195         } else if (tmp == 0x06) {       /* 2,3 supported, so use 2 */
 196                 min_cas = 2;
 197 /*              t_ck = read_spd(23); */
 198 /*              t_ac = read_spd(24); */
 199         } else {
 200                 SPD_ERR("SDRAM - unsupported CAS latency \n");
 201         }
 202
 203         /* get some timing values, t_rp,t_rcd,t_ras,t_rc
 204          */
 205         t_rp = read_spd(27);
 206         t_rcd = read_spd(29);
 207         t_ras = read_spd(30);
 208         t_rc = t_ras + t_rp;
 209
 210         /* The following timing calcs subtract 1 before deviding.
 211          * this has effect of using ceiling instead of floor rounding,
 212          * and also subtracting 1 to convert number to reg value
 213          */
 214         /* set up CASL */
 215         sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
 216         /* set up PTA */
 217         sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
 218         /* set up CTP */
 219         tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
 220         if (tmp < 1)
 221                 tmp = 1;
 222         sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
 223         /* set LDF      = 2 cycles, reg value = 1 */
 224         sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
 225         /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
 226         tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
 227         if (tmp < 0)
 228                 tmp = 0;
 229         if (tmp > 6)
 230                 tmp = 6;
 231         sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
 232         /* set RCD = t_rcd/bus_period*/
 233         sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
 234
 235
 236         /*------------------------------------------------------------------
 237          * configure RTR register
 238          * -------------------------------------------------------------------*/
 239         row = read_spd(3);
 240         col = read_spd(4);
 241         tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
 242         switch (tmp) {
 243         case 0x00:
 244                 tmp = 15625;
 245                 break;
 246         case 0x01:
 247                 tmp = 15625 / 4;
 248                 break;
 249         case 0x02:
 250                 tmp = 15625 / 2;
 251                 break;
 252         case 0x03:
 253                 tmp = 15625 * 2;
 254                 break;
 255         case 0x04:
 256                 tmp = 15625 * 4;
 257                 break;
 258         case 0x05:
 259                 tmp = 15625 * 8;
 260                 break;
 261         default:
 262                 SPD_ERR("SDRAM - Bad refresh period \n");
 263         }
 264         /* convert from nsec to bus cycles */
 265         tmp = (tmp * 10) / bus_period_x_10;
 266         sdram0_rtr = (tmp & 0x3ff8) <<  SDRAM0_RTR_SHIFT;
 267
 268         /*------------------------------------------------------------------
 269          * determine the number of banks used
 270          * -------------------------------------------------------------------*/
 271         /* byte 7:6 is module data width */
 272         if (read_spd(7) != 0)
 273                 SPD_ERR("SDRAM - unsupported module width\n");
 274         tmp = read_spd(6);
 275         if (tmp < 32)
 276                 SPD_ERR("SDRAM - unsupported module width\n");
 277         else if (tmp < 64)
 278                 bank_cnt = 1;           /* one bank per sdram side */
 279         else if (tmp < 73)
 280                 bank_cnt = 2;   /* need two banks per side */
 281         else if (tmp < 161)
 282                 bank_cnt = 4;   /* need four banks per side */
 283         else
 284                 SPD_ERR("SDRAM - unsupported module width\n");
 285
 286         /* byte 5 is the module row count (refered to as dimm "sides") */
 287         tmp = read_spd(5);
 288         if (tmp == 1)
 289                 ;
 290         else if (tmp==2)
 291                 bank_cnt *= 2;
 292         else if (tmp==4)
 293                 bank_cnt *= 4;
 294         else
 295                 bank_cnt = 8;           /* 8 is an error code */
 296
 297         if (bank_cnt > 4)       /* we only have 4 banks to work with */
 298                 SPD_ERR("SDRAM - unsupported module rows for this width\n");
 299
 300         /* now check for ECC ability of module. We only support ECC
 301          *   on 32 bit wide devices with 8 bit ECC.
 302          */
 303         if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
 304                 sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
 305                 ecc_on = 1;
 306         } else {
 307                 sdram0_ecccfg = 0;
 308                 ecc_on = 0;
 309         }
 310
 311         /*------------------------------------------------------------------
 312          * calculate total size
 313          * -------------------------------------------------------------------*/
 314         /* calculate total size and do sanity check */
 315         tmp = read_spd(31);
 316         total_size = 1 << 22;   /* total_size = 4MB */
 317         /* now multiply 4M by the smallest device row density */
 318         /* note that we don't support asymetric rows */
 319         while (((tmp & 0x0001) == 0) && (tmp != 0)) {
 320                 total_size = total_size << 1;
 321                 tmp = tmp >> 1;
 322         }
 323         total_size *= read_spd(5);      /* mult by module rows (dimm sides) */
 324
 325         /*------------------------------------------------------------------
 326          * map  rows * cols * banks to a mode
 327          * -------------------------------------------------------------------*/
 328
 329         switch (row) {
 330         case 11:
 331                 switch (col) {
 332                 case 8:
 333                         mode=4; /* mode 5 */
 334                         break;
 335                 case 9:
 336                 case 10:
 337                         mode=0; /* mode 1 */
 338                         break;
 339                 default:
 340                         SPD_ERR("SDRAM - unsupported mode\n");
 341                 }
 342                 break;
 343         case 12:
 344                 switch (col) {
 345                 case 8:
 346                         mode=3; /* mode 4 */
 347                         break;
 348                 case 9:
 349                 case 10:
 350                         mode=1; /* mode 2 */
 351                         break;
 352                 default:
 353                         SPD_ERR("SDRAM - unsupported mode\n");
 354                 }
 355                 break;
 356         case 13:
 357                 switch (col) {
 358                 case 8:
 359                         mode=5; /* mode 6 */
 360                         break;
 361                 case 9:
 362                 case 10:
 363                         if (read_spd(17) == 2)
 364                                 mode = 6; /* mode 7 */
 365                         else
 366                                 mode = 2; /* mode 3 */
 367                         break;
 368                 case 11:
 369                         mode = 2; /* mode 3 */
 370                         break;
 371                 default:
 372                         SPD_ERR("SDRAM - unsupported mode\n");
 373                 }
 374                 break;
 375         default:
 376                 SPD_ERR("SDRAM - unsupported mode\n");
 377         }
 378
 379         /*------------------------------------------------------------------
 380          * using the calculated values, compute the bank
 381          * config register values.
 382          * -------------------------------------------------------------------*/
 383         sdram0_b1cr = 0;
 384         sdram0_b2cr = 0;
 385         sdram0_b3cr = 0;
 386
 387         /* compute the size of each bank */
 388         bank_size = total_size / bank_cnt;
 389         /* convert bank size to bank size code for ppc4xx
 390            by takeing log2(bank_size) - 22 */
 391         tmp = bank_size;                /* start with tmp = bank_size */
 392         bank_code = 0;                  /* and bank_code = 0 */
 393         while (tmp > 1) {               /* this takes log2 of tmp */
 394                 bank_code++;            /* and stores result in bank_code */
 395                 tmp = tmp >> 1;
 396         }                               /* bank_code is now log2(bank_size) */
 397         bank_code -= 22;                /* subtract 22 to get the code */
 398
 399         tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
 400         sdram0_b0cr = (bank_size * 0) | tmp;
 401 #ifndef CONFIG_405EP /* not on PPC405EP */
 402         if (bank_cnt > 1)
 403                 sdram0_b2cr = (bank_size * 1) | tmp;
 404         if (bank_cnt > 2)
 405                 sdram0_b1cr = (bank_size * 2) | tmp;
 406         if (bank_cnt > 3)
 407                 sdram0_b3cr = (bank_size * 3) | tmp;
 408 #else
 409         /* PPC405EP chip only supports two SDRAM banks */
 410         if (bank_cnt > 1)
 411                 sdram0_b1cr = (bank_size * 1) | tmp;
 412         if (bank_cnt > 2)
 413                 total_size = 2 * bank_size;
 414 #endif
 415
 416         /*
 417          *   enable sdram controller DCE=1
 418          *  enable burst read prefetch to 32 bytes BRPF=2
 419          *  leave other functions off
 420          */
 421
 422         /*------------------------------------------------------------------
 423          * now that we've done our calculations, we are ready to
 424          * program all the registers.
 425          * -------------------------------------------------------------------*/
 426
 427 #define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
 428         /* disable memcontroller so updates work */
 429         mtsdram0( mem_mcopt1, 0 );
 430
 431 #ifndef CONFIG_405EP /* not on PPC405EP */
 432         mtsdram0( mem_besra , sdram0_besr0 );
 433         mtsdram0( mem_besrb , sdram0_besr1 );
 434         mtsdram0( mem_ecccf , sdram0_ecccfg );
 435         mtsdram0( mem_eccerr, sdram0_eccesr );
 436 #endif
 437         mtsdram0( mem_rtr   , sdram0_rtr );
 438         mtsdram0( mem_pmit  , sdram0_pmit );
 439         mtsdram0( mem_mb0cf , sdram0_b0cr );
 440         mtsdram0( mem_mb1cf , sdram0_b1cr );
 441 #ifndef CONFIG_405EP /* not on PPC405EP */
 442         mtsdram0( mem_mb2cf , sdram0_b2cr );
 443         mtsdram0( mem_mb3cf , sdram0_b3cr );
 444 #endif
 445         mtsdram0( mem_sdtr1 , sdram0_tr );
 446
 447         /* SDRAM have a power on delay,  500 micro should do */
 448         udelay(500);
 449         sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 450         if (ecc_on)
 451                 sdram0_cfg |= SDRAM0_CFG_MEMCHK;
 452         mtsdram0(mem_mcopt1, sdram0_cfg);
 453
 454         return (total_size);
 455 }
 456
 457 int spd_read(uint addr)
 458 {
 459         uchar data[2];
 460
 461         if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 462                 return (int)data[0];
 463         else
 464                 return 0;
 465 }
 466
 467 #else /* CONFIG_440 */
 468
 469 /*-----------------------------------------------------------------------------
 470   |  Memory Controller Options 0
 471   +-----------------------------------------------------------------------------*/
 472 #define SDRAM_CFG0_DCEN         0x80000000      /* SDRAM Controller Enable      */
 473 #define SDRAM_CFG0_MCHK_MASK    0x30000000      /* Memory data errchecking mask */
 474 #define SDRAM_CFG0_MCHK_NON     0x00000000      /* No ECC generation            */
 475 #define SDRAM_CFG0_MCHK_GEN     0x20000000      /* ECC generation               */
 476 #define SDRAM_CFG0_MCHK_CHK     0x30000000      /* ECC generation and checking  */
 477 #define SDRAM_CFG0_RDEN         0x08000000      /* Registered DIMM enable       */
 478 #define SDRAM_CFG0_PMUD         0x04000000      /* Page management unit         */
 479 #define SDRAM_CFG0_DMWD_MASK    0x02000000      /* DRAM width mask              */
 480 #define SDRAM_CFG0_DMWD_32      0x00000000      /* 32 bits                      */
 481 #define SDRAM_CFG0_DMWD_64      0x02000000      /* 64 bits                      */
 482 #define SDRAM_CFG0_UIOS_MASK    0x00C00000      /* Unused IO State              */
 483 #define SDRAM_CFG0_PDP          0x00200000      /* Page deallocation policy     */
 484
 485 /*-----------------------------------------------------------------------------
 486   |  Memory Controller Options 1
 487   +-----------------------------------------------------------------------------*/
 488 #define SDRAM_CFG1_SRE          0x80000000      /* Self-Refresh Entry           */
 489 #define SDRAM_CFG1_PMEN         0x40000000      /* Power Management Enable      */
 490
 491 /*-----------------------------------------------------------------------------+
 492   |  SDRAM DEVPOT Options
 493   +-----------------------------------------------------------------------------*/
 494 #define SDRAM_DEVOPT_DLL        0x80000000
 495 #define SDRAM_DEVOPT_DS         0x40000000
 496
 497 /*-----------------------------------------------------------------------------+
 498   |  SDRAM MCSTS Options
 499   +-----------------------------------------------------------------------------*/
 500 #define SDRAM_MCSTS_MRSC        0x80000000
 501 #define SDRAM_MCSTS_SRMS        0x40000000
 502 #define SDRAM_MCSTS_CIS         0x20000000
 503
 504 /*-----------------------------------------------------------------------------
 505   |  SDRAM Refresh Timer Register
 506   +-----------------------------------------------------------------------------*/
 507 #define SDRAM_RTR_RINT_MASK       0xFFFF0000
 508 #define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
 509 #define sdram_HZ_to_ns(hertz)     (1000000000/(hertz))
 510
 511 /*-----------------------------------------------------------------------------+
 512   |  SDRAM UABus Base Address Reg
 513   +-----------------------------------------------------------------------------*/
 514 #define SDRAM_UABBA_UBBA_MASK   0x0000000F
 515
 516 /*-----------------------------------------------------------------------------+
 517   |  Memory Bank 0-7 configuration
 518   +-----------------------------------------------------------------------------*/
 519 #define SDRAM_BXCR_SDBA_MASK    0xff800000        /* Base address             */
 520 #define SDRAM_BXCR_SDSZ_MASK    0x000e0000        /* Size                     */
 521 #define SDRAM_BXCR_SDSZ_8       0x00020000        /*   8M                     */
 522 #define SDRAM_BXCR_SDSZ_16      0x00040000        /*  16M                     */
 523 #define SDRAM_BXCR_SDSZ_32      0x00060000        /*  32M                     */
 524 #define SDRAM_BXCR_SDSZ_64      0x00080000        /*  64M                     */
 525 #define SDRAM_BXCR_SDSZ_128     0x000a0000        /* 128M                     */
 526 #define SDRAM_BXCR_SDSZ_256     0x000c0000        /* 256M                     */
 527 #define SDRAM_BXCR_SDSZ_512     0x000e0000        /* 512M                     */
 528 #define SDRAM_BXCR_SDAM_MASK    0x0000e000        /* Addressing mode          */
 529 #define SDRAM_BXCR_SDAM_1       0x00000000        /*   Mode 1                 */
 530 #define SDRAM_BXCR_SDAM_2       0x00002000        /*   Mode 2                 */
 531 #define SDRAM_BXCR_SDAM_3       0x00004000        /*   Mode 3                 */
 532 #define SDRAM_BXCR_SDAM_4       0x00006000        /*   Mode 4                 */
 533 #define SDRAM_BXCR_SDBE         0x00000001        /* Memory Bank Enable       */
 534
 535 /*-----------------------------------------------------------------------------+
 536   |  SDRAM TR0 Options
 537   +-----------------------------------------------------------------------------*/
 538 #define SDRAM_TR0_SDWR_MASK     0x80000000
 539 #define  SDRAM_TR0_SDWR_2_CLK   0x00000000
 540 #define  SDRAM_TR0_SDWR_3_CLK   0x80000000
 541 #define SDRAM_TR0_SDWD_MASK     0x40000000
 542 #define  SDRAM_TR0_SDWD_0_CLK   0x00000000
 543 #define  SDRAM_TR0_SDWD_1_CLK   0x40000000
 544 #define SDRAM_TR0_SDCL_MASK     0x01800000
 545 #define  SDRAM_TR0_SDCL_2_0_CLK 0x00800000
 546 #define  SDRAM_TR0_SDCL_2_5_CLK 0x01000000
 547 #define  SDRAM_TR0_SDCL_3_0_CLK 0x01800000
 548 #define SDRAM_TR0_SDPA_MASK     0x000C0000
 549 #define  SDRAM_TR0_SDPA_2_CLK   0x00040000
 550 #define  SDRAM_TR0_SDPA_3_CLK   0x00080000
 551 #define  SDRAM_TR0_SDPA_4_CLK   0x000C0000
 552 #define SDRAM_TR0_SDCP_MASK     0x00030000
 553 #define  SDRAM_TR0_SDCP_2_CLK   0x00000000
 554 #define  SDRAM_TR0_SDCP_3_CLK   0x00010000
 555 #define  SDRAM_TR0_SDCP_4_CLK   0x00020000
 556 #define  SDRAM_TR0_SDCP_5_CLK   0x00030000
 557 #define SDRAM_TR0_SDLD_MASK     0x0000C000
 558 #define  SDRAM_TR0_SDLD_1_CLK   0x00000000
 559 #define  SDRAM_TR0_SDLD_2_CLK   0x00004000
 560 #define SDRAM_TR0_SDRA_MASK     0x0000001C
 561 #define  SDRAM_TR0_SDRA_6_CLK   0x00000000
 562 #define  SDRAM_TR0_SDRA_7_CLK   0x00000004
 563 #define  SDRAM_TR0_SDRA_8_CLK   0x00000008
 564 #define  SDRAM_TR0_SDRA_9_CLK   0x0000000C
 565 #define  SDRAM_TR0_SDRA_10_CLK  0x00000010
 566 #define  SDRAM_TR0_SDRA_11_CLK  0x00000014
 567 #define  SDRAM_TR0_SDRA_12_CLK  0x00000018
 568 #define  SDRAM_TR0_SDRA_13_CLK  0x0000001C
 569 #define SDRAM_TR0_SDRD_MASK     0x00000003
 570 #define  SDRAM_TR0_SDRD_2_CLK   0x00000001
 571 #define  SDRAM_TR0_SDRD_3_CLK   0x00000002
 572 #define  SDRAM_TR0_SDRD_4_CLK   0x00000003
 573
 574 /*-----------------------------------------------------------------------------+
 575   |  SDRAM TR1 Options
 576   +-----------------------------------------------------------------------------*/
 577 #define SDRAM_TR1_RDSS_MASK     0xC0000000
 578 #define  SDRAM_TR1_RDSS_TR0     0x00000000
 579 #define  SDRAM_TR1_RDSS_TR1     0x40000000
 580 #define  SDRAM_TR1_RDSS_TR2     0x80000000
 581 #define  SDRAM_TR1_RDSS_TR3     0xC0000000
 582 #define SDRAM_TR1_RDSL_MASK     0x00C00000
 583 #define  SDRAM_TR1_RDSL_STAGE1  0x00000000
 584 #define  SDRAM_TR1_RDSL_STAGE2  0x00400000
 585 #define  SDRAM_TR1_RDSL_STAGE3  0x00800000
 586 #define SDRAM_TR1_RDCD_MASK     0x00000800
 587 #define  SDRAM_TR1_RDCD_RCD_0_0 0x00000000
 588 #define  SDRAM_TR1_RDCD_RCD_1_2 0x00000800
 589 #define SDRAM_TR1_RDCT_MASK     0x000001FF
 590 #define  SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
 591 #define  SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
 592 #define  SDRAM_TR1_RDCT_MIN     0x00000000
 593 #define  SDRAM_TR1_RDCT_MAX     0x000001FF
 594
 595 /*-----------------------------------------------------------------------------+
 596   |  SDRAM WDDCTR Options
 597   +-----------------------------------------------------------------------------*/
 598 #define SDRAM_WDDCTR_WRCP_MASK  0xC0000000
 599 #define  SDRAM_WDDCTR_WRCP_0DEG   0x00000000
 600 #define  SDRAM_WDDCTR_WRCP_90DEG  0x40000000
 601 #define  SDRAM_WDDCTR_WRCP_180DEG 0x80000000
 602 #define SDRAM_WDDCTR_DCD_MASK   0x000001FF
 603
 604 /*-----------------------------------------------------------------------------+
 605   |  SDRAM CLKTR Options
 606   +-----------------------------------------------------------------------------*/
 607 #define SDRAM_CLKTR_CLKP_MASK   0xC0000000
 608 #define  SDRAM_CLKTR_CLKP_0DEG    0x00000000
 609 #define  SDRAM_CLKTR_CLKP_90DEG   0x40000000
 610 #define  SDRAM_CLKTR_CLKP_180DEG  0x80000000
 611 #define SDRAM_CLKTR_DCDT_MASK   0x000001FF
 612
 613 /*-----------------------------------------------------------------------------+
 614   |  SDRAM DLYCAL Options
 615   +-----------------------------------------------------------------------------*/
 616 #define SDRAM_DLYCAL_DLCV_MASK  0x000003FC
 617 #define  SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 618 #define  SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 619
 620 /*-----------------------------------------------------------------------------+
 621   |  General Definition
 622   +-----------------------------------------------------------------------------*/
 623 #define DEFAULT_SPD_ADDR1       0x53
 624 #define DEFAULT_SPD_ADDR2       0x52
 625 #define MAXBANKS                4               /* at most 4 dimm banks */
 626 #define MAX_SPD_BYTES           256
 627 #define NUMHALFCYCLES           4
 628 #define NUMMEMTESTS             8
 629 #define NUMMEMWORDS             8
 630 #define MAXBXCR                 4
 631 #define TRUE                    1
 632 #define FALSE                   0
 633
 634 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 635         {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 636          0xFFFFFFFF, 0xFFFFFFFF},
 637         {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 638          0x00000000, 0x00000000},
 639         {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 640          0x55555555, 0x55555555},
 641         {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 642          0xAAAAAAAA, 0xAAAAAAAA},
 643         {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 644          0x5A5A5A5A, 0x5A5A5A5A},
 645         {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 646          0xA5A5A5A5, 0xA5A5A5A5},
 647         {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 648          0x55AA55AA, 0x55AA55AA},
 649         {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 650          0xAA55AA55, 0xAA55AA55}
 651 };
 652
 653 /* bank_parms is used to sort the bank sizes by descending order */
 654 struct bank_param {
 655         unsigned long cr;
 656         unsigned long bank_size_bytes;
 657 };
 658
 659 typedef struct bank_param BANKPARMS;
 660
 661 #ifdef CFG_SIMULATE_SPD_EEPROM
 662 extern unsigned char cfg_simulate_spd_eeprom[128];
 663 #endif
 664
 665 unsigned char spd_read(uchar chip, uint addr);
 666
 667 void get_spd_info(unsigned long* dimm_populated,
 668                   unsigned char* iic0_dimm_addr,
 669                   unsigned long  num_dimm_banks);
 670
 671 void check_mem_type
 672 (unsigned long* dimm_populated,
 673  unsigned char* iic0_dimm_addr,
 674  unsigned long  num_dimm_banks);
 675
 676 void check_volt_type
 677 (unsigned long* dimm_populated,
 678  unsigned char* iic0_dimm_addr,
 679  unsigned long  num_dimm_banks);
 680
 681 void program_cfg0(unsigned long* dimm_populated,
 682                   unsigned char* iic0_dimm_addr,
 683                   unsigned long  num_dimm_banks);
 684
 685 void program_cfg1(unsigned long* dimm_populated,
 686                   unsigned char* iic0_dimm_addr,
 687                   unsigned long  num_dimm_banks);
 688
 689 void program_rtr (unsigned long* dimm_populated,
 690                   unsigned char* iic0_dimm_addr,
 691                   unsigned long  num_dimm_banks);
 692
 693 void program_tr0 (unsigned long* dimm_populated,
 694                   unsigned char* iic0_dimm_addr,
 695                   unsigned long  num_dimm_banks);
 696
 697 void program_tr1 (void);
 698
 699 void program_ecc (unsigned long  num_bytes);
 700
 701 unsigned
 702 long  program_bxcr(unsigned long* dimm_populated,
 703                    unsigned char* iic0_dimm_addr,
 704                    unsigned long  num_dimm_banks);
 705
 706 /*
 707  * This function is reading data from the DIMM module EEPROM over the SPD bus
 708  * and uses that to program the sdram controller.
 709  *
 710  * This works on boards that has the same schematics that the AMCC walnut has.
 711  *
 712  * BUG: Don't handle ECC memory
 713  * BUG: A few values in the TR register is currently hardcoded
 714  */
 715
 716 long int spd_sdram(void) {
 717         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 718         unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 719         unsigned long total_size;
 720         unsigned long cfg0;
 721         unsigned long mcsts;
 722         unsigned long num_dimm_banks;               /* on board dimm banks */
 723
 724         num_dimm_banks = sizeof(iic0_dimm_addr);
 725
 726         /*
 727          * Make sure I2C controller is initialized
 728          * before continuing.
 729          */
 730         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 731
 732         /*
 733          * Read the SPD information using I2C interface. Check to see if the
 734          * DIMM slots are populated.
 735          */
 736         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 737
 738         /*
 739          * Check the memory type for the dimms plugged.
 740          */
 741         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 742
 743         /*
 744          * Check the voltage type for the dimms plugged.
 745          */
 746         check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 747
 748 #if defined(CONFIG_440GX)
 749         /*
 750          * Soft-reset SDRAM controller.
 751          */
 752         mtsdr(sdr_srst, SDR0_SRST_DMC);
 753         mtsdr(sdr_srst, 0x00000000);
 754 #endif
 755
 756         /*
 757          * program 440GP SDRAM controller options (SDRAM0_CFG0)
 758          */
 759         program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 760
 761         /*
 762          * program 440GP SDRAM controller options (SDRAM0_CFG1)
 763          */
 764         program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 765
 766         /*
 767          * program SDRAM refresh register (SDRAM0_RTR)
 768          */
 769         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 770
 771         /*
 772          * program SDRAM Timing Register 0 (SDRAM0_TR0)
 773          */
 774         program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 775
 776         /*
 777          * program the BxCR registers to find out total sdram installed
 778          */
 779         total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 780                                   num_dimm_banks);
 781
 782         /*
 783          * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 784          */
 785         mtsdram(mem_clktr, 0x40000000);
 786
 787         /*
 788          * delay to ensure 200 usec has elapsed
 789          */
 790         udelay(400);
 791
 792         /*
 793          * enable the memory controller
 794          */
 795         mfsdram(mem_cfg0, cfg0);
 796         mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
 797
 798         /*
 799          * wait for SDRAM_CFG0_DC_EN to complete
 800          */
 801         while (1) {
 802                 mfsdram(mem_mcsts, mcsts);
 803                 if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
 804                         break;
 805                 }
 806         }
 807
 808         /*
 809          * program SDRAM Timing Register 1, adding some delays
 810          */
 811         program_tr1();
 812
 813         /*
 814          * if ECC is enabled, initialize parity bits
 815          */
 816
 817         return total_size;
 818 }
 819
 820 unsigned char spd_read(uchar chip, uint addr)
 821 {
 822         unsigned char data[2];
 823
 824 #ifdef CFG_SIMULATE_SPD_EEPROM
 825         if (chip == CFG_SIMULATE_SPD_EEPROM) {
 826                 /*
 827                  * Onboard spd eeprom requested -> simulate values
 828                  */
 829                 return cfg_simulate_spd_eeprom[addr];
 830         }
 831 #endif /* CFG_SIMULATE_SPD_EEPROM */
 832
 833         if (i2c_probe(chip) == 0) {
 834                 if (i2c_read(chip, addr, 1, data, 1) == 0) {
 835                         return data[0];
 836                 }
 837         }
 838
 839         return 0;
 840 }
 841
 842 void get_spd_info(unsigned long*   dimm_populated,
 843                   unsigned char*   iic0_dimm_addr,
 844                   unsigned long    num_dimm_banks)
 845 {
 846         unsigned long dimm_num;
 847         unsigned long dimm_found;
 848         unsigned char num_of_bytes;
 849         unsigned char total_size;
 850
 851         dimm_found = FALSE;
 852         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 853                 num_of_bytes = 0;
 854                 total_size = 0;
 855
 856                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 857                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 858
 859                 if ((num_of_bytes != 0) && (total_size != 0)) {
 860                         dimm_populated[dimm_num] = TRUE;
 861                         dimm_found = TRUE;
 862 #if 0
 863                         printf("DIMM slot %lu: populated\n", dimm_num);
 864 #endif
 865                 } else {
 866                         dimm_populated[dimm_num] = FALSE;
 867 #if 0
 868                         printf("DIMM slot %lu: Not populated\n", dimm_num);
 869 #endif
 870                 }
 871         }
 872
 873         if (dimm_found == FALSE) {
 874                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 875                 hang();
 876         }
 877 }
 878
 879 void check_mem_type(unsigned long*   dimm_populated,
 880                     unsigned char*   iic0_dimm_addr,
 881                     unsigned long    num_dimm_banks)
 882 {
 883         unsigned long dimm_num;
 884         unsigned char dimm_type;
 885
 886         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 887                 if (dimm_populated[dimm_num] == TRUE) {
 888                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 889                         switch (dimm_type) {
 890                         case 7:
 891 #if 0
 892                                 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 893 #endif
 894                                 break;
 895                         default:
 896                                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 897                                        dimm_num);
 898                                 printf("Only DDR SDRAM DIMMs are supported.\n");
 899                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 900                                 hang();
 901                                 break;
 902                         }
 903                 }
 904         }
 905 }
 906
 907
 908 void check_volt_type(unsigned long*   dimm_populated,
 909                      unsigned char*   iic0_dimm_addr,
 910                      unsigned long    num_dimm_banks)
 911 {
 912         unsigned long dimm_num;
 913         unsigned long voltage_type;
 914
 915         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 916                 if (dimm_populated[dimm_num] == TRUE) {
 917                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 918                         if (voltage_type != 0x04) {
 919                                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 920                                        dimm_num);
 921                                 hang();
 922                         } else {
 923 #if 0
 924                                 printf("DIMM %lu voltage level supported.\n", dimm_num);
 925 #endif
 926                         }
 927                         break;
 928                 }
 929         }
 930 }
 931
 932 void program_cfg0(unsigned long* dimm_populated,
 933                   unsigned char* iic0_dimm_addr,
 934                   unsigned long  num_dimm_banks)
 935 {
 936         unsigned long dimm_num;
 937         unsigned long cfg0;
 938         unsigned long ecc_enabled;
 939         unsigned char ecc;
 940         unsigned char attributes;
 941         unsigned long data_width;
 942         unsigned long dimm_32bit;
 943         unsigned long dimm_64bit;
 944
 945         /*
 946          * get Memory Controller Options 0 data
 947          */
 948         mfsdram(mem_cfg0, cfg0);
 949
 950         /*
 951          * clear bits
 952          */
 953         cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 954                   SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 955                   SDRAM_CFG0_DMWD_MASK |
 956                   SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 957
 958
 959         /*
 960          * FIXME: assume the DDR SDRAMs in both banks are the same
 961          */
 962         ecc_enabled = TRUE;
 963         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 964                 if (dimm_populated[dimm_num] == TRUE) {
 965                         ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 966                         if (ecc != 0x02) {
 967                                 ecc_enabled = FALSE;
 968                         }
 969
 970                         /*
 971                          * program Registered DIMM Enable
 972                          */
 973                         attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 974                         if ((attributes & 0x02) != 0x00) {
 975                                 cfg0 |= SDRAM_CFG0_RDEN;
 976                         }
 977
 978                         /*
 979                          * program DDR SDRAM Data Width
 980                          */
 981                         data_width =
 982                                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 983                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 984                         if (data_width == 64 || data_width == 72) {
 985                                 dimm_64bit = TRUE;
 986                                 cfg0 |= SDRAM_CFG0_DMWD_64;
 987                         } else if (data_width == 32 || data_width == 40) {
 988                                 dimm_32bit = TRUE;
 989                                 cfg0 |= SDRAM_CFG0_DMWD_32;
 990                         } else {
 991                                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 992                                        data_width);
 993                                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 994                                 hang();
 995                         }
 996                         break;
 997                 }
 998         }
 999
1000         /*
1001          * program Memory Data Error Checking
1002          */
1003         if (ecc_enabled == TRUE) {
1004                 cfg0 |= SDRAM_CFG0_MCHK_GEN;
1005         } else {
1006                 cfg0 |= SDRAM_CFG0_MCHK_NON;
1007         }
1008
1009         /*
1010          * program Page Management Unit
1011          */
1012         cfg0 |= SDRAM_CFG0_PMUD;
1013
1014         /*
1015          * program Memory Controller Options 0
1016          * Note: DCEN must be enabled after all DDR SDRAM controller
1017          * configuration registers get initialized.
1018          */
1019         mtsdram(mem_cfg0, cfg0);
1020 }
1021
1022 void program_cfg1(unsigned long* dimm_populated,
1023                   unsigned char* iic0_dimm_addr,
1024                   unsigned long  num_dimm_banks)
1025 {
1026         unsigned long cfg1;
1027         mfsdram(mem_cfg1, cfg1);
1028
1029         /*
1030          * Self-refresh exit, disable PM
1031          */
1032         cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
1033
1034         /*
1035          * program Memory Controller Options 1
1036          */
1037         mtsdram(mem_cfg1, cfg1);
1038 }
1039
1040 void program_rtr (unsigned long* dimm_populated,
1041                   unsigned char* iic0_dimm_addr,
1042                   unsigned long  num_dimm_banks)
1043 {
1044         unsigned long dimm_num;
1045         unsigned long bus_period_x_10;
1046         unsigned long refresh_rate = 0;
1047         unsigned char refresh_rate_type;
1048         unsigned long refresh_interval;
1049         unsigned long sdram_rtr;
1050         PPC440_SYS_INFO sys_info;
1051
1052         /*
1053          * get the board info
1054          */
1055         get_sys_info(&sys_info);
1056         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1057
1058
1059         for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
1060                 if (dimm_populated[dimm_num] == TRUE) {
1061                         refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1062                         switch (refresh_rate_type) {
1063                         case 0x00:
1064                                 refresh_rate = 15625;
1065                                 break;
1066                         case 0x01:
1067                                 refresh_rate = 15625/4;
1068                                 break;
1069                         case 0x02:
1070                                 refresh_rate = 15625/2;
1071                                 break;
1072                         case 0x03:
1073                                 refresh_rate = 15626*2;
1074                                 break;
1075                         case 0x04:
1076                                 refresh_rate = 15625*4;
1077                                 break;
1078                         case 0x05:
1079                                 refresh_rate = 15625*8;
1080                                 break;
1081                         default:
1082                                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1083                                        dimm_num);
1084                                 printf("Replace the DIMM module with a supported DIMM.\n");
1085                                 break;
1086                         }
1087
1088                         break;
1089                 }
1090         }
1091
1092         refresh_interval = refresh_rate * 10 / bus_period_x_10;
1093         sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
1094
1095         /*
1096          * program Refresh Timer Register (SDRAM0_RTR)
1097          */
1098         mtsdram(mem_rtr, sdram_rtr);
1099 }
1100
1101 void program_tr0 (unsigned long* dimm_populated,
1102                   unsigned char* iic0_dimm_addr,
1103                   unsigned long  num_dimm_banks)
1104 {
1105         unsigned long dimm_num;
1106         unsigned long tr0;
1107         unsigned char wcsbc;
1108         unsigned char t_rp_ns;
1109         unsigned char t_rcd_ns;
1110         unsigned char t_ras_ns;
1111         unsigned long t_rp_clk;
1112         unsigned long t_ras_rcd_clk;
1113         unsigned long t_rcd_clk;
1114         unsigned long t_rfc_clk;
1115         unsigned long plb_check;
1116         unsigned char cas_bit;
1117         unsigned long cas_index;
1118         unsigned char cas_2_0_available;
1119         unsigned char cas_2_5_available;
1120         unsigned char cas_3_0_available;
1121         unsigned long cycle_time_ns_x_10[3];
1122         unsigned long tcyc_3_0_ns_x_10;
1123         unsigned long tcyc_2_5_ns_x_10;
1124         unsigned long tcyc_2_0_ns_x_10;
1125         unsigned long tcyc_reg;
1126         unsigned long bus_period_x_10;
1127         PPC440_SYS_INFO sys_info;
1128         unsigned long residue;
1129
1130         /*
1131          * get the board info
1132          */
1133         get_sys_info(&sys_info);
1134         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1135
1136         /*
1137          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1138          */
1139         mfsdram(mem_tr0, tr0);
1140         tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1141                  SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1142                  SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1143                  SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
1144
1145         /*
1146          * initialization
1147          */
1148         wcsbc = 0;
1149         t_rp_ns = 0;
1150         t_rcd_ns = 0;
1151         t_ras_ns = 0;
1152         cas_2_0_available = TRUE;
1153         cas_2_5_available = TRUE;
1154         cas_3_0_available = TRUE;
1155         tcyc_2_0_ns_x_10 = 0;
1156         tcyc_2_5_ns_x_10 = 0;
1157         tcyc_3_0_ns_x_10 = 0;
1158
1159         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1160                 if (dimm_populated[dimm_num] == TRUE) {
1161                         wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1162                         t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1163                         t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1164                         t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1165                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1166
1167                         for (cas_index = 0; cas_index < 3; cas_index++) {
1168                                 switch (cas_index) {
1169                                 case 0:
1170                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1171                                         break;
1172                                 case 1:
1173                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1174                                         break;
1175                                 default:
1176                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1177                                         break;
1178                                 }
1179
1180                                 if ((tcyc_reg & 0x0F) >= 10) {
1181                                         printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1182                                                dimm_num);
1183                                         hang();
1184                                 }
1185
1186                                 cycle_time_ns_x_10[cas_index] =
1187                                         (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1188                         }
1189
1190                         cas_index = 0;
1191
1192                         if ((cas_bit & 0x80) != 0) {
1193                                 cas_index += 3;
1194                         } else if ((cas_bit & 0x40) != 0) {
1195                                 cas_index += 2;
1196                         } else if ((cas_bit & 0x20) != 0) {
1197                                 cas_index += 1;
1198                         }
1199
1200                         if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1201                                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1202                                 cas_index++;
1203                         } else {
1204                                 if (cas_index != 0) {
1205                                         cas_index++;
1206                                 }
1207                                 cas_3_0_available = FALSE;
1208                         }
1209
1210                         if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1211                                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1212                                 cas_index++;
1213                         } else {
1214                                 if (cas_index != 0) {
1215                                         cas_index++;
1216                                 }
1217                                 cas_2_5_available = FALSE;
1218                         }
1219
1220                         if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1221                                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1222                                 cas_index++;
1223                         } else {
1224                                 if (cas_index != 0) {
1225                                         cas_index++;
1226                                 }
1227                                 cas_2_0_available = FALSE;
1228                         }
1229
1230                         break;
1231                 }
1232         }
1233
1234         /*
1235          * Program SD_WR and SD_WCSBC fields
1236          */
1237         tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
1238         switch (wcsbc) {
1239         case 0:
1240                 tr0 |= SDRAM_TR0_SDWD_0_CLK;
1241                 break;
1242         default:
1243                 tr0 |= SDRAM_TR0_SDWD_1_CLK;
1244                 break;
1245         }
1246
1247         /*
1248          * Program SD_CASL field
1249          */
1250         if ((cas_2_0_available == TRUE) &&
1251             (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1252                 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1253         } else if ((cas_2_5_available == TRUE) &&
1254                  (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1255                 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1256         } else if ((cas_3_0_available == TRUE) &&
1257                  (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1258                 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1259         } else {
1260                 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1261                 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1262                 printf("Make sure the PLB speed is within the supported range.\n");
1263                 hang();
1264         }
1265
1266         /*
1267          * Calculate Trp in clock cycles and round up if necessary
1268          * Program SD_PTA field
1269          */
1270         t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1271         plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1272         if (sys_info.freqPLB != plb_check) {
1273                 t_rp_clk++;
1274         }
1275         switch ((unsigned long)t_rp_clk) {
1276         case 0:
1277         case 1:
1278         case 2:
1279                 tr0 |= SDRAM_TR0_SDPA_2_CLK;
1280                 break;
1281         case 3:
1282                 tr0 |= SDRAM_TR0_SDPA_3_CLK;
1283                 break;
1284         default:
1285                 tr0 |= SDRAM_TR0_SDPA_4_CLK;
1286                 break;
1287         }
1288
1289         /*
1290          * Program SD_CTP field
1291          */
1292         t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1293         plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1294         if (sys_info.freqPLB != plb_check) {
1295                 t_ras_rcd_clk++;
1296         }
1297         switch (t_ras_rcd_clk) {
1298         case 0:
1299         case 1:
1300         case 2:
1301                 tr0 |= SDRAM_TR0_SDCP_2_CLK;
1302                 break;
1303         case 3:
1304                 tr0 |= SDRAM_TR0_SDCP_3_CLK;
1305                 break;
1306         case 4:
1307                 tr0 |= SDRAM_TR0_SDCP_4_CLK;
1308                 break;
1309         default:
1310                 tr0 |= SDRAM_TR0_SDCP_5_CLK;
1311                 break;
1312         }
1313
1314         /*
1315          * Program SD_LDF field
1316          */
1317         tr0 |= SDRAM_TR0_SDLD_2_CLK;
1318
1319         /*
1320          * Program SD_RFTA field
1321          * FIXME tRFC hardcoded as 75 nanoseconds
1322          */
1323         t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1324         residue = sys_info.freqPLB % (ONE_BILLION / 75);
1325         if (residue >= (ONE_BILLION / 150)) {
1326                 t_rfc_clk++;
1327         }
1328         switch (t_rfc_clk) {
1329         case 0:
1330         case 1:
1331         case 2:
1332         case 3:
1333         case 4:
1334         case 5:
1335         case 6:
1336                 tr0 |= SDRAM_TR0_SDRA_6_CLK;
1337                 break;
1338         case 7:
1339                 tr0 |= SDRAM_TR0_SDRA_7_CLK;
1340                 break;
1341         case 8:
1342                 tr0 |= SDRAM_TR0_SDRA_8_CLK;
1343                 break;
1344         case 9:
1345                 tr0 |= SDRAM_TR0_SDRA_9_CLK;
1346                 break;
1347         case 10:
1348                 tr0 |= SDRAM_TR0_SDRA_10_CLK;
1349                 break;
1350         case 11:
1351                 tr0 |= SDRAM_TR0_SDRA_11_CLK;
1352                 break;
1353         case 12:
1354                 tr0 |= SDRAM_TR0_SDRA_12_CLK;
1355                 break;
1356         default:
1357                 tr0 |= SDRAM_TR0_SDRA_13_CLK;
1358                 break;
1359         }
1360
1361         /*
1362          * Program SD_RCD field
1363          */
1364         t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1365         plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1366         if (sys_info.freqPLB != plb_check) {
1367                 t_rcd_clk++;
1368         }
1369         switch (t_rcd_clk) {
1370         case 0:
1371         case 1:
1372         case 2:
1373                 tr0 |= SDRAM_TR0_SDRD_2_CLK;
1374                 break;
1375         case 3:
1376                 tr0 |= SDRAM_TR0_SDRD_3_CLK;
1377                 break;
1378         default:
1379                 tr0 |= SDRAM_TR0_SDRD_4_CLK;
1380                 break;
1381         }
1382
1383 #if 0
1384         printf("tr0: %x\n", tr0);
1385 #endif
1386         mtsdram(mem_tr0, tr0);
1387 }
1388
1389 void program_tr1 (void)
1390 {
1391         unsigned long tr0;
1392         unsigned long tr1;
1393         unsigned long cfg0;
1394         unsigned long ecc_temp;
1395         unsigned long dlycal;
1396         unsigned long dly_val;
1397         unsigned long i, j, k;
1398         unsigned long bxcr_num;
1399         unsigned long max_pass_length;
1400         unsigned long current_pass_length;
1401         unsigned long current_fail_length;
1402         unsigned long current_start;
1403         unsigned long rdclt;
1404         unsigned long rdclt_offset;
1405         long max_start;
1406         long max_end;
1407         long rdclt_average;
1408         unsigned char window_found;
1409         unsigned char fail_found;
1410         unsigned char pass_found;
1411         unsigned long * membase;
1412         PPC440_SYS_INFO sys_info;
1413
1414         /*
1415          * get the board info
1416          */
1417         get_sys_info(&sys_info);
1418
1419         /*
1420          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1421          */
1422         mfsdram(mem_tr1, tr1);
1423         tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1424                  SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1425
1426         mfsdram(mem_tr0, tr0);
1427         if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1428             (sys_info.freqPLB > 100000000)) {
1429                 tr1 |= SDRAM_TR1_RDSS_TR2;
1430                 tr1 |= SDRAM_TR1_RDSL_STAGE3;
1431                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1432         } else {
1433                 tr1 |= SDRAM_TR1_RDSS_TR1;
1434                 tr1 |= SDRAM_TR1_RDSL_STAGE2;
1435                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1436         }
1437
1438         /*
1439          * save CFG0 ECC setting to a temporary variable and turn ECC off
1440          */
1441         mfsdram(mem_cfg0, cfg0);
1442         ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1443         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1444
1445         /*
1446          * get the delay line calibration register value
1447          */
1448         mfsdram(mem_dlycal, dlycal);
1449         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1450
1451         max_pass_length = 0;
1452         max_start = 0;
1453         max_end = 0;
1454         current_pass_length = 0;
1455         current_fail_length = 0;
1456         current_start = 0;
1457         rdclt_offset = 0;
1458         window_found = FALSE;
1459         fail_found = FALSE;
1460         pass_found = FALSE;
1461 #ifdef DEBUG
1462         printf("Starting memory test ");
1463 #endif
1464         for (k = 0; k < NUMHALFCYCLES; k++) {
1465                 for (rdclt = 0; rdclt < dly_val; rdclt++)  {
1466                         /*
1467                          * Set the timing reg for the test.
1468                          */
1469                         mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1470
1471                         for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1472                                 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1473                                 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1474                                         /* Bank is enabled */
1475                                         membase = (unsigned long*)
1476                                                 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1477
1478                                         /*
1479                                          * Run the short memory test
1480                                          */
1481                                         for (i = 0; i < NUMMEMTESTS; i++) {
1482                                                 for (j = 0; j < NUMMEMWORDS; j++) {
1483                                                         membase[j] = test[i][j];
1484                                                         ppcDcbf((unsigned long)&(membase[j]));
1485                                                 }
1486
1487                                                 for (j = 0; j < NUMMEMWORDS; j++) {
1488                                                         if (membase[j] != test[i][j]) {
1489                                                                 ppcDcbf((unsigned long)&(membase[j]));
1490                                                                 break;
1491                                                         }
1492                                                         ppcDcbf((unsigned long)&(membase[j]));
1493                                                 }
1494
1495                                                 if (j < NUMMEMWORDS) {
1496                                                         break;
1497                                                 }
1498                                         }
1499
1500                                         /*
1501                                          * see if the rdclt value passed
1502                                          */
1503                                         if (i < NUMMEMTESTS) {
1504                                                 break;
1505                                         }
1506                                 }
1507                         }
1508
1509                         if (bxcr_num == MAXBXCR) {
1510                                 if (fail_found == TRUE) {
1511                                         pass_found = TRUE;
1512                                         if (current_pass_length == 0) {
1513                                                 current_start = rdclt_offset + rdclt;
1514                                         }
1515
1516                                         current_fail_length = 0;
1517                                         current_pass_length++;
1518
1519                                         if (current_pass_length > max_pass_length) {
1520                                                 max_pass_length = current_pass_length;
1521                                                 max_start = current_start;
1522                                                 max_end = rdclt_offset + rdclt;
1523                                         }
1524                                 }
1525                         } else {
1526                                 current_pass_length = 0;
1527                                 current_fail_length++;
1528
1529                                 if (current_fail_length >= (dly_val>>2)) {
1530                                         if (fail_found == FALSE) {
1531                                                 fail_found = TRUE;
1532                                         } else if (pass_found == TRUE) {
1533                                                 window_found = TRUE;
1534                                                 break;
1535                                         }
1536                                 }
1537                         }
1538                 }
1539 #ifdef DEBUG
1540                 printf(".");
1541 #endif
1542                 if (window_found == TRUE) {
1543                         break;
1544                 }
1545
1546                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1547                 rdclt_offset += dly_val;
1548         }
1549 #ifdef DEBUG
1550         printf("\n");
1551 #endif
1552
1553         /*
1554          * make sure we find the window
1555          */
1556         if (window_found == FALSE) {
1557                 printf("ERROR: Cannot determine a common read delay.\n");
1558                 hang();
1559         }
1560
1561         /*
1562          * restore the orignal ECC setting
1563          */
1564         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1565
1566         /*
1567          * set the SDRAM TR1 RDCD value
1568          */
1569         tr1 &= ~SDRAM_TR1_RDCD_MASK;
1570         if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1571                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1572         } else {
1573                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1574         }
1575
1576         /*
1577          * set the SDRAM TR1 RDCLT value
1578          */
1579         tr1 &= ~SDRAM_TR1_RDCT_MASK;
1580         while (max_end >= (dly_val << 1)) {
1581                 max_end -= (dly_val << 1);
1582                 max_start -= (dly_val << 1);
1583         }
1584
1585         rdclt_average = ((max_start + max_end) >> 1);
1586         if (rdclt_average >= 0x60)
1587                 while (1)
1588                         ;
1589
1590         if (rdclt_average < 0) {
1591                 rdclt_average = 0;
1592         }
1593
1594         if (rdclt_average >= dly_val) {
1595                 rdclt_average -= dly_val;
1596                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1597         }
1598         tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1599
1600 #if 0
1601         printf("tr1: %x\n", tr1);
1602 #endif
1603         /*
1604          * program SDRAM Timing Register 1 TR1
1605          */
1606         mtsdram(mem_tr1, tr1);
1607 }
1608
1609 unsigned long program_bxcr(unsigned long* dimm_populated,
1610                            unsigned char* iic0_dimm_addr,
1611                            unsigned long  num_dimm_banks)
1612 {
1613         unsigned long dimm_num;
1614         unsigned long bank_base_addr;
1615         unsigned long cr;
1616         unsigned long i;
1617         unsigned long j;
1618         unsigned long temp;
1619         unsigned char num_row_addr;
1620         unsigned char num_col_addr;
1621         unsigned char num_banks;
1622         unsigned char bank_size_id;
1623         unsigned long ctrl_bank_num[MAXBANKS];
1624         unsigned long bx_cr_num;
1625         unsigned long largest_size_index;
1626         unsigned long largest_size;
1627         unsigned long current_size_index;
1628         BANKPARMS bank_parms[MAXBXCR];
1629         unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1630         unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1631
1632         /*
1633          * Set the BxCR regs.  First, wipe out the bank config registers.
1634          */
1635         for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1636                 mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
1637                 mtdcr(memcfgd, 0x00000000);
1638                 bank_parms[bx_cr_num].bank_size_bytes = 0;
1639         }
1640
1641 #ifdef CONFIG_BAMBOO
1642         /*
1643          * This next section is hardware dependent and must be programmed
1644          * to match the hardware.  For bammboo, the following holds...
1645          * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0
1646          * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1647          * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1648          * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1649          * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1650          */
1651         ctrl_bank_num[0] = 0;
1652         ctrl_bank_num[1] = 1;
1653         ctrl_bank_num[2] = 3;
1654 #else
1655         ctrl_bank_num[0] = 0;
1656         ctrl_bank_num[1] = 1;
1657         ctrl_bank_num[2] = 2;
1658         ctrl_bank_num[3] = 3;
1659 #endif
1660
1661         /*
1662          * reset the bank_base address
1663          */
1664         bank_base_addr = CFG_SDRAM_BASE;
1665
1666         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1667                 if (dimm_populated[dimm_num] == TRUE) {
1668                         num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1669                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1670                         num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1671                         bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1672
1673                         /*
1674                          * Set the SDRAM0_BxCR regs
1675                          */
1676                         cr = 0;
1677                         switch (bank_size_id) {
1678                         case 0x02:
1679                                 cr |= SDRAM_BXCR_SDSZ_8;
1680                                 break;
1681                         case 0x04:
1682                                 cr |= SDRAM_BXCR_SDSZ_16;
1683                                 break;
1684                         case 0x08:
1685                                 cr |= SDRAM_BXCR_SDSZ_32;
1686                                 break;
1687                         case 0x10:
1688                                 cr |= SDRAM_BXCR_SDSZ_64;
1689                                 break;
1690                         case 0x20:
1691                                 cr |= SDRAM_BXCR_SDSZ_128;
1692                                 break;
1693                         case 0x40:
1694                                 cr |= SDRAM_BXCR_SDSZ_256;
1695                                 break;
1696                         case 0x80:
1697                                 cr |= SDRAM_BXCR_SDSZ_512;
1698                                 break;
1699                         default:
1700                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1701                                        dimm_num);
1702                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1703                                        bank_size_id);
1704                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1705                                 hang();
1706                         }
1707
1708                         switch (num_col_addr) {
1709                         case 0x08:
1710                                 cr |= SDRAM_BXCR_SDAM_1;
1711                                 break;
1712                         case 0x09:
1713                                 cr |= SDRAM_BXCR_SDAM_2;
1714                                 break;
1715                         case 0x0A:
1716                                 cr |= SDRAM_BXCR_SDAM_3;
1717                                 break;
1718                         case 0x0B:
1719                                 cr |= SDRAM_BXCR_SDAM_4;
1720                                 break;
1721                         default:
1722                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1723                                        dimm_num);
1724                                 printf("ERROR: Unsupported value for number of "
1725                                        "column addresses: %d.\n", num_col_addr);
1726                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1727                                 hang();
1728                         }
1729
1730                         /*
1731                          * enable the bank
1732                          */
1733                         cr |= SDRAM_BXCR_SDBE;
1734
1735                         for (i = 0; i < num_banks; i++) {
1736                                 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1737                                         (4 * 1024 * 1024) * bank_size_id;
1738                                 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1739                         }
1740                 }
1741         }
1742
1743         /* Initialize sort tables */
1744         for (i = 0; i < MAXBXCR; i++) {
1745                 sorted_bank_num[i] = i;
1746                 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1747         }
1748
1749         for (i = 0; i < MAXBXCR-1; i++) {
1750                 largest_size = sorted_bank_size[i];
1751                 largest_size_index = 255;
1752
1753                 /* Find the largest remaining value */
1754                 for (j = i + 1; j < MAXBXCR; j++) {
1755                         if (sorted_bank_size[j] > largest_size) {
1756                                 /* Save largest remaining value and its index */
1757                                 largest_size = sorted_bank_size[j];
1758                                 largest_size_index = j;
1759                         }
1760                 }
1761
1762                 if (largest_size_index != 255) {
1763                         /* Swap the current and largest values */
1764                         current_size_index = sorted_bank_num[largest_size_index];
1765                         sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1766                         sorted_bank_size[i] = largest_size;
1767                         sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1768                         sorted_bank_num[i] = current_size_index;
1769                 }
1770         }
1771
1772         /* Set the SDRAM0_BxCR regs thanks to sort tables */
1773         for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1774                 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1775                         mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
1776                         temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1777                                                   SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1778                         temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1779                                 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1780                         mtdcr(memcfgd, temp);
1781                         bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1782                 }
1783         }
1784
1785         return(bank_base_addr);
1786 }
1787
1788 void program_ecc (unsigned long  num_bytes)
1789 {
1790         unsigned long bank_base_addr;
1791         unsigned long current_address;
1792         unsigned long end_address;
1793         unsigned long address_increment;
1794         unsigned long cfg0;
1795
1796         /*
1797          * get Memory Controller Options 0 data
1798          */
1799         mfsdram(mem_cfg0, cfg0);
1800
1801         /*
1802          * reset the bank_base address
1803          */
1804         bank_base_addr = CFG_SDRAM_BASE;
1805
1806         if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1807                 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1808                         SDRAM_CFG0_MCHK_GEN);
1809
1810                 if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1811                         address_increment = 4;
1812                 } else {
1813                         address_increment = 8;
1814                 }
1815
1816                 current_address = (unsigned long)(bank_base_addr);
1817                 end_address = (unsigned long)(bank_base_addr) + num_bytes;
1818
1819                 while (current_address < end_address) {
1820                         *((unsigned long*)current_address) = 0x00000000;
1821                         current_address += address_increment;
1822                 }
1823
1824                 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1825                         SDRAM_CFG0_MCHK_CHK);
1826         }
1827 }
1828
1829 #endif /* CONFIG_440 */
1830
1831 #endif /* CONFIG_SPD_EEPROM */